Search Results (27)

Arc-flash protective textiles are specialized technical fabrics designed to endure extreme thermal energy and inhibit ignition during electrical faults. It is an industry driven by the enhanced use of machine learning models, autonomous technologies, and advanced analytics. Key sectors, including healthcare, automotive, retail, financial services, and technology, are making considerable investments in high-quality training datasets to improve AI performance. Consequently, there is an escalating demand for scalable and accurate data annotation services. This review has as its main objective to demonstrate the recent advances on arc-flash protective textiles, including arc-flash environment, material failure mechanisms, structural design, performance characterization, and new materials breakthrough. Full article

Federated edge learning on microcontrollers (MCUs) enables privacy-preserving adaptation, but on-device training faces a hardware tradeoff: fitting backpropagation into a limited static random-access memory (SRAM) often relies on on-chip flash as auxiliary storage, while repeated parameter persistence rapidly consumes finite program/erase (P/E) endurance. This paper proposes TinySLFL, a flash-endurance-aware federated learning framework for resource-constrained MCUs. On the client, layer-wise training bounds the peak SRAM usage to one layer, and delayed aggregation keeps intermediate updates in SRAM so that each communication round incurs only one flash persistence. On the server, dynamic aggregation combines loss-aware freezing with proxy-accuracy-guided filtering to improve the robustness under non-independently and identically distributed (Non-IID) data while suppressing unnecessary rounds. Experiments on CIFAR-10 and SVHN under a severe Dirichlet label skew and on a naturally heterogeneous FEMNIST showed, in a server-side simulation, that TinySLFL reduces the cumulative protocol-level erase-block operations (EOs) required to reach a common target accuracy by 97.8–98.6% relative to sequential layer training (SLT) and improves the mean Top-1 accuracy by up to 5.24 percentage points over the same ResNet-8 backbone in a five-seed evaluation. The power, latency, SRAM, and deployment feasibility were reported from actual ESP32-S3 measurements. These results demonstrate durable federated learning for extreme-edge MCUs. Full article

Write amplification factor (WAF) is a critical performance and endurance bottleneck in flash-based solid-state drives (SSDs). Multi-streamed SSDs mitigate WAF by enabling logical data streams to be written separately, thereby improving the efficiency of garbage collection. However, despite the architectural potential of multi-streaming, prior research has largely overlooked the design of write buffer management schemes tailored to this model. In this paper, we propose a stream-aware block-level write buffer management technique that leverages both spatial and temporal locality to further reduce WAF. Although the write buffer operates at the granularity of pages, eviction is performed at the block level, where each block is composed exclusively of pages from the same stream. All pages and blocks are tracked using least recently used (LRU) lists at both global and per-stream levels. To avoid mixing data with disparate hotness and update frequencies, pages from the same stream are dynamically grouped into logical blocks based on their recency order. When space is exhausted, eviction is triggered by selecting a full block of pages from the cold region of the global LRU list. This strategy prevents premature eviction of hot pages and aligns physical block composition with logical stream boundaries. The proposed approach enhances WAF and garbage collection efficiency without requiring hardware modification or device-specific extensions. Experimental results confirm that our design delivers consistent performance and endurance improvements across diverse multi-streamed I/O workloads. Full article

The trend of decreasing endurance of flash memory makes the overall lifetime of SSDs more sensitive to the effects of wear leveling. Under these circumstances, we observe that existing wear-leveling techniques exhibit anomalous behavior under workloads without clear access skew or under dynamic access patterns and produce high write amplification, as high as 5.4×, negating its intended benefits. We argue that wear leveling is an artifact for maintaining the fixed-capacity abstraction of a storage device, and it becomes unnecessary if the exported capacity of the SSD is to gracefully reduce. We show that this idea of capacity variance extends the lifetime of the SSD, allowing up to 2.94× more writes under real workloads. Full article

As a critical storage technology, the material selection and structural design of flash memory devices are pivotal to their storage density and operational characteristics. Although van der Waals materials can potentially take over the scaling roadmap of silicon-based technologies, the scaling mechanisms and optimization principles at low-dimensional scales remain to be systematically unveiled. In this study, we experimentally demonstrated that the floating-gate length can significantly affect the memory window characteristics of memory devices. Experiments involving various floating-gate and tunneling-layer configurations, combined with TCAD simulations, were conducted to reveal the electrostatic coupling behaviors between floating gate and source/drain electrodes during shaping of the charge storage capabilities. Fundamental performance characteristics of the designed memory devices, including a large memory ratio (82.25%), good retention (>50,000 s, 8 states), and considerable endurance characteristics (>2000 cycles), further validate the role of floating-gate topological structures in manipulating low-dimensional memory devices, offering valuable insights to drive the development of next-generation memory technologies. Full article

This work investigates a new erase scheme in NAND flash memory to improve the lifetime and performance of modern solid-state drives (SSDs). In NAND flash memory, an erase operation applies a high voltage (e.g., >20 V) to flash cells for a long time (e.g., >3.5 ms), which degrades cell endurance and potentially delays user I/O requests. While a large body of prior work has proposed various techniques to mitigate the negative impact of erase operations, no work has yet investigated how erase latency and voltage should be set to fully exploit the potential of NAND flash memory; most existing techniques use a fixed latency and voltage for every erase operation, which is set to cover the worst-case operating conditions. To address this, we propose Revisiting Erase Operation, (REO) a new erase scheme that dynamically adjusts erase latency and voltage depending on the cells’ current erase characteristics. We design REO by two key apporaches. First, REO accurately predicts such near-optimal erase latency based on the number of fail bits during an erase operation. To maximize its benefits, REO aggressively yet safely reduces erase latency by leveraging a large reliability margin present in modern SSDs. Second, REO applies near-optimal erase voltage to each WL based on its unique erase characteristics. We demonstrate the feasibility and reliability of REO using 160 real 3D NAND flash chips, showing that it enhances SSD lifetime over the conventional erase scheme by 43% without change to existing NAND flash chips. Our system-level evaluation using eleven real-world workloads shows that an REO-enabled SSD reduces average I/O performance and read tail latency by 12% and 38%, respectivley, on average over a state-of-the-art technique. Full article

With the increasing requirements for chip data storage capabilities in fields such as automotive electronics and the Internet of Things, Flash memory is becoming more and more widely used. This paper presents a 512 KBytes Flash memory array with high reliability, high-speed reading, and high noise immunity. By regarding one bit of the dual-bit NORD structure as a dummy bit, we simplify the operation mode and obtain a wider cell current window. Meanwhile, this paper minimized the influence of supply voltage fluctuation on the comparison between cell current and reference current through the optimization of the sense amplifier circuit. We tested whether this array depicts a high-endurance performance under 25 °C and 85 °C, as well as high-speed reading up to 18 ns. This enhanced Flash memory is expected to bring inspiration for achieving high reliability and endurance in the automotive field under harsh operating conditions. Full article

With vertical stacking, 3D NAND’s flash memory can achieve continuous capacity growth. However, the endurance variation between the stacked layers becomes more and more significant due to process variation, which will lead to the underutilization of many pages and seriously affect the lifetime of 3D NAND’s flash memory. We investigated the endurance variation characteristics between layers and divided the stacked layers into the top, middle, and bottom layers according to the endurance characteristics. We found that the endurance of the bottom layer pages is much weaker than that of the other two layers, which is the primary factor that affects the lifetime of 3D NAND’s flash memory. In response to this endurance variation feature, we proposed a new layer-aware write strategy, called LA-Write. First of all, the write–skip unit in LA-Write will reduce the wear pressure of the pages through write–skip operations. Secondly, LA-Write maintains a layer-aware table, which stores the probability of pages in different layers performing the write–skip operation. Setting the probability of the bottom pages to the highest value will result in more write–skip operations on the bottom layers, mitigating endurance variations between layers. We carried out our experiments of LA-Write on DiskSim, a popular SSD simulator. Compared to existing schemes, experimental results show that LA-Write can greatly increase SSD’s lifetime. Full article

We aimed to fabricate reliable memory devices using HfO₂, which is gaining attention as a charge-trapping layer material for next-generation NAND flash memory. To this end, a new atomic layer deposition process using sequential remote plasma (RP) and direct plasma (DP) was designed to create charge-trapping memory devices. Subsequently, the operational characteristics of the devices were analyzed based on the thickness ratio of thin films deposited using the sequential RP and DP processes. As the thickness of the initially RP-deposited thin film increased, the memory window and retention also increased, while the interface defect density and leakage current decreased. When the thickness of the RP-deposited thin film was 7 nm, a maximum memory window of 10.1 V was achieved at an operating voltage of ±10 V, and the interface trap density (D_it) reached a minimum value of 1.0 × 10¹² eV⁻¹cm⁻². Once the RP-deposited thin film reaches a certain thickness, the ion bombardment effect from DP on the substrate is expected to decrease, improving the Si/SiO₂/HfO₂ interface and thereby enhancing device endurance and reliability. This study confirmed that the proposed sequential RP and DP deposition processes could resolve issues related to unstable interface layers, improve device performance, and enhance process throughput. Full article

This article investigates resistive random access memory (ReRAM) crossbar memory arrays, which is a notable development in non-volatile memory technology. We highlight ReRAM’s competitive edge over NAND, NOR Flash, and phase-change memory (PCM), particularly in terms of endurance, speed, and energy efficiency. This paper focuses on the architecture of crossbar arrays, where memristive devices are positioned at intersecting metal wires. We emphasize the unique resistive switching mechanisms of memristors and the challenges of sneak path currents and delve into the roles and configurations of selectors, particularly focusing on the one-selector one-resistor (1S1R) architecture with an insulator–metal transition (IMT) based selector. We use SPICE simulations based on defined models to examine a 3 × 3 1S1R ReRAM array with vanadium dioxide selectors and titanium dioxide film memristors, assessing the impact of ambient temperature and critical IMT temperatures on array performance. We highlight the operational regions of low resistive state (LRS) and high resistive state (HRS), providing insights into the electrical behavior of these components under various conditions. Lastly, we demonstrate the impact of selector presence on sneak path currents. This research contributes to the overall understanding of ReRAM crossbar arrays integrated with IMT material-based selectors. Full article

Ternary Content-Addressable Memory (TCAM) is used for storing the flow tables in software-defined networking (SDN)-based OpenFlow switches. However, the TCAM can store only a certain number of flow tables (8000). Moreover, when the switch flow tables need to be updated due to the link failure in the SDN, further updates may be lost due to the flow tables limit of the TCAM space. Hence, to resolve this issue, other memories need to be used in conjunction with TCAM to enhance the memory operations of TCAM. When considering which flash memory technology is to be used in conjunction with TCAM, we need to balance several factors to ensure optimal performance, speed, endurance, reliability, integration complexity, and cost-effectiveness. Hence, it leads to a multi-criteria decision-making problem regarding the selection of other memory technologies such as 3D XPoint, Magnetoresistive RAM, Resistive RAM, and Ferroelectric RAM. In this paper, we use the analytical network process (ANP) method to select the suitable technology in conjunction with TCAM, considering the features of the memory technologies for Software-Defined Internet-of-Things (SD-IoT). We provide a comprehensive numerical model leveraging the ANP to rank the memory technologies regarding their weights. The highest weights identify the most suitable technology for TCAM. We perform simulations to show the effectiveness of the mathematical model utilizing the ANP. The results show that the suggested methodology reduces the recovery delay, improves the packets received ratio (PRR), decreases the jitter, and increases the throughput. Full article

This study’s aim was to assess FreeStyle Libre Flash glucose monitoring (FGM) performance during an oral glucose tolerance test (OGTT) and treadmill exercise in healthy adolescents. This should advance the feasibility and utility of user-friendly technologies for metabolic assessments in adolescents. Seventeen healthy adolescents (nine girls aged 12.8 ± 0.9 years) performed an OGTT and submaximal and maximal treadmill exercise tests in a laboratory setting. The scanned interstitial fluid glucose concentration ([ISFG]) obtained by FGM was compared against finger-prick capillary plasma glucose concentration ([CPG]) at 0 (pre-OGTT), −15, −30, −60, −120 min post-OGTT, pre-, mid-, post- submaximal exercise, and pre- and post- maximal exercise. Overall mean absolute relative difference (MARD) was 13.1 ± 8.5%, and 68% (n = 113) of the paired glucose data met the ISO 15197:2013 criteria. For clinical accuracy, 84% and 16% of FGM readings were within zones A and B in the Consensus Error Grid (CEG), respectively, which met the ISO 15197:2013 criteria of having at least 99% of results within these zones. Scanned [ISFG] were statistically lower than [CPG] at 15 (−1.16 mmol∙L⁻¹, p < 0.001) and 30 min (−0.74 mmol∙L⁻¹, p = 0.041) post-OGTT. Yet, post-OGTT glycaemic responses assessed by total and incremental areas under the curve (AUCs) were not significantly different, with trivial to small effect sizes (p ≥ 0.084, d = 0.14–0.45). Further, [ISFGs] were not different from [CPGs] during submaximal and maximal exercise tests (interaction p ≥ 0.614). FGM can be a feasible alternative to reflect postprandial glycaemia (AUCs) in healthy adolescents who may not endure repeated finger pricks. Full article

Road pavements are spread over large areas and convey various possibilities for energy sources such as high thermal gradients due to their materials and colors, wind corridors, large flat areas for solar harvesting, and heavy loading from traffic. The latest advances in road energy generation have been discretely implemented and have mainly focused on photovoltaic surface applications; other studies have explored the use of piezoelectric transducers with high stresses for better energy-production performance but limited life span. This study explores the stresses on pavement surfaces from traffic loading shockwaves that yield to the natural frequency vibration a piezoelectric harvester using a cantilever array. The passing vehicles triggered 16 piezoelectric sensors divided into four embedded steel profiles. The peak electrical power obtained in the experiment was 55.6 µW with a single transducer using a tip mass of 16 g. The proposed harvester demonstrated potential for applications in micro-generation of energy with limited infrastructure modification and high endurance under traffic loading over time. Its generation capacity is around 50 mWh a month with 16 piezoelectric cantilevers installed (for a commercial traffic volume of 1500 vehicles a day), enough to power a 200 m flashing LED raised marker strip to guide drivers for lane alignment during night shifts. Full article

Charge-based memories, such as NAND flash and dynamic random-access memory (DRAM), have reached scaling limits and various next-generation memories are being studied to overcome their issues. Resistive random-access memory (RRAM) has advantages in structural scalability and long retention characteristics, and thus has been studied as a next-generation memory application and neuromorphic system area. In this paper, AlSiO_x, which was used as an alloyed insulator, was used to secure stable switching. We demonstrate synaptic characteristics, as well as the basic resistive switching characteristics with multi-level cells (MLC) by applying the DC sweep and pulses. Conduction mechanism analysis for resistive switching characteristics was conducted to understand the resistive switching properties of the device. MLC, retention, and endurance are evaluated and potentiation/depression curves are mimicked for a neuromorphic device. Full article

Flash memories are the preferred choice for data storage in portable gadgets. The charge trapping nonvolatile flash memories are the main contender to replace standard floating gate technology. In this work, we investigate metal/blocking oxide/high-k charge trapping layer/tunnel oxide/Si (MOHOS) structures from the viewpoint of their application as memory cells in charge trapping flash memories. Two different stacks, HfO₂/Al₂O₃ nanolaminates and Al-doped HfO₂, are used as the charge trapping layer, and SiO₂ (of different thickness) or Al₂O₃ is used as the tunneling oxide. The charge trapping and memory windows, and retention and endurance characteristics are studied to assess the charge storage ability of memory cells. The influence of post-deposition oxygen annealing on the memory characteristics is also studied. The results reveal that these characteristics are most strongly affected by post-deposition oxygen annealing and the type and thickness of tunneling oxide. The stacks before annealing and the 3.5 nm SiO₂ tunneling oxide have favorable charge trapping and retention properties, but their endurance is compromised because of the high electric field vulnerability. Rapid thermal annealing (RTA) in O₂ significantly increases the electron trapping (hence, the memory window) in the stacks; however, it deteriorates their retention properties, most likely due to the interfacial reaction between the tunneling oxide and the charge trapping layer. The O₂ annealing also enhances the high electric field susceptibility of the stacks, which results in better endurance. The results strongly imply that the origin of electron and hole traps is different—the hole traps are most likely related to HfO₂, while electron traps are related to Al₂O₃. These findings could serve as a useful guide for further optimization of MOHOS structures as memory cells in NVM. Full article