TinySLFL: A Flash-Endurance-Aware Federated Edge Learning Framework with Layer-Wise Delayed Aggregation for Resource-Constrained Microcontrollers

Federated edge learning on microcontrollers (MCUs) enables privacy-preserving adaptation, but on-device training faces a hardware tradeoff: fitting backpropagation into a limited static random-access memory (SRAM) often relies on on-chip flash as auxiliary storage, while repeated parameter persistence rapidly consumes finite program/erase (P/E) endurance. This paper proposes TinySLFL, a flash-endurance-aware federated learning framework for resource-constrained MCUs. On the client, layer-wise training bounds the peak SRAM usage to one layer, and delayed aggregation keeps intermediate updates in SRAM so that each communication round incurs only one flash persistence. On the server, dynamic aggregation combines loss-aware freezing with proxy-accuracy-guided filtering to improve the robustness under non-independently and identically distributed (Non-IID) data while suppressing unnecessary rounds. Experiments on CIFAR-10 and SVHN under a severe Dirichlet label skew and on a naturally heterogeneous FEMNIST showed, in a server-side simulation, that TinySLFL reduces the cumulative protocol-level erase-block operations (EOs) required to reach a common target accuracy by 97.8–98.6% relative to sequential layer training (SLT) and improves the mean Top-1 accuracy by up to 5.24 percentage points over the same ResNet-8 backbone in a five-seed evaluation. The power, latency, SRAM, and deployment feasibility were reported from actual ESP32-S3 measurements. These results demonstrate durable federated learning for extreme-edge MCUs.