Search Results (34)

In this work, a substrate-integrated waveguide (SIW) filtering power divider with a modified complementary split-ring resonator (CSRR) is reported. Firstly, by integrating the meander-shaped slots with the conventional CSRR, the proposed inner-meander-slot CSRR (IMSCSRR) can enlarge the total length of the defected slot and increase the width of the split, thus enhancing the equivalent capacitance and inductance. In this way, the fundamental resonant frequency of the IMSCSRR can be effectively decreased without enlarging the circuit size, which can generally help to reduce the physical size by over 35%. Subsequently, to further reduce the circuit size, two IMSCSRRs are separately loaded on the top and bottom metal covers to constitute a broadside-coupled IMSCSRR, which is combined with the SIW. To verify the efficacy of the proposed SIW-IMSCSRR unit cell, a two-way filtering power divider is implemented. It combines the band-selection function of a filter and the power-distribution property of a power divider, thereby enhancing system integration and realizing size compactness. Experimental results show that the proposed filtering power divider achieves a center frequency of 3.53 GHz, a bandwidth of about 320 MHz, an in-band insertion loss of (3 + 1.3) dB, an in-band isolation of over 21 dB, and a size reduction of about 30% compared with the design without broadside-coupling, as well as good magnitude and phase variations. All the results indicate that the proposed filtering power divider achieves a good balance between low loss, high isolation, and compact size, which is suitable for system integration applications in microwave scenarios. Full article

This paper investigates the capacitance characteristics of a glass-embedded interdigitated capacitive sensor (IDCS) for touch-sensing applications. The study analyzes both baseline (no-touch) and touch-induced capacitance variations through a combination of analytical modeling and experimental validation. A multilayer analytical model is first employed to calculate the baseline capacitance of the proposed structure, followed by experimental measurements for model verification. Subsequently, an equivalent circuit model of the touched state is introduced to represent the interaction between the human fingertip, sensor electrodes, and earth-ground, explaining the observed capacitance reduction during a finger touch. Sensor prototypes with electrode finger widths of 1.4, 2.0, 2.4, and 3.0 mm were fabricated within a 40 × 40 mm² sensing area. The baseline capacitance decreased from 28.6 pF at 1.4 mm to 12 pF at 3.0 mm electrode finger width, while the capacitance change upon touch ranged from 0.6–0.9 pF. Touch sensitivity for three test persons increased from about 1.7–4.6% at 1.4 mm to 5–7.6% at 3.0 mm electrode finger width. The results confirm that narrower-electrode designs yield higher absolute capacitance, whereas wider electrodes enhance touch sensitivity and provide greater uniformity within the defined sensing area. Overall, the findings validate the proposed IDCS configuration as a practical approach for realizing glass-integrated touch sensors and offer practical guidelines for optimizing electrode geometry in touch-based smart-glass applications. Full article

Integrated circuits have become indispensable in modern society owing to their formidable computational power and high integration, finding extensive applications in critical fields such as artificial intelligence and new energy vehicles. However, continued increases in integration density and reductions in physical size lead to a significantly higher heat flux density, thereby posing major challenges for thermal management and overall chip reliability. To address these thermal challenges, this study introduces an optimized manifold microchannel design. A three-dimensional conjugate heat transfer model was developed, and computational fluid dynamics simulations were performed to analyze the thermal–hydraulic performance. To mitigate temperature non-uniformity, several strategies were implemented: adjusting channel widths, employing uneven inlet gaps, and incorporating micro-fins. Results demonstrate that the optimized configuration achieves a maximum temperature reduction of 7.7 K, with peak thermal stress decreasing from 55.29 MPa to 47 MPa, effectively improving temperature uniformity. This study confirms that the proposed optimized design significantly enhances overall thermal performance, thereby offering a reliable and effective strategy for advanced chip thermal management. Full article

Active magnetic bearings (AMBs), pivotal in high-speed rotating machinery for their frictionless operation and precise control, demand power amplifiers with exceptional dynamic performance and minimal current ripple. However, conventional amplifier designs often overlook eddy current effects, a critical oversight given the high-frequency switching inherent to pulse-width modulation (PWM). These induced eddy currents distort output waveforms, amplify ripple, and degrade system bandwidth. This paper bridges this critical gap by proposing a comprehensive methodology to model, quantify, and mitigate eddy current impacts on three-level half-bridge power amplifiers. A novel mutual inductance-embedded circuit model was developed, integrating winding–eddy current interactions under PWM operations, while a discretized transfer function framework dissects frequency-dependent ripple amplification and phase hysteresis. A voltage selection criterion was analytically derived to suppress nonlinear distortions, ensuring stable operation in high-precision applications. A Simulink simulation model was established to verify the accuracy of the theoretical model. Experimental validation demonstrated a 212% surge in steady-state ripple (48 mA to 150 mA at 4 A DC bias) under a 20 kHz PWM operation, aligning with theoretical predictions. Dynamic load tests (400 Hz) showed a 6.28% current amplitude reduction at 80 V DC bus voltage compared to 40 V, highlighting bandwidth degradation. This research provides a paradigm for optimizing AMB power electronics, enhancing precision in next-generation high-speed systems. Full article

Distortions of electrocardiograms (ECGs) caused by mandatory high-pass and low-pass analog RC filters in ECG devices are always present. The fidelity of the ECG waveform requires limiting the RC cutoff frequencies of the diagnostic (0.05–150 Hz) and monitoring systems (0.5–40 Hz). However, the use of fixed frequency bands is a compromise between enhanced noise immunity and ECG distortions. This study aims to propose active inverse high-pass and low-pass filters which are able to compensate for distortions in digital recordings of RC-filtered ECGs, thereby overcoming the limitations imposed by analog filtering. A new straightforward design of an inverse high-pass filter (IHPF) uses an integrator as the forward-path gain block, with a feedback loop containing an active digital filter equivalent to the analog RC high-pass filter. In contrast, the inverse low-pass filter (ILPF) employs a constant-gain block in the forward path to ensure stability and prevent phase delay, while its feedback path features an active digital counterpart of the RC low-pass filter. Second-order inverse filters are created by cascading two first-order stages. The proposed filters were validated according to essential performance requirements for electrocardiographs. The low-frequency (impulse) responses of IHPFs with cutoff frequencies of 0.05–5 Hz exhibit no overshoot and undershoot by magnitudes of 0.1–25 µV, well within the ±100 µV compliance limit defined for a test rectangular pulse (3 mV, 100 ms). The high-frequency responses of ILPFs with cutoff frequencies of 10–150 Hz present a relative amplitude drop of only 0.2–2.5%, far below the 10% limit for peak amplitude reduction of a triangular pulse (1.5 mV) with 20 ms vs. 200 ms widths. For any of the eight ECG leads (I, II, and V1–V6) available in the standard signal (ANE20000), the IHPF (0.05–5 Hz) presents ST-segment deviations <5 μV (within the ±25 μV limit) and R- and S-peak deviations <±3.5% (within the ±5% limit). The ILPF (10–150 Hz) preserves R- and S-peak amplitudes with deviations less than −1%. Diagnostic-level recovery of ECG waveforms distorted by first- and second-order analog RC filters in ECG devices is possible with the innovative and comprehensive inverse filter design presented in this study. This approach offers a significant advancement in ECG signal processing, effectively restoring essential waveform components even after aggressive, noise-robust analog filtering in ECG acquisition circuits. Although validated for ECG signals, the proposed inverse filters are also applicable to other biosignal front-end circuits employing RC coupling. Full article

Power consumption in interconnects is a critical constraint on performance improvements in integrated circuits. This paper proposes a novel design methodology to minimize loss in interconnects and address this limitation. The approach incorporates air cavities within the substrate to lower the equivalent loss tangent, thereby reducing dielectric losses. Additionally, the inner conductor is engineered with a periodically nonuniform width to maintain stable effective characteristic impedance. To validate the effectiveness of the methodology, it is applied to both a substrate integrated coaxial line (SICL) and a stripline. Simulation results reveal a 9.76% reduction in loss for the SICL and a 19.40% reduction in loss for the stripline, demonstrating significant improvements with wide tolerance. Furthermore, this design methodology can be generalized to other interconnect types, offering the potential for additional power savings. Full article

In order to achieve high accuracy in interferometric direction-finding systems, antennas with a stable phase center in the working bandwidth are required. This article proposes a miniaturized loaded open-boundary quad-ridge horn (LOQRH) antenna with dimensions of 40 mm × 40 mm × 49 mm. First, to stabilize the phase center of the antenna, the design builds on the foundation of a quad-ridge horn antenna, where measures such as optimizing the ridge structure and introducing resistive loading were implemented to achieve size reduction. Second, electrically small-sized antennas are more susceptible to the effects of common-mode currents (CMCs), which can reduce the symmetry of the radiation pattern and the stability of the phase center. To avoid the generation of common-mode currents during operation, a self-balanced feed structure was introduced into the proposed antenna design. This structure establishes a balanced circuit and routes the feedline at the voltage null point, effectively suppressing the common-mode current. As a result, the miniaturization of the LOQRH antenna was achieved while ensuring the suppression of the common-mode current, thereby maintaining the stability of the antenna’s electromagnetic performance. The measured results show that the miniaturized antenna has a small phase center change of less than 20.3 mm within 2–18 GHz, while the simulated phase center fluctuation is only 14.6 mm. In addition, when taking 18.5 mm in front of the antenna’s feed point as the phase center, the phase fluctuation is less than 22.5° within the required beam width. Along with the desired stable phase center, the miniaturized design makes the proposed antenna suitable for interferometric direction-finding systems. Full article

Ultra-low-voltage design brings considerable outcomes in power reduction and energy efficiency improvement at the cost of performance degradation and uncertainty. Conventional standard cell design methodology cannot guarantee optimal performance for subthreshold operations due to the lack of consideration of process variation. In this paper, an effective subthreshold cell sizing method is proposed to minimize the worst-case propagation delay by deriving the optimal pMOS-to-nMOS width ratio (β) analytically, which reveals the relation between the minimal worst-case delay and the process parameters and provides distinct guidance for standard cell library design. The proposed method demonstrated good agreement with the Monte Carlo SPICE simulation results and was validated at the cell level and the circuit level. At the cell level, the logic cells designed with the proposed method show at least 8.6% and 7.4% improvement, on average, for worst-case delay and energy-delay product (EDP), respectively, with an additional 3.2% energy overhead compared to the prior approaches. At the circuit level, the proposed method improves the worst-case performance and worst-case EDP of the ring oscillator by at least 15.5% and 15.0%, respectively, with a 0.9% energy penalty. Moreover, the ISCAS’89 and OpenCores circuits synthesized with the optimized cells achieve at least 6.6% worst-case performance enhancement, 6.9% power reduction, and 9.4% area saving. Full article

In analyzing the decoupling of emissions from economic growth, current literature foregoes the nonlinear complexities of macroeconomic systems, leading to ineffective energy transition policies, specifically for developing countries. This study focuses on the Indian energy–economy–emission nexus to establish a control system that internalizes inflation, trade openness, and fossil fuel imports with economic growth and macro-emissions to visualize the complex pathways of decoupling. Through long-term cointegration and vector error correction modeling, it was found that GDP and energy affect capital, inflation and energy imports, which are locked in a long-run negative feedback loop that ultimately increases emissions. Capital growth enables decoupling at 0.7% CO₂ emissions reduction for every 1% capital growth, while 1% inflation growth inhibits decoupling by increasing CO₂ emissions by 0.8%. A cybernetic fractional circuit of R-C elements and operational amplifiers was utilized to examine the delay of pulses from GDP to the loop elements, which revealed that capital is periodic with GDP pulses. However, inflation, being aperiodic with the clock pulses of GDP, causes the pulse-width of capital to decrease and fossil fuel imports to increase. Through the circuital model, it was possible to determine the exact policy intervention schedule in business cycle growth and recession phases that could build clean energy capital and limit inflation-induced recoupling. Full article

This paper presents an optimized quantum circuit for the $scrypt$ cryptographic algorithm. We applied various optimization techniques to reduce the DW cost, which is the product of the time and space complexity of quantum circuits. In our proposed method, the number of ancilla qubits was significantly reduced through the use of optimized inverse operations, while the depth was minimized by implementing parallel structures. For the SHA-256, we devised a structure that achieves a substantial reduction in the number of ancilla qubits with only a slight increase in quantum circuit depth. By cleaning the dirty ancilla qubits used in the previous round through inverse operations, we enabled their reuse in each subsequent round. Specifically, we reduced the number of 8128 ancilla qubits, achieving this with an increase of only 6 in the full depth of the quantum circuit. Additionally, within Salsa20/8 in SMix, we reused qubits through inverse operations and performed some operations in parallel to reduce both the number of qubits and the overall quantum circuit depth. Finally, our quantum circuit for $scrypt$ demonstrates a significant reduction in the width (the number of qubits) with only a minimal increase in the full quantum circuit depth. Full article

The escalating component density in radio frequency (RF) systems presents a growing challenge related to the coupling of adjacent microstrip lines in high-density printed circuit boards (PCBs). As a result, to tackle this prominent issue, there is a continuous pursuit of innovative techniques to effectively minimize the coupling effects among closely spaced microstrip lines. This paper proposes a reduction in the coupling of adjacent lines by utilizing a coating (stiffener) layer, which is commonly used in rigid-flex PCB fabrication. For this purpose, a reference 50 Ohm coupled line performance was compared to three coupled lines with track widths of 1.39 mm, 1.30 mm, and 1.25 mm, respectively, all at a fixed distance between the tracks. These decreasing widths were used to achieve the same 50 Ohm impedance for the coupled lines when covered with different coating layers. Each of these three coupled lines was covered with different coating (stiffener) layers, measuring 0.1 mm, 0.3 mm, and 0.5 mm in thickness, respectively. The manufactured device under test (DUT) structures underwent time-domain reflectometry (TDR) and S-parameter measurements. The TDR measurements of the DUT structures with coating layers demonstrated excellent conformity to the 50 Ohm reference coupled line. Meanwhile, the S21 measurements indicated a significant decrease in the crosstalk. For example, for a coating layer thickness of 0.3 mm, the crosstalk decreased by approximately 5–6 dB within the frequency range up to 5 GHz. When the coating layer thickness was 0.5 mm, the crosstalk decreased by approximately 10 dB or more. Full article

This research article presents a modified novel crisscross augmented ladder (CCAL) structured multilevel inverter (MLI). MLIs can be operated in symmetric and asymmetric binary and ternary voltage ratios. The modified structure comprises a generalized unit (CCAL) and an extendable structure; this structure can be extended to generate more stair case waveform. The foremost benefit of this modified structure is to curb the conduction path of active switches. The utilized structure uses only four active conduction paths in all modes. However, an MLI has complexity, such as a higher number of switches and bulky controlling driver circuits which need superior controls. This article suggests a prominent solution for the above issues. The subtle CCAL is a governed multicarrier pulse width modulation scheme with the savvy fuzzy logic controller and, therefore, added benefits, such as lower switch stress, lower switching loss, and lower dv/dt stress. Hitherto, many topologies are emerging to curb the component count reduction structure; among them it is an attempt to curtail the active conduction path. The working capability of the presented system is substantiated with a simulation study carried out in MATLAB R2017a and viability hardware (Xilinx FPGA) proof of concept to validate the effectiveness. Full article

Currently, there is a need to increase the density of interconnections on printed circuit boards (PCBs). Does this mean that the only option for quality PCB manufacturing is to proportionally increase precision of equipment, or is there another way? One of the main constraints on increasing the density of PCB interconnections is posed by the transition holes. As the number of conductive layers increases, the number of vias increases and they cover a significant space on the PCB. On the other hand, reducing the size of the vias is limited by the capability of spatial alignment of the PCB stack during manufacturing. There are standards that set limits for the design of contact pads on a PCB (IPC-A-600G, IPC-6012B). However, depending on the precision of production, the contact pads may be of poor quality. This raises the issue of determining the reliability of a contact pad with defined parameters at the design stage, taking into account manufacturing capabilities. This research proposes an analytical method for evaluation of reliability of a via or plated through-hole based on calculation of its probability of production in accordance with the current standards. On the basis of the method, a model was developed both for the case of a contact pad without any conductors connected to it (nonfunctional contact pad) and for the real case with a connected conductor. The model estimates the probability of making an acceptable via for a given reliability class depending on parameters such as the conductor width (minimum permissible and usable), drilled hole diameter, and pad diameter, as well as the accuracy of the drilling operation. The analysis of the modeling results showed that for the real case, a reduction in the reliability class would insignificantly affect the probability of making an acceptable via due to the tight limitation on the connection place of the conductor and the contact pad. In conclusion, we propose an algorithm for determining the optimal parameters of teardrops to minimize the negative impact of the conductor on the reliability of the vias. Full article

As quantum computing technology continues to develop, the need for research into novel quantum algorithms is growing. However, such algorithms cannot yet be reliably tested on actual quantum hardware, which is still limited in several ways, including qubit coherence times, connectivity, and available qubits. To facilitate the development of novel algorithms despite this, simulators on classical computing systems are used to verify the correctness of an algorithm, and study its behaviour under different error models. In general, this involves operating on a memory space that grows exponentially with the number of qubits. In this work, we introduce quantum circuit transformations that allow for the construction of parameterised circuits for quantum algorithms. The parameterised circuits are in an ideal form to be processed by quantum compilation tools, such that the circuit can be partially evaluated prior to simulation, and a smaller specialised circuit can be constructed by eliminating fixed input qubits. We show significant reduction in the number of qubits for various quantum arithmetic circuits. Divide-by-n-bits quantum integer dividers are used as an example demonstration. It is shown that the complexity reduces from $4n+2$ to $3n+2$ qubits in the specialised versions. For quantum algorithms involving divide-by-8 arithmetic operations, a reduction by $2^8=256$ in required memory is achieved for classical simulation, reducing the memory required from 137 GB to 0.53 GB. Full article

The high-repeat frequency ultrafast electrical pulse generation technology is mainly based on ultrafast switching devices combined with ultrafast circuits to generate electrical pulses with repetition frequencies of several kilohertz and a rise-time of nanoseconds or even picoseconds. This technology is the basis for several research studies and is one of the key technologies that has received wide attention from various countries. The problems to be solved are high re-frequency ultrafast high-voltage pulse generation and ultra-broadband ultrafast pulse transport and circuit stability applicability, which include circuit conduction mechanism research, pulse generation time improvement and recovery time reduction. By studying the avalanche transistor high-voltage transient conduction characteristics and reducing the loss in the carrier transport process, the influence of each parameter on the output is determined, and the key factors to enhance the circuit performance are identified. This paper designs a new high-repetition frequency ultrafast electric pulse generation (UPG) circuit using pure electronics components, which consists of combining avalanche transistor model 2N2222 with a hybrid Marx structure at the same time in the pulse circuit to add filtering, fast recovery diodes and pulse cutoff and other matching techniques to make its output more stable, which can obtain higher output frequency, faster rise-time and narrower pulse widths. It has been tested that a high re-frequency ultrafast high-voltage electrical pulse signal with a pulse repetition frequency of 200 kHz, a leading edge of 800 ps, a half-high pulse width of 5 ns, an amplitude of 1.2 kV and jitter of less than 5% can be generated at the load with a 50 Ω load at the output. The signal can be applied in the fields of ultrafast diagnosis, information countermeasures and nuclear electromagnetic radiation research. Full article