Search Results (117)

The rapid growth of 5G necessitates wireless receivers capable of high-speed, low-latency communication under complex channel conditions. Traditional receivers struggle with the performance–complexity trade-off in massive MIMO systems, where linear detectors underperform and maximum likelihood (ML) detection becomes computationally prohibitive. Deep-learning-based model-driven approaches have demonstrated a favorable balance between detection performance and computational cost. However, despite their algorithmic promise, the transition of these learned detectors into practical, real-time systems is critically hampered by inefficient hardware mapping, resulting in suboptimal throughput, high resource overhead, and limited scalability. To bridge this gap, this paper presents LwAMP-Net, a dedicated FPGA accelerator for a lightweight learned AMP detector. We propose a modular and multi-mode hardware architecture for LwAMP-Net, featuring an outer-product-based dataflow that mitigates pipeline stalls and multi-mode processing elements that adapt to diverse computation patterns. These innovations jointly enhance computational parallelism and resource utilization on the FPGA. Implemented on a Xilinx XC7VX690T FPGA for a 128 × 8 MIMO system with 16QAM, the accelerator achieves a 49.2% higher normalized throughput per iteration, an 85.4% improvement in throughput per LUT slice, and a 12.7% improvement in throughput per DSP compared to the state-of-the-art methods. This work provides a complete architectural solution for deploying high-performance, hardware-efficient learned MIMO detectors in real-world systems. Full article

This paper studies a MuJoCo-based locomotion framework that couples an adaptive-frequency central pattern generator (AFCO-CPG) with single rigid-body dynamics model predictive control (MPC) for the RENS Q1 quadruped with elastic parallel knee joints. AFCO-CPG combines multi-scale phase coordination, saturated phase correction, and load-gated feedback, while MPC supplies feasible ground-reaction forces and returns load cues to the timing layer. In MuJoCo, the controller achieves stable diagonal-trot speed tracking from 0.4 to 1.2 m/s and recovers from short external pushes. A matched elastic-versus-rigid timing sweep shows a favorable flat-ground parameter band around $\omega =1.8$ Hz, with a best-case cost-of-transport reduction of 12.83% for the elastic model under identical controller gains. A flat-to-slope ascent case further verifies that AFCO timing is modulated when load conditions change. Ablation across nine controller variants shows that multi-scale coordination is the dominant component, causing a 135% increase in phase error and a 536% increase in recovery time when removed. A reduced-order early/late-contact benchmark further confirms faster re-locking than diagonal-only and minimal variants. The results support the value of combining neural timing, predictive force optimization, and compliant-leg feedback in high-fidelity simulation, while hardware validation remains future work. Full article

Heterogeneous multi-core systems (HMCSs) typically face a dilemma: heuristics (e.g., Linux CFS) are fast but blind to global constraints, while meta-heuristics (e.g., GAs) are globally optimal but too slow for real-time OS interaction. To bridge this gap without relying on “black-box” neural networks, we introduce the Tissue P System-Inspired Task Allocator (TPSTA). By mapping HMCS and parallel task scheduling to Tissue P System models and vectorized linear algebra problems, TPSTA achieves a computational complexity of $\mathrm{O}\left(\mathrm{M}/\mathrm{W}\right)$, effectively compressing the decision space. Our rigorous evaluation across four dimensions reveals a system strictly bound by physical constraints rather than algorithmic heuristics. (1) Under sufficient resource provisioning (four chips), TPSTA achieves a 0.00% Deadline Miss Ratio (DMR). Crucially, stress tests on constrained hardware (two chips) show graceful degradation to a 12.88% DMR, matching the optimal theoretical bound of EDF, whereas standard heuristics collapse to failure rates > 68%. On a massive 4096-core cluster, TPSTA outperforms the Linux GTS scalar baseline by 14.4×, maintaining low latency where traditional algorithms fail (>8 s). (3) Adaptability: The system demonstrates adaptive routing in handling hardware heterogeneity; without explicit rule-coding, it autonomously prioritizes data locality during NUMA transfers and migrates compute-bound tasks during thermal throttling events. (4) Physical Limits: Finally, our roofline analysis confirms that while the algorithmic speedup is theoretically linear, practical performance saturates at ~375× due to the Memory Wall, validating the isomorphism between synaptic bandwidth and hardware memory channels. Full article

As distributed terminals are increasingly integrated into modern power systems with high penetration of renewable energy and decentralized resources, access control mechanisms must support continuous and highly detailed trust assessment. Existing approaches based on machine learning primarily rely on network traffic features from a single source and analyze terminals in isolation, which limits their ability to capture complex device states and correlated attack behaviors. This paper presents a trust assessment framework for distributed power grid terminals that combines multidimensional behavioral modeling with dual domain graph neural networks. Behavioral features are collected from network traffic, runtime environment, and hardware or kernel events and are fused into compact representations through a variational autoencoder to mitigate redundancy and reduce computational overhead. Based on the fused features and observed communication relationships, two graphs are constructed in parallel: a feature domain graph reflecting behavioral similarity and a topological domain graph capturing communication structure between terminals. Graph convolution is performed in both domains to jointly model individual behavioral risk and correlation across terminals. A fusion mechanism based on attention is further introduced to adaptively integrate embeddings specific to each domain, together with a loss function that enforces both shared and complementary representations across domains. Experiments conducted on the CIC EV Charger Attack Dataset 2024 show that the proposed framework achieves a classification accuracy of 96.84%, while maintaining a recall rate above 95% for the low trust category. These results indicate that incorporating multidimensional behavior perception and dual domain relational modeling improves trust assessment performance for distributed power grid terminals under complex attack scenarios. Full article

Distributed fiber optic sensing (DFOS) has emerged as a critical technology for structural health monitoring of large-scale infrastructure, offering unique advantages in terms of coverage and environmental adaptability. This review presents a comprehensive analysis of the two dominant technical routes: fully distributed sensing based on intrinsic backscattering and massive-capacity sensing based on ultra-weak fiber Bragg grating (UWFBG) networks. For backscattering-based systems—encompassing Raman, Brillouin, and Rayleigh scattering—the inherent trade-offs among signal-to-noise ratio (SNR), spatial resolution, and sensing range constitute major performance bottlenecks. This review systematically summarizes advanced demodulation and signal processing strategies designed to overcome these physical barriers, including pulse coding sequences, chaotic laser compressed correlation, and deep learning-enhanced noise reduction algorithms. In parallel, for UWFBG-based technologies, the evolution from traditional multiple-point fiber Bragg grating (FBG) array to quasi-distributed and fully distributed UWFBG network is discussed. This review highlights key breakthroughs in achieving high spatial resolution and high-speed interrogation through hybrid multiplexing, aliased spectrum reconstruction, and dispersion-based demodulation techniques. By synthesizing recent advances in modulation schemes, detection hardware, and algorithmic processing, this paper outlines the trajectory of DFOS technologies toward high-precision, long-distance, and real-time sensing networking. Full article

Real-time object detection on resource-constrained edge devices remains a critical challenge in precision agriculture and autonomous systems, particularly when integrating advanced multi-modal sensors (RGB-D, thermal, hyperspectral). This paper introduces FEGW-YOLO, a lightweight detection framework explicitly designed to bridge the efficiency-accuracy gap for fine-grained visual perception on edge hardware while maintaining compatibility with multiple sensor modalities. The core innovation is a Feature Complexity Descriptor (FCD) metric that enables adaptive, layer-wise compression based on the information-bearing capacity of network features. This compression-guided approach is coupled with (1) Feature Engineering-driven Ghost Convolution (FEG-Conv) for parameter reduction, (2) Efficient Multi-Scale Attention (EMA) for compensating compression-induced information loss, and (3) Wise-IoU loss for improved localization in dense, occluded scenes. The framework follows a principled “Compress, Compensate, and Refine” philosophy that treats compression and compensation as co-designed objectives rather than isolated knobs. Extensive experiments on a custom strawberry dataset (11,752 annotated instances) and cross-crop validation on apples, tomatoes, and grapes demonstrate that FEGW-YOLO achieves 95.1% mAP@0.5 while reducing model parameters by 54.7% and computational cost (GFLOPs) by 53.5% compared to a strong YOLO-Agri baseline. Real-time inference on NVIDIA Jetson Xavier achieves 38 FPS at 12.3 W, enabling 40+ hours of continuous operation on typical agricultural robotic platforms. Multi-modal fusion experiments with RGB-D sensors demonstrate that the lightweight architecture leaves sufficient computational headroom for parallel processing of depth and visual data, a capability essential for practical advanced sensing systems. Field deployment in commercial strawberry greenhouses validates an 87.3% harvesting success rate with a 2.1% fruit damage rate, demonstrating feasibility for autonomous systems. The proposed framework advances the state-of-the-art in efficient agricultural sensing by introducing a principled metric-guided compression strategy, comprehensive multi-modal sensor integration, and empirical validation across diverse crop types and real-world deployment scenarios. This work bridges the gap between laboratory research and practical edge deployment of advanced sensing systems, with direct relevance to autonomous harvesting, precision monitoring, and other resource-constrained agricultural applications. Full article

Parallel inverter systems constitute the fundamental units of AC microgrids and distributed renewable energy generation systems, wherein accurate power sharing among units represents a critical challenge for stable operation. Conventional droop control fails to share the harmonic power in proportionality to the capacity of inverters due to disparities on line impedance, leading to circulating currents, degraded power quality, and reduced system load capability. To address these issues, this paper proposes a harmonic power-sharing control strategy based on perturbative virtual impedance injection. Under the premise that fundamental power sharing according to capacity ratios has been ensured, the strategy first converts the harmonic power information of each inverter into a small-signal perturbation, which is injected into the virtual impedance of its fundamental control loop. Subsequently, by detecting the resulting variations in fundamental power coefficients induced by this perturbation, a closed-loop feedback is constructed to adaptively adjust the virtual impedance value of each inverter at harmonic frequencies. This adjustment enables the automatic matching of the harmonic power distribution ratio to the inverter capacity ratio, ultimately achieving precise harmonic power sharing. The proposed strategy operates without requiring inter-unit communication links or sampling the voltage at the common coupling point, relying solely on local information, thereby enhancing system reliability. Finally, the effectiveness of the proposed control strategy in achieving harmonic power sharing under conditions of line impedance mismatch is validated through an RT-LAB hardware-in-the-loop platform. Full article

High-speed electrical wireline links, spanning Serializer/Deserializer backplanes and cables, chip-to-chip and die-to-die interfaces, wide-parallel single-ended (SE) buses, and simultaneous-bidirectional (SBD) buses, increasingly operate under severe insertion loss, long channel memory, and strong multi-lane interference. Equalization is therefore a central enabler for reliable symbol recovery in the presence of inter-symbol interference (ISI), echo, and near-/far-end crosstalk. This review synthesizes recent principles, architectures, and silicon-proven implementations of wireline equalizers with an emphasis on practical hardware constraints. It further organizes key research trajectories in high-speed wireline communications across three domains: (i) Time-domain equalization and detection for ISI-limited channels, spanning feed-forward equalizers, latency-relaxed decision-feedback equalization architectures that mitigate stringent feedback-loop constraints, and partial-response signaling combined with reduced-complexity maximum-likelihood sequence detection to enhance resilience against extended channel memory. (ii) Advanced modulation and frequency-domain processing, marking the transition from conventional 4-level pulse-amplitude modulation toward higher-order constellations and multicarrier techniques, notably discrete multitone and orthogonal frequency-division multiplexing, which necessitates modulation-aware frequency-domain equalization and adaptive bit- and power-loading algorithms. (iii) Crosstalk and echo mitigation for dense SE and SBD systems, including cancellation filtering in a multiple-input multiple-output framework and coding-aided interference suppression approaches. Across these domains, we present the fundamental trade-offs between equalization performance, algorithmic convergence, power-area efficiency, and latency. Full article

Distributed Denial-of-Service (DDoS) attacks remain the most pervasive and operationally disruptive cyber threat and are routinely weaponized in interstate conflict (e.g., Russia–Ukraine and Stuxnet). Although attack-chain models are standard for Advanced Persistent Threat (APT) analysis, they have seldom been applied to DDoS, which is often framed as a single-step volumetric assault. However, ubiquitous intelligence and ambient connectivity increasingly enable DDoS campaigns to unfold as multi-stage operations rather than isolated floods. In parallel, large language models (LLMs) create new opportunities to strengthen traditional DDoS defenses through richer contextual understanding. Reviewing incidents from 2019 to 2024, we propose a three-phase DDoS attack chain—preparation, development, and execution—that captures contemporary tactics and their dependencies on novel hardware, network architectures, and application protocols. We classify these patterns, contrast them with conventional DDoS, survey current defenses (anycast and scrubbing, BGP Flowspec, programmable data planes, adaptive ML detection, API hardening), and outline research directions in cross-layer telemetry, adversarially robust learning, automated mitigation orchestration, and cooperative takedown. Full article

Recent developments in unmanned aerial vehicle (UAV) activity highlight the need for advanced electromagnetic spectrum monitoring systems that can detect drones operating near sensitive or restricted areas. Such systems can identify emissions from drones even under frequency-hopping conditions, providing an early warning system and enabling a timely response to protect critical infrastructure and ensure secure operations. In this context, the present work proposes the development of a high-performance multichannel broadband monitoring system with real-time analysis capabilities, designed on an SDR architecture based on USRP with three acquisition channels: two broadband (160 MHz and 80 MHz) and one narrowband (1 MHz) channel, for simultaneous, of extended spectrum segments, aligned with current requirements for analyzing emissions from drones in the 2.4 GHz and 5.8 GHz ISM bands. The processing system was configured to support cumulative bandwidths of over 200 MHz through a high-performance hardware platform (powerful CPU, fast storage, GPU acceleration) and fiber optic interconnection, ensuring stable and lossless transfer of large volumes of data. The proposed spectrum monitoring system proved to be extremely sensitive, flexible, and extensible, achieving a reception sensitivity of −130 dBm, thus exceeding the values commonly reported in the literature. Additionally, the parallel multichannel architecture facilitates real-time detection of signals from different frequency ranges and provides a foundation for advanced signal classification. Its reconfigurable design enables rapid adaptation to various signal types beyond unmanned aerial systems. Full article

AI-driven network security relies increasingly on Large Language Models (LLMs) to detect sophisticated threats; however, their deployment on resource-constrained edge devices is severely hindered by immense parameter scales. While unstructured pruning offers a theoretical reduction in model size, commodity Graphics Processing Unit (GPU) architectures fail to efficiently leverage element-wise sparsity due to the mismatch between fine-grained pruning patterns and the coarse-grained parallelism of Tensor Cores, leading to latency bottlenecks that compromise real-time analysis of high-volume security telemetry. To bridge this gap, we propose SPARTA (Sparse Parallel Architecture for Real-Time Threat Analysis), an algorithm–architecture co-design framework. Specifically, we integrate a hardware-based address remapping interface to enable flexible row-offset access. This mechanism facilitates a novel graph-based column vector merging strategy that aligns sparse data with Tensor Core parallelism, complemented by a pipelined execution scheme to mask decoding latencies. Evaluations on Llama2-7B and Llama2-13B benchmarks demonstrate that SPARTA achieves an average speedup of 2.35× compared to Flash-LLM, with peak speedups reaching 5.05×. These findings indicate that hardware-aware microarchitectural adaptations can effectively mitigate the penalties of unstructured sparsity, providing a viable pathway for efficient deployment in resource-constrained edge security. Full article

The exponential growth of digital data and the escalating sophistication of cyber threats have intensified the demand for secure yet computationally efficient encryption methods. Conventional algorithms (e.g., AES-based schemes) are cryptographically strong and widely deployed; however, some implementations can face performance bottlenecks in large-scale or real-time workloads. While many modern systems seed from hardware entropy sources and employ standardized cryptographic PRNGs/DRBGs, security can still be degraded in practice by weak entropy initialization, misconfiguration, or the use of non-cryptographic deterministic generators in certain environments. To address these gaps, this study introduces FileCipher. This novel file-encryption framework integrates a chaos-enhanced Cryptographically Secure Pseudorandom Number Generator (CPRNG) based on the State-Based Tent Map (SBTM). The proposed design achieves a balanced trade-off between security and efficiency through dynamic key generation, adaptive block reshaping, and structured confusion–diffusion processes. The SBTM-driven CPRNG introduces adaptive seeding and multi-key feedback, ensuring high entropy and sensitivity to initial conditions. A multi-threaded Java implementation demonstrates approximately 60% reduction in encryption time compared with AES-CBC, validating FileCipher’s scalability in parallel execution environments. Statistical evaluations using NIST SP 800-22, SP 800-90B, Dieharder, and TestU01 confirm superior randomness with over 99% pass rates, while Avalanche Effect analysis indicates bit-change ratios near 50%, proving strong diffusion characteristics. The results highlight FileCipher’s novelty in combining nonlinear chaotic dynamics with lightweight parallel architecture, offering a robust, platform-independent solution for secure data storage and transmission. Ultimately, this paper contributes a reproducible, entropy-stable, and high-performance cryptographic mechanism that redefines the efficiency–security balance in modern encryption systems. Full article

Quantum computing is a new discipline that uses the ideas of quantum physics to do calculations that are not possible with conventional computers. Quantum bits, called qubits, could exist in superposition states, making them suitable for parallel processing in contrast to traditional bits. When it comes to addressing complex challenges like proof simulation, optimization, and cryptography, quantum entanglement and quantum interference provide exponential improvements. This survey focuses on recent advances in entanglement routing, quantum key distribution (QKD), and qubit management for short- and long-distance quantum communication. It studies optimization approaches such as integer programming, reinforcement learning, and collaborative methods, evaluating their efficacy in terms of throughput, scalability, and fairness. Despite improvements, challenges remain in dynamic network adaptation, resource limits, and error correction. Addressing these difficulties necessitates the creation of hybrid quantum–classical algorithms for efficient resource allocation, hardware-aware designs to improve real-world deployment, and fault-tolerant architecture. Therefore, this survey suggests that future research focus on integrating quantum networks with existing classical infrastructure to improve security, dependability, and mainstream acceptance. This connection has significance for applications that require secure communication, financial transactions, and critical infrastructure protection. Full article

FPGA-based reconfigurable systems play a vital role in many critical domains by virtue of their unique advantages. They can effectively adapt to dynamically changing application scenarios, while featuring high parallelism and low power consumption. As a result, they have been widely adopted in key sectors such as aerospace, nuclear industry, and weapon equipment, where high performance and stability are of utmost importance. However, these systems face significant challenges. The continuous and drastic reduction in chip process size has led to increasingly complex and delicate internal circuit structures and physical characteristics. Meanwhile, the operating environments are often harsh and unpredictable. Additionally, the adoption of untrusted third-party foundries to reduce development costs further compounds these issues. Collectively, these factors make such systems highly susceptible to reliability threats, including environmental radiation, aging degradation, and malicious hardware attacks. These problems severely impact the stable operation and functionality of the systems. Therefore, ensuring the highly reliable operation of reconfigurable systems has become a critical issue that urgently needs to be addressed. There is a pressing need to summarize their technical characteristics, research status, and development trends comprehensively and in depth. In response, this paper conducts relevant research. By systematically reviewing 183 domestic and international research papers published between 2012 and 2024, it first provides a detailed analysis of the root causes of reliability issues in reconfigurable systems, thoroughly exploring their underlying mechanisms. Second, it focuses on the key technologies for achieving high reliability, encompassing four types of fault-tolerant design technologies, three types of aging mitigation technologies, and two types of hardware attack defense technologies. The paper comprehensively summarizes relevant research findings and the latest advancements in this field, offering a wealth of references for related research. Finally, it conducts a detailed comparative analysis and summary of the research hotspots in the field of high-reliability reconfigurable systems. It objectively evaluates the achievements and shortcomings of current research efforts and delves into the development trends of key technologies for high-reliability reconfigurable systems, providing clear directions for future research and practical applications. Full article

Neuromorphic computing, an interdisciplinary field combining neuroscience and computer science, aims to create efficient, bio-inspired systems. Different from von Neumann architectures, neuromorphic systems integrate memory and processing units to enable parallel, event-driven computation. By simulating the behavior of biological neurons and networks, these systems excel in tasks like pattern recognition, perception, and decision-making. Neuromorphic computing chips, which operate similarly to the human brain, offer significant potential for enhancing the performance and energy efficiency of bio-inspired algorithms. This review introduces a novel five-dimensional comparative framework—process technology, scale, power consumption, neuronal models, and architectural features—that systematically categorizes and contrasts neuromorphic implementations beyond existing surveys. We analyze notable neuromorphic chips, such as BrainScaleS, SpiNNaker, TrueNorth, and Loihi, comparing their scale, power consumption, and computational models. The paper also explores the applications of neuromorphic computing chips in artificial intelligence (AI), robotics, neuroscience, and adaptive control systems, while facing challenges related to hardware limitations, algorithms, and system scalability and integration. Full article