Search Results (181)

Smart-manufacturing Industrial Internet of Things (IIoT) deployments increasingly depend on low-latency device-to-device (D2D) communication among resource-constrained, physically exposed field devices. This setting makes mutual authentication and session-key establishment difficult: public-key-intensive or cloud-dependent schemes add overhead, availability dependence, and single points of failure, while weak PUF-based designs may expose challenge-response pairs (CRPs) to replay, disclosure, and modeling attacks. This paper proposes PASMAP, a lightweight PUF-ASCON mutual authentication protocol for gateway-assisted D2D communication in smart-manufacturing IIoT. PASMAP combines SRAM-PUF key reconstruction, fuzzy-extractor helper data, hash- and XOR-based obfuscation, and ASCON authenticated encryption with associated data (AEAD) to protect hardware-rooted identities, hide raw PUF responses, and establish fresh session keys for post-authentication data exchange under an explicitly trusted local-gateway model. The protocol is evaluated against physical, protocol-level, and insider threats, including cloning, tampering, replay, man-in-the-middle, CRP disclosure, PUF modeling, stolen-verifier, and known-key attacks. A real-or-random (ROR) analysis bounds the adversary’s session-key advantage using hash collisions, PUF-response prediction, online guessing, and ASCON AEAD security. A mixed-platform evaluation based on ESP32 primitive timings for the edge devices and desktop timings for the resource-rich gateway yields an estimated total computation cost of 4.762 ms. The initiator and responder require 2.006 ms/264.79 $\mathsf{\mu }$J and 2.679 ms/353.63 $\mathsf{\mu }$J of computational energy, respectively, while the five-message exchange carries 4704 bits. These results indicate low computational overhead under the stated benchmark and power-model assumptions. However, the protocol totals are operation-count-based estimates, the PUF and fuzzy-extractor operations are simulated, and the energy model excludes several platform- and communication-dependent costs. A complete embedded implementation is therefore required to validate end-to-end latency, memory use, energy consumption, communication-stack overhead, SRAM-PUF reliability, and fuzzy-extractor performance. Full article

Feature selection plays an important role in improving classification performance for high-dimensional datasets. To address the limitations of the original Zebra Optimization Algorithm (ZOA) in binary optimization problems, a Binary Zebra Optimization Algorithm for Feature Selection (BZOA-FS) is proposed. The proposed algorithm is integrated with a K-nearest neighbor (KNN) classifier to construct a prediction model for rockburst hazard levels. The proposed framework consists of three main components. First, the feature importance guidance mechanism is designed, and the feature importance score is constructed and run through the initialization, foraging stage, and defense stage of BZOA-FS. The binary zebra foraging operator and binary defense operator are designed to complete the transformation from continuous optimization to discrete optimization, and the adaptive strategy is introduced to make adaptive dynamic selection according to the evolution stage and population state. It should be emphasized that the basic binary operations used in BZOA-FS, such as XOR-based difference representation and probabilistic bit flipping, are common components in binary metaheuristic optimization. The main contribution of this study is its ZOA-specific reconstruction and integration with feature-importance guidance and diversity-driven adaptive defense. Second, four UCI data sets are selected for experiments to compare the performance of GA-FS, WOA-FS, ZOA-FS, BPSO-FS, RF-FS, and BZOA-FS algorithms on the two classifiers. The proposed BZOA-FS demonstrates competitive or superior performance compared with the selected benchmark algorithms on the investigated datasets. This verifies the feasibility of the improved strategy proposed in this study. Third, the algorithm is applied to the example of rockburst, and the prediction model of rockburst hazard level based on BZOA-FS is constructed. The results show that the performance of the BZOA-FS model in the evaluation indexes is better than other models, which demonstrates the potential of the proposed BZOA-FS model in the prediction of rockburst hazard level. Full article

Continuous stream-oriented data-plane processing in 5G/6G edge nodes increases the energy and latency cost of CPU-centered execution. This paper studies this boundary on an Intel Cyclone V SoC FPGA and proposes Hardware Accountability: a partitioning discipline in which Linux performs supervisory control while high-rate payload processing remains in programmable logic. The evaluation uses the Strumok stream cipher, adopted as the Ukrainian national standard DSTU 8845:2019, as a secure fronthaul/payload workload with XOR- and shift-dominated logic. On the evaluated USB 2.0/Cortex-A9/Linux path, the software-driven stream approaches saturation near 20 MSPS. In contrast, the RTL core reaches 9.6 Gbps at 150 MHz and occupies less than 6% of the available logic. Quartus Prime vectorless power analysis estimates 24.00 mW dynamic power for the RTL computational core, corresponding to approximately 2.5 pJ/bit. Control-plane measurements show P99 orchestration jitter below 1 ms under Spatial Isolation, conservative full context reloads near 1290 per second, and more than 7200 shadow-register context/state update operations per second. A design-space exploration then projects an 83.2 Gbps multi-core data path when external DDR traffic is avoided through internal stream aggregation and elastic buffering. Full article

This study proposes a hybrid multi-domain color image encryption algorithm that integrates a 2D Fractional-Order Chaotic Map (2D-FOCM), a 5D Gauss-Logistic Hyperchaotic System (5D-GLHS), two-level Discrete Wavelet Transform (DWT), and iris-biometric key distribution within a unified framework. The proposed architecture addresses three fundamental challenges simultaneously: the key distribution vulnerability of symmetric encryption, the limited dynamic complexity of integer-order chaotic systems, and the inadequacy of single-domain encryption approaches. The key distribution problem inherent in symmetric encryption is resolved through biometric uniqueness: rather than transmitting the encryption key directly, only an iris image is exchanged over a secure channel, and each party independently derives the chaotic control parameters from the iris ring region. Statistical features extracted from the iris ring region determine the control parameters of both the 2D-FOCM and the 5D-GLHS, establishing a user-specific, biometrically grounded dynamic key structure with an effective key space of 2¹⁴⁹. The 2D-FOCM, constructed via the piecewise constant arguments method with a Caputo fractional-order derivative, exhibits a broader chaotic parameter range, higher Lyapunov exponents (LE₁ ≈ 16.90, LE₂ ≈ 16.96), and higher approximate entropy than its integer-order counterparts, thereby expanding the key space and suppressing periodic tendencies. The encryption pipeline combines two-level DWT-based frequency-domain subband permutation using 2D-FOCM sequences with five sequential spatial-domain operations directed by the 5D-GLHS: chaotic sequence sorting-based permutation, forward chaining diffusion, inter-block scrambling, intra-block permutation, and XOR diffusion. Comprehensive security evaluations demonstrate that the proposed method achieves the highest average information entropy (7.9975) among 14 compared methods, near-ideal differential attack resistance (NPCR: 99.6109–99.6292%; UACI: 33.3291–33.4308%), and near-zero pixel correlation coefficients across all channels and spatial directions. Chi-square test results confirm superior histogram uniformity in the G and B channels over all 12 compared methods. These results collectively validate the proposed algorithm as a robust and competitive solution for color image security. Full article

This paper presents TALOS, a unified reusable 6G CryptoProcessor architecture for high-assurance symmetric security services under a 256-bit private-key baseline. The design addresses a core hardware challenge in future mobile systems: supporting heterogeneous strong symmetric primitives without duplicating complete cipher cores. TALOS combines a Hierarchical Common Data Path (HCDP) with a three-tier cryptographic encapsulation model spanning AES-256, Snow 5G/SNOW-V-class, and ZUC-256. Tier-1 captures native nonlinear substitutions, Tier-2 compiles bounded arithmetic nonlinearities into exact micro-S-boxes, and Tier-3 consolidates shared permutation, XOR, affine, diffusion, and state-transport fabrics. This decomposition preserves cipher correctness while exposing realistic sharing opportunities across substitution, arithmetic, and linear transport layers. The architecture also supports confidentiality processing and integration with integrity- and authentication-oriented service logic through a common control/resource framework. Compared with monolithic universal-box or loosely aggregated multi-core approaches, TALOS provides a disciplined, RTL-oriented taxonomy for crypto-agile symmetric-core hardware. The proposed framework advances 6G cryptographic hardware design by combining operator-exact reuse, architectural scalability, and implementation-oriented efficiency within a single CryptoProcessor paradigm. Full article

One of the bottlenecks in realizing all-optical computing is the lack of on-chip all-optical logic devices that combine compactness, low loss, and high robustness. Valley photonic crystals (VPCs) have become an important solution for realizing such devices, relying on the excellent transmission characteristics of topological valley states. However, existing structures still face issues such as limited design flexibility. In this paper, a high-performance topological all-optical logic device based on VPCs consisting of circular ring dielectric columns is designed and demonstrated. By introducing the inner radius as an independent design parameter, we construct a new type of VPC and systematically investigate its influence on the photonic band gap. Based on this, we design a beam splitter with high operational bandwidth and low insertion loss (<0.5 dB) and then realize fundamental OR and XOR logic gates, achieving extinction ratios of 18.9 dB for the OR gate and up to 44 dB for the XOR gate at an operating frequency of 193.5 THz. The platform also supports the NOT gate and, through cascading, can implement more logic functions such as the AND gate. Full article

The growing need for secure image transmission across public networks requires robust encryption algorithms. Traditional chaos-based image ciphers typically have a small key space, weak avalanche behavior, or are susceptible to differential cryptanalysis. To overcome such inadequacies, this paper suggests a new adaptive image cryptosystem that combines a fractional-order memristive chaotic engine and a non-linear hybrid encryption kernel. The system uses piano-inspired feedback; the keystream generator dynamically adapts to the previously encrypted pixel, enabling powerful Cipher Block Chaining (CBC)-style chaining and content-dependent diffusion. A four-dimensional memristive system is solved by the use of fractional-order calculus, which gives an ultra-large key space (>10⁸⁰) and very high sensitivity to initial conditions—confirmed by a positive largest Lyapunov exponent (1.7199). The encryption kernel maps the traditional Exclusive OR (XOR) with the reversible two-step operation: the modular addition of the plaintext with the first keystream byte and the XOR with the second keystream one, both of which increase non-linearity and confusion. Large-scale experiments with six standard 256 × 256 colour images indicate almost ideal entropy (7.9994), Number of Pixel Change Rate (NPCR) which is 99.62, Unified Average Changing Intensity (UACI) which is 33.43, correlation coefficients are near to zero, very low Gray-Level Co-occurrence Matrix (GLCM) homogeneity (≈0.017) and high contrast (≈4843) and low energy (≈0.006 The ciphertext passes seven National Institute of Standards and Technology (NIST) SP-800-22 statistical tests, is extremely sensitive to keys (a perturbation of 1 × 10⁻¹⁴ alters >99.6% of ciphertext) and resists chosen-plaintext and known-plaintext attacks. Decryption has linear time complexity O(N), and average encryption and decryption times are 3.40 s and 2.75 s for 256 × 256 images. The proposed cryptosystem provides an attractive security–performance trade-off that can be used in high-security systems like medical image protection, privacy-preserving multimedia transmission, and secure cloud storage. Full article

High-density (HD) quasi-cyclic low-density parity-check (QC-LDPC) codes are widely adopted in high-speed, high-reliability optical communication systems. However, the high density of the quasi-cyclic parity-check matrix prevents the direct derivation of a corresponding quasi-cyclic generator matrix, leading to computationally prohibitive encoding complexity. To address this limitation, based on the established polynomial-ring representation of QC-LDPC codes, this paper develops a structure-preserving polynomial-domain transformation for the high-density 50G-PON QC-LDPC parity-check matrix. The proposed method transforms the dense quasi-cyclic parity-check matrix into a compact systematic encoding form over $R={\mathbb{F}}_2\left[x\right]/(x^{256}-1)$. As a result, parity generation is reduced to the inversion of a small $3\times 3$ polynomial submatrix and a sequence of cyclic-shift-and-XOR operations. Based on this construction, an optimized HD-QC-LDPC encoding algorithm and its corresponding FPGA architecture are developed. The resulting hardware encoder achieves a throughput of 58.9 Gbps at a 200 MHz clock frequency on a Xilinx Kintex-7 FPGA, satisfying the throughput and latency requirements of 50G-PON systems. Full article

In highly dynamic vehicular ad hoc networks (VANETs), vehicles frequently move across the coverage areas of multiple roadside units (RSUs), making secure and efficient continuous vehicle-to-infrastructure access essential. However, repeated full authentication and key agreement for each new RSU access impose considerable computational and communication overhead. This paper proposes a state-assisted privacy-preserving mutual authentication and key agreement scheme for lightweight multi-RSU access in VANETs. The proposed scheme consists of initial and subsequent authentication phases. In the initial phase, elliptic curve cryptography (ECC) is used to achieve anonymous mutual authentication and session key establishment between vehicles and RSUs. In the subsequent authentication phase, a vehicle leverages follow-up authentication state securely forwarded by the previous RSU to complete fast authentication with a neighboring RSU using only hash and XOR operations. In addition, physically unclonable functions (PUFs) are deployed on both vehicles and RSUs to protect critical secrets. Security analysis shows that the proposed scheme achieves mutual authentication, anonymity preservation, and resistance to common attacks. Performance evaluation shows that it reduces the computational cost of subsequent authentication by more than 90% while maintaining low communication overhead. Full article

Multiplication is a fundamental operation in digital signal processing, embedded computing, and nanoscale arithmetic data paths, where area, delay, and energy efficiency are critical design constraints. However, nanoscale multiplier design is challenged by high interconnect complexity, frequent wire crossings, clock-zone synchronization issues, and the rapid growth of area and latency with operand size. Quantum-dot cellular automata (QCA) technology offers a promising post-CMOS platform for compact arithmetic circuit realization through field-coupled computation and transistor-free switching. This paper presents a single-layer QCA-based Dadda Tree Multiplier (DTM) using layout-aware integration of compact half-adder, full adder, XOR, and carry-skip adder modules. The proposed design emphasizes partial-product compression, routing compactness, clock-aware organization, and area-efficient final accumulation. Functional verification is performed using QCADesigner 2.0.3, while energy-related behavior is evaluated using QCADesigner-E under the conventional QCA simulation framework. The proposed DTM consists of 4282 cells and occupies 6.14 μm². Compared with a recent compact QCA multiplier baseline, the proposed architecture reduces cell count by 59.12% and occupies area by 39.80%, while maintaining competitive clocking latency. These results indicate that layout-aware integration of arithmetic modules can substantially improve the area efficiency of QCA-based multipliers, making the proposed design a compact arithmetic core for future nanoscale embedded and signal-processing systems. Full article

Digital images are easily transmitted in Internet, but there is also a great risk of information leakage. To meet the requirements of secure image transmission and real-time communication, an image encryption algorithm based on a novel chaotic map and a three-dimensional histogram is proposed. Firstly, a novel two-dimensional chaotic map is designed. Compared with traditional chaotic systems, it exhibits superior chaotic performance and a wider parameter range; secondly, the proposed algorithm is designed to extend the original image to three dimensions, followed by 3D simultaneous scrambling–diffusion; thirdly, the 2D exclusive OR (XOR) operation is performed for further diffusion; finally, the 3D matrix is merged to obtain the encrypted image. The encrypted images have uniform histograms and pass the Chi-square test. Information entropy is greater than 7.9992, and the average values of Number of Pixels Change Rate (NPCR) and Uniform Average Change Intensity (UACI), being 99.6137 and 33.4783, respectively, show that this algorithm can effectively resist differential attacks. On average, a 512 × 512 image can be encrypted in 0.7 s using the proposed algorithm. Thus, the proposed algorithm is applicable to image transmission over network platforms due to its high security, excellent encryption performance, and high efficiency. Full article

This paper addresses the problem of constructing adaptive stream encryption transformations based on dynamically generated Boolean mappings. A formal framework for modeling and modifying asymmetric two-operand Conditional Elementary Transformations (CETs) is proposed, where new operations are obtained through permutation-driven modification of operands and transformation results. The main contribution of the study is the development of a method for generating groups of CET-based transformations and corresponding generator models that enable the construction of pseudorandom sequences of dynamically varying substitution rules. The proposed approach ensures preservation of bijectivity and establishes formal relationships between direct and inverse operations under transformation modifications. Experimental evaluation demonstrates that the generated CET-based transformations produce output sequences with entropy close to the theoretical maximum (H ≈ 1) while providing enhanced diffusion properties. In particular, the CET_base configuration achieves an avalanche effect of approximately 0.79 compared to ≈0.5 for the classical XOR baseline. At the same time, permutation-based variants introduce additional structural diversity, enabling flexible trade-offs between diffusion strength and variability of transformation behavior. The obtained results confirm that the proposed framework enables systematic construction of large families of Boolean mappings, including up to 16 and 64 S-box transformations for 2Ci- and 3Ci-quanta operations, respectively, exceeding the capabilities of fixed XOR-based schemes. The proposed approach is intended as a flexible design paradigm for adaptive and lightweight cryptographic systems. However, the current study is limited to structural and statistical analysis, and a formal evaluation of resistance to established cryptanalytic attacks remains a subject of future research. Full article

Polarity-tunable photocurrents provide an intrinsic decision variable that enables in-sensor computing within a single device, moving beyond simple intensity detection toward next-generation intelligent vision, yet traditional photodetectors are limited by static doping profiles and fixed junction polarities. To overcome this bottleneck, we propose a Te_0.61Se_0.39 nanowire device with polarity-tunable photoresponse for broadband optoelectronic logic operation via photocarrier diffusion under localized light illumination. By simultaneously harnessing temporal (pulse width), spatial (light positions), amplitude (light intensity), and bias, our polarity-tunable devices deterministically realize the four fundamental Boolean logic gates (AND, NAND, XNOR, XOR), with a responsivity of 1.39 A/W and a specific detectivity of 1.75 × 10¹⁰ Jones across the visible to mid-wave infrared spectrum. We further showcased its scalability by constructing a two-layer composite Boolean circuit through the integration of optoelectronic AND and NAND gates. Practical applications in optical encoding/decoding transmission and differential perception highlight its broad functional adaptability. This work establishes a paradigm for broadband polarity devices in low-dimensional nanowires, providing a versatile platform for optoelectronic logic and differential imaging applications. Full article

The Internet of Drones (IoD) has emerged as a critical extension of the Internet of Things, enabling unmanned aerial vehicles to support diverse applications, including precision agriculture, logistics, disaster monitoring, and security surveillance. Despite its rapid growth, securing IoD communications remains a significant challenge due to the open wireless environment, high drone mobility, and strict computational and energy constraints. Existing authentication mechanisms either rely on computationally expensive cryptographic operations or remain validated only at the protocol or simulation level, leaving a critical gap in practical, hardware-validated solutions suitable for resource-constrained drone platforms. This gap motivates the need for a lightweight, privacy-preserving authentication scheme that is both theoretically sound and experimentally deployable on real hardware. To address this, we propose a Physically Unclonable Functions (PUF)-assisted lightweight authentication scheme for IoD environments that binds cryptographic keys to each drone’s intrinsic hardware characteristics via PUFs. The scheme employs dynamically generated pseudo-identities to conceal permanent drone identities and prevent tracking, while authentication and key agreement are achieved using efficient symmetric cryptographic primitives, including SHA-256 for key derivation and updates, AES-256 for secure communication, and lightweight XOR operations to minimize overhead. Forward secrecy is ensured through rolling key updates, and periodic renewal of PUF challenges enhances resistance to replay and modeling attacks. To validate practicality, both software-based and hardware-based implementations were developed and evaluated. The software evaluation demonstrates a low communication overhead of 708.5 bytes and an average computation time of 18.87 ms. The hardware implementation on a Nexys A7-100T FPGA operates at 100 MHz with only 12.49% LUT utilization and low dynamic power consumption of approximately 182.5 mW. These results confirm that the proposed framework achieves an effective balance between security, privacy, and efficiency. The significance of this work lies in providing a fully hardware-validated, PUF-based authentication framework specifically tailored to the real-world constraints of IoD environments, offering a practical foundation for securing next-generation drone networks. Full article

This paper presents an action potential detector (APD) based on a high-order non-linear energy operator (HONEO). The APD consists of a HONEO, a positive threshold generator, a negative threshold generator, and an XOR. The APD is capable of detecting the half-width of an action potential since it can determine both the positive peak and the negative peak of the action potential by means of the HONEO and two threshold generators. In addition, the signal-to-noise ratio (SNR) of the APD can also be improved due to the two adaptive threshold generators. The circuit is designed in a standard 0.18 $\mathsf{\mu }$m CMOS process with a 1.8 V supply voltage. Pre-layout simulations are performed under typical conditions (TT process corner, 1.8 V supply, 27 °C). The results show that the output amplitudes of the HONEO remain almost constant ($\pm 100$ mV) when the amplitude of the source signal varies from −10 mV to 30 mV at 1 kHz. Across temperature variations from $-20$°C to 80 °C, the output amplitude remains within $\pm 12\%$ of the nominal value, demonstrating acceptable stability for the target implantable application. Compared to the conventional NEO, the APD achieves 14–$20\mathrm{dB}$ SNR improvement, a detection accuracy of $97\%$. The power consumption of the APD is approximately $62\mathsf{\mu }\mathrm{W}$. Full article