An Action Potential Detector Based on a High-Order Nonlinear Energy Operator

Abstract

This paper presents an action potential detector (APD) based on a high-order non-linear energy operator (HONEO). The APD consists of a HONEO, a positive threshold generator, a negative threshold generator, and an XOR. The APD is capable of detecting the half-width of an action potential since it can determine both the positive peak and the negative peak of the action potential by means of the HONEO and two threshold generators. In addition, the signal-to-noise ratio (SNR) of the APD can also be improved due to the two adaptive threshold generators. The circuit is designed in a standard 0.18 $\mathsf{\mu }$m CMOS process with a 1.8 V supply voltage. Pre-layout simulations are performed under typical conditions (TT process corner, 1.8 V supply, 27 °C). The results show that the output amplitudes of the HONEO remain almost constant ($\pm 100$ mV) when the amplitude of the source signal varies from −10 mV to 30 mV at 1 kHz. Across temperature variations from $-20$°C to 80 °C, the output amplitude remains within $\pm 12\%$ of the nominal value, demonstrating acceptable stability for the target implantable application. Compared to the conventional NEO, the APD achieves 14–$20\mathrm{dB}$ SNR improvement, a detection accuracy of $97\%$. The power consumption of the APD is approximately $62\mathsf{\mu }\mathrm{W}$.

1. Introduction

Advances in semiconductor technology have enabled modern neural recording systems-on-chips (SoCs) to integrate thousands of channels on a single die [1,2,3]. This scaling in channel capacity allows for the simultaneous monitoring of activity across large populations of neurons. Neuronal activity, often termed “action potentials (AP)” or “spikes,” refers to the rapid electrical impulses generated when excitable cells are triggered to propagate signals between neurons. AP detection is a fundamental and critical step in decoding neural activities [4,5,6]. It not only provides essential support for investigating motor neuron firing patterns and elucidating the pathological mechanisms of neurological disorders such as drug-resistant epilepsy [7,8], but also finds wide application in neurophysiological research, clinical diagnosis of neuromuscular diseases, and the development of closed-loop neural stimulators. High-performance APD must clearly distinguish APs from background noise. Moreover, it is necessary to maintain spike waveforms, which are crucial for neurological disorder management systems. However, during the acquisition of extracellular neural signals, volume conduction effects often corrupt the recorded signals, and the overlapping of multi-unit activities also distorts them. These factors significantly reduce SNR and constrain detection accuracy, particularly for low-amplitude signals [2]. Traditional detection methods, such as threshold-based detection and the Teager energy operator (TEO) [3], therefore struggle to achieve an optimal balance between detection rate and false alarm rate (FAR) in noisy environments, and fail to meet the demands for high-precision neural signal analysis.

The non-linear energy operator (NEO) has gained prominence in the field of AP detection, owing to its distinctive ability to amplify transient signal features while effectively suppressing background noise [8,9,10]. It is typically defined as

$$NEO\left(t\right)={\left({\displaystyle \frac{dx\left(t\right)}{dt}}\right)}^2-{\displaystyle \frac{d^{2}x\left(t\right)}{d{t}^2}}·x\left(t\right)$$

(1)

where $x\left(t\right)$ is the AP signal source. To address the limited sensitivity of the conventional NEO, Li introduced a frequency-enhanced nonlinear energy operator (FNEO). The FNEO was implemented by two low-power analog spike detectors featuring an inverter-based design operating in the weak inversion region of MOSFETs [8]. In pursuit of ultra-low-power operation, Yao et al. [9] developed a compact current-mode neural spike detector fabricated in 65 nm CMOS technology. Operating at a supply voltage of only 0.7 V, this detector consumes a mere 40 nW of power, demonstrating the feasibility of integrating spike detection circuitry into energy-constrained implantable devices without compromising detection performance. Hu proposed a high-precision spike detection method by integrating an NEO with the first- and second-derivative (FSDE) feature extraction algorithm [10], which achieved a remarkably low power consumption of only $2.08\mathsf{\mu }\mathrm{W}$ per channel. Beyond detection algorithm development, several studies have focused on system-level integration and hardware efficiency. Kamboh and Mason [11] investigated on-chip feature extraction methodologies for spike sorting in high-density implantable neural recording systems. Their work highlighted the importance of integrating detection and feature extraction circuitry to reduce data transmission bandwidth and overall system power consumption. Furthermore, Gibson et al. [12] conducted a comprehensive comparative study of spike-sorting algorithms, evaluating their suitability for future hardware implementation. Their analysis provided critical guidance for selecting and optimizing detection and sorting algorithms under area and power constraints typical of multichannel neural interfaces. In addition, adaptive thresholding techniques have been explored to improve detection robustness in varying noise conditions. Tambaro and Vasanelli [13] proposed a firing rate independent threshold estimation method for neuronal spike detection, which adapts to the statistical properties of the background noise without requiring prior knowledge of the neural firing rate. This approach enhances detection reliability in long-term recordings where noise characteristics may drift over time. Beyond these adaptive approaches, Saggese et al. [14] investigated the smoothed nonlinear energy operator (SNEO) for multi-transistor array biosensors. Their results show that SNEO detection accuracy degrades significantly with increasing firing rate, dropping from 60% at 10 Hz to 25% at 200 Hz under 0 dB SNR. To address this, they proposed pre-normalization and post-normalization variants, with the latter achieving 52% accuracy at 0 dB SNR while adding only 6% hardware overhead. Rizk and Wolf [15] systematically compared four noise estimators for threshold selection: mean deviation (MD), root-mean-square (RMS), 84th percentile (P84), and 68th percentile of absolute values (PA68). They found that the RMS operator has the narrowest optimal multiplier range (3.5–4.5) and performs poorly in multi-unit recordings, whereas the MD operator offers the widest optimal range (4.5–6.0) and better robustness. Their work provides a quantitative framework for noise-based thresholding, though it still relies on accurate noise estimation that can be perturbed by spike activity.

Collectively, these studies offer valuable insights for advancing the performance of APDs. However, the aforementioned detection methods still face two primary challenges. First, although conventional NEOs would improve SNR, their excessive noise sensitivity could degrade performance during non-stationary signal processing and distort key AP features [16,17]. Conversely, most algorithmic improvements remain confined to the signal processing level, lacking joint consideration with hardware design. This gap hinders their applicability in scenarios demanding real-time operation and low power consumption, such as implantable neuroprosthetic devices [18,19].

In this work, we propose a novel AP detector (APD) based on a high-order non-linear energy operator (HONEO) to detect the half-width of an AP. To achieve high-precision detection, firstly, a HONEO is developed from the conventional NEO to enhance the SNR of AP signals while preserving their characteristic waveform parameters. Secondly, a preprocessing stage based on the HONEO is designed and optimized to reduce the operational complexity, while maintaining power consumption within the typical budget for implantable devices. Finally, the detection performance of the APD under varying SNR conditions is validated using publicly available neural signal datasets, such as the Quian Quiroga and Kamboh simulation datasets, as well as clinically recorded electromyography (EMG) data [20].

The rest of the paper is organized as follows. Section 2 introduces the HONEO algorithm and the architecture of the APD based on the HONEO. Section 3 illustrates the detailed circuit implementation of the key modules of the APD based on the HONEO. Simulation results and performance analysis are presented in Section 4. Finally, Section 5 concludes the paper.

2. Architecture of the APD Based on the HONEO

2.1. The HONEO

A standard deviation-based threshold generator is employed, which is expressed as

$$\sigma =\sqrt{{{\displaystyle \frac{{\displaystyle \sum _{i=1}^n}\left(x_i-\overline{x}\right)}{n-1}}}^2}$$

(2)

where $\sigma$ denotes the standard deviation of the signal, x is the amplitude of the AP signal, n is the total number of sampling points, i is the index of a sampling point, and $\overline{x}$ is the mean amplitude over the n points. Based on this, the signal threshold is calculated as $Thr=a·\sigma$.

The HONEO is established based on the traditional NEO [9,20]. Considering a sinusoidal input $f\left(t\right)=Asin\left(\omega t\right)$, is fed to the NEO, which will yield a constant output $A^2{\omega }^2$. Given that an AP can be approximated as a biphasic sinusoid [10], this fundamental property provides a valuable theoretical reference for analyzing AP signals. The mathematical formulation of the HONEO is given by

$$y\left(t\right)={\left({\displaystyle \frac{dx\left(t\right)}{dt}}\right)}^k-x\left(t\right)·\left({\displaystyle \frac{d^{2}x\left(t\right)}{d{t}^2}}\right)$$

(3)

where $x\left(t\right)$ is the neural signal, k is an odd integer.

$$f\left(t\right)=sin\left(\pi \left(t-4\right)\right)/\pi /\left(t-4\right)$$

(4)

The block diagram of the proposed APD based on the HONEO is illustrated in Figure 1. The APD consists of a HONEO, a positive threshold generator, a negative threshold generator, two comparators, and an XOR. The positive (negative) threshold generator contains a positive (negative) peak detector and a variable gain amplifier (VGA).

Equation (3) was synthesized in MATLAB R2021a when the input was SINC function signals as defined in Equation (4). Figure 2a displays the temporal waveforms of the original simulated AP signal along with its first- and second-order derivatives. Figure 2b presents the corresponding processing results after applying Equation (3) to the derivatives, with the parameter k set to 3, 5, and 7, respectively. Simulations demonstrate that the odd-order operator effectively preserves key AP features, such as pulse duration. Further analysis revealed that larger k values lead to more pronounced positive and negative spike characteristics. In the practical circuit implementation of the analog multiplier, the signal amplitude undergoes an attenuation of approximately two orders of magnitude (40 dB) per multiplication stage, which is inherent to the finite gain of the CMOS Gilbert cell. To maintain sufficient dynamic range for subsequent signal processing, a fixed-gain amplifier must be inserted after each multiplier stage to restore the signal amplitude. Consequently, as the order k increases, the number of required multiplier stages and associated amplifiers grows linearly, leading to a significant increase in overall power consumption and circuit complexity. Furthermore, higher-order operations are more sensitive to high-frequency noise, potentially amplifying noise components and causing false alarms or missed detections under low signal-to-noise ratio conditions.

Table 1. Power consumption of HONEO with different k values.

k	Multiplier Stages	Amplifiers	Power ($\mathsf{\mu }$W)
3	2	2	42
5	3	3	85
7	4	4	127

presents the estimated power consumption of the preprocessing circuit for different k values, illustrating the impact of this design constraint on power consumption. Considering the implementation probability and power consumption, the cubic nonlinear energy operator ($k=3$ in Equation (3)) was ultimately selected.

The proposed HONEO is formulated in Equation (5), and its implementation is shown in the block diagram of Figure 3.

$$HONEO\left(t\right)={\left({\displaystyle \frac{dx\left(t\right)}{dt}}\right)}^3-x\left(t\right)·\left({\displaystyle \frac{d^{2}x\left(t\right)}{d{t}^2}}\right)$$

(5)

2.2. The Dual-Threshold Detection Mechanism

As also shown in Figure 1, a positive peak detector and a negative peak detector track the positive peak and negative peak of the AP signals in real time. In the absence of an AP, their outputs gradually decay over time due to leakage [21,22]. A variable-gain amplifier then sets the positive threshold to $70\%$ of the positive peak detector’s output and the negative threshold to 60% of the negative peak detector’s output. Moreover, the inherent leakage of the peak detector allows the thresholds to adjust automatically over time, and ensure that small APs are detectable even followed the large ones. An AP is identified once the HONEO output exceeds both thresholds, triggering the simultaneous calculation of its half-width, which is defined as the time difference between the positive and negative peaks.

3. Circuit Implementation of the APD Based on the HONEO

3.1. The Proposed HONEO-Based Circuit

The HONEO is depicted in Figure 3. It contains two differentiators, three multipliers, three operational transconductance amplifiers (OTAs), and a subtractor. The OTA structure employed in this work is shown in Figure 4a. The choice of the mirrored operational amplifier topology is primarily motivated by the need to achieve sufficient DC gain under a low supply voltage of 1.8 V. As demonstrated in [9], using long-channel devices instead of cascode structures enables high gain without sacrificing voltage headroom. This topology features a reduced transistor count, leading to lower power consumption and smaller area. All transistors are biased in the weak inversion region, achieving a DC gain of approximately 60 dB with sub-microampere bias currents. The input-referred noise of the structure is presented in Figure 4b, which is approximately 36.7 nV/$\sqrt{\mathrm{Hz}}$ at 1 kHz, well below the amplitude of the amplified neural signal, thereby meeting the detection requirements. Compared to a differential pair with active load or a folded cascode structure, the adopted OTA achieves a more favorable trade-off among power, area, and noise performance [23]. The differentiator, implemented with a $g_m\text{-}C$ topology (Figure 5), generates the first derivative to highlight high-frequency components that above the threshold for slope assessment. It consists of three transconductance stages $\left(g_{m1}–g_{m3}\right)$ and a grounded capacitor $C_1$. The transfer function of the differentiator is given by [24]

$${\displaystyle \frac{V_{out}}{V_{in}}}={\displaystyle \frac{g_{m2}}{g_{m3}}}·{\displaystyle \frac{s{C}_1}{s{C}_1+g_{m1}}}$$

(6)

The differentiator is cascaded by the multiplier. The multiplier incorporates a preconditioning module consisting of an active attenuator and a source follower to enhance the input dynamic range, optimize bias conditions, and thereby improve the overall linearity [25,26]. As shown in Figure 6, the multiplier consists of a CMOS Gilbert cell, an active attenuator, and a bias circuitry. In the CMOS Gilbert cell, transistors $M7$, $M11$, and $M12$ are configured as NMOS current sources [27]. Under the idealized assumption that all core transistors share a unity width-to-length ratio ($W/L=1$) and their transconductance parameters satisfy $K_{1–6}=K$ (where $K=0.5{\mu }_n{C}_{\mathrm{ox}}$), the theoretical transfer characteristic of the multiplier can be expressed as

$$I_{out}=I_{11}-I_{12}=\left(I_1-I_2\right)-\left(I_4-I_3\right)\approx \sqrt{2}K{U}_X{U}_Y$$

(7)

The effective input range of the multiplier is determined by

$$-\sqrt{{\displaystyle \frac{I_{SS}}{K}}}\le U_X\le \sqrt{{\displaystyle \frac{I_{SS}}{K}}}$$

(8)

where $I_i$ (here i is an integer) represents the drain-source current of transistors $M_i$. The input differential voltage is defined as $U_X=V_{a1}-V_{a2}$ and $U_Y=V_{b1}-V_{b2}$.

From the approximation condition given by Equation (8), it can be seen that when $U_x^2$ is sufficiently small, the multiplier can perform linear multiplication operations. To satisfy this approximation condition, a pair of active attenuators can be connected to the two inputs X and Y of the multiplier [28]. The active attenuator employs a symmetric topology to process signals from the two input signals independently [29]. Taking the left half-circuit in Figure 6 as an example, PMOS transistors $M13$ and $M17$ form one active attenuator, where $M13$ operates in the linear region, and $M17$ operates in the saturation region. NMOS transistor $M25$ is also biased in the saturation region, functioning as a source follower. $M21$ acts as a current source. $M21$ and $M25$ form a level-shifter. $V_{x1}$ and $V_{x2}$ represent the input signal terminals, while $V_{a1}$ and $V_{a2}$ are the output signal terminals. Let the gate voltage of $M25$ be denoted as $V_1$. Assuming the threshold voltages of $M13$ and $M17$ are equal, i.e., $V_{TH13}$ = $V_{TH17}$ = $V_{TH}$, then the relationship between $V_1$ and the input voltage is given by

$$V_1=\left(1-\sqrt{{\displaystyle \frac{W_{13}{L}_{17}}{W_{13}{L}_{17}+W_{17}{L}_{13}}}}\right)·\left(V_{x1}-V_{TH}\right)$$

(9)

where W and L denote the channel width and length of the MOS transistor, respectively. Let the attenuation factor be denoted as

$$F=\left(1-\sqrt{{\displaystyle \frac{W_{13}{L}_{17}}{W_{13}{L}_{17}+W_{17}{L}_{13}}}}\right)$$

(10)

It can be seen that by adjusting the channel width and length of $M13$ and $M17$, the desired attenuation coefficient can be achieved.

3.2. The Positive and Negative Threshold Generators

The output signal of the HONEO is then fed to the positive and negative threshold generators (Figure 7). Taking the positive threshold generator as an example, the $M9$ functions as a nonlinear rectifying element. Under low current bias, its source voltage can track the peak of the input signal. However, the gate source voltage of the MOSFET is susceptible to process variations and temperature drift. To compensate for this voltage attenuation, $M10$ is introduced, ensuring that the output voltage accurately follows the input peak. Furthermore, to suppress the channel length modulation effect of $M9$ and $M10$, an operational amplifier composed of $M2$, $M6$, $M7$, and $M14$ is incorporated into the design. To address charge injection effects in the traditional diode-based peak detector [22], a MOSFET current mirror is employed in the positive peak detector. This modification effectively mitigates charge injection into the holding capacitor and enables more accurate and stable peak detection.

The VGA is similar to the one proposed in [9]. The gain is controlled by the bias voltage $V_c$. The positive threshold is defined as $V_{\mathrm{pth}}=V_{\mathrm{peak}}\times G$, and the negative threshold is defined as $V_{\mathrm{vth}}=V_{\mathrm{npeak}}\times G$, where $V_{\mathrm{peak}}$ and $V_{\mathrm{npeak}}$ are the outputs of the positive peak detector and negative peak detector, respectively, and G is the gain of the VGA, with a range of 0.3–0.7. The gain range is selected based on empirical optimization: thresholds below 30% cause excessive false positives due to noise triggering, while thresholds above 70% miss valid spikes. The specific 70%/60% split for positive/negative thresholds compensates for typical AP asymmetry.

The comparator adopts a Class AB two-stage open-loop structure. Applying the Class AB output stage to the open-loop comparator can effectively enhance the output driving capability, reduce the crossover distortion, and obtain excellent efficiency and low distortion performance [23]. To evaluate the impact of device mismatch, Monte Carlo simulations were performed on the comparator circuit, which is the most critical block for threshold decision. As shown in Figure 8, the results exhibit an input-referred offset voltage of $900\mathsf{\mu }\mathrm{V}$ (mean) with a standard deviation of $27\mathsf{\mu }\mathrm{V}$, and this performance meets the circuit design requirements.

The XOR gate circuit designed in this paper is shown in Figure 9. Its function is to logically combine the results of the two preceding threshold comparisons: a high level is output only when both the positive and negative peaks are detected simultaneously (i.e., both threshold generators are triggered), indicating that a complete action potential event has been successfully identified. This XOR gate consists of three core functional modules: an OR logic module implemented with PMOS transistors ($M5$–$M8$), an AND logic module implemented with NMOS transistors ($M9$–$M12$), and a signal conditioning module comprising two CMOS inverters used to generate the necessary inverted signals. In the specific implementation, the OR gate realizes the logical OR function through a parallel configuration of four PMOS transistors ($M5$–$M8$) to receive the preceding signals, while the AND gate realizes the logical AND function through a series configuration of four NMOS transistors ($M9$–$M12$) to perform the final event determination.

Benefiting from its fully complementary CMOS structure, this XOR gate offers a significant advantage in static power consumption: when the input signals are in a steady state, either the PMOS or the NMOS network is cut off, completely eliminating the DC path from the power supply to ground. Due to this complementary switching characteristic, the static power dissipation of the XOR gate is nearly negligible. This ultra-low static power feature makes it particularly suitable for battery-powered neural recording devices, effectively extending the system’s operational lifetime. Furthermore, the design exhibits excellent noise margin and full output voltage swing, further enhancing its operational reliability in low-voltage microelectrode array acquisition environments.

4. Simulation Results

The proposed APD is implemented in a standard 180 nm CMOS process. The input signals are constructed by selecting three distinct spike shapes from a database of 594 spikes recorded from intracortical neural activity [19,29]. The reason for selecting this database is that it not only has broad coverage but also supports queries of AP morphological parameters. Some parameters are used for evaluating the performance of the APD. The SNR is defined as [30]

$$SNR=20·{log}_{10}\left({\displaystyle \frac{{\sigma }_x}{{\sigma }_n}}\right)$$

(11)

where ${\sigma }_x$ and ${\sigma }_n$ are the standard deviations of the signal and noise, respectively. To quantitatively assess the performance of the proposed APD, we used three detection metrics: False positive rate (FPR), False negative rate (FNR), and Accuracy (Acc), calculated as follows [31]:

$$FPR={\displaystyle \frac{FP}{TN+FP}}$$

(12)

$$FNR={\displaystyle \frac{FN}{TP+FN}}$$

(13)

$$Accuracy={\displaystyle \frac{TP}{TP+FN+FP}}$$

(14)

where the true positive ($TP$) refers to the number of APs accurately identified. The false positive ($FP$) indicates the actual number of non-APs erroneously identified as APs. The false negative ($FN$) represents the number of APs that were not detected. The true negative ($TN$) denotes the number of signal segments correctly judged as non-APs.

Figure 10 shows the simulation results of the HONEO. Figure 11 presents the output of the positive and negative threshold generators, where Figure 11a demonstrates the overall detection results, and Figure 11b exhibits the detection result of a single AP signal. When setting thresholds, optimal performance is achieved by adjusting $V_C$. The results demonstrate that the proposed HONEO enhances the SNR from $3.4\mathrm{dB}$ to $17.5\mathrm{dB}$ while preserving the characteristics of APs.

The APD can accurately detect APs and measure the half-width parameter by recording the time intervals between the positive and negative peaks. As shown in Figure 11b, the half-width of a single AP signal is $0.3\mathrm{ms}$. The total propagation delay of the HONEO is dominated by the analog signal path through differentiators, multipliers, and comparators. Based on transient simulations, the delay from input spike to output detection pulse is estimated to be approximately 100 $\mathsf{\mu }$s. This is negligible compared to the typical refractory period of neurons (2–5 ms). Therefore, the detection latency does not affect real-time performance. Detailed delay characterization across PVT corners will be addressed in future work.

To quantify the overall performance and compare it with other published APDs [24,32]. We conducted simulation experiments on the MATLAB platform based on the Waveclus dataset [29]. Figure 12 presents the output results of the HONEO detector for AP signals at an SNR of $10\mathrm{dB}$. We also performed a comparative analysis of the detection accuracy between the HONEO and NEO operators under different noise levels.

Table 2. Performance comparison of different schemes at ${\sigma }_n=0.1$.

Method	TP	FN	FP	TN	Acc	FPR	FNR
HONEO	49	1	45	1905	0.977	0.023	0.02
NEO	49	1	51	1899	0.974	0.026	0.02

and

Table 3. Performance comparison of different schemes at ${\sigma }_n=0.3$.

Method	TP	FN	FP	TN	Acc	FPR	FNR
HONEO	45	5	195	1755	0.90	0.10	0.13
NEO	40	10	390	1560	0.81	0.10	0.10

further present the specific performance parameters of the two methods at noise standard deviations ${\sigma }_n=0.1$ and ${\sigma }_n=0.3$, respectively. As shown in Figure 13, the performance advantage of HONEO over NEO becomes increasingly significant as the noise level increases. At ${\sigma }_n=0.10$ (SNR ≈ 14 dB), the improvement is modest (0.3%). However, at ${\sigma }_n=0.30$ (SNR ≈ 4.4 dB), it further increases to 7.0%. This trend demonstrates that the proposed HONEO detector exhibits superior noise robustness, especially in challenging low-SNR recording environments. In addition, beyond detection accuracy, the HONEO detector uniquely provides half-width extraction capability, enabling downstream spike sorting and neuron classification. This functional advantage further distinguishes the proposed method from conventional NEO-based detectors.

Figure 14 shows the performance comparison of various APDs under different noise standard deviations, where the noise standard deviation ${\sigma }_n$ is normalized to the AP amplitude. For the FPR, it can be seen from Figure 14a that the performance of HONEO is similar to that of NEO at low noise levels. For the FNR, as shown in Figure 14b, when the noise level exceeds 0.2, the number of missed detections of APs based on the NEO increases more significantly. This is because the NEO-based detection method relies on single-positive threshold determination. This results in more APs being missed in events where the SNR of the negative wave of the AP is higher than that of the positive wave. Furthermore,

Table 4. Performance comparison with reported APDs.

Parameter	This Work	[14]	[30]	[21]	[24]	[28]
Process (nm)	180	N/A	180	180	180	65
VDD (V)	1.8	N/A	1.8	1.8	0.8	1.1
Method	HONEO	SNEO	NEO	ADF	ED	Dual NEO
Style	Analog	Digital	Analog	Digital	Analog	Analog
Accuracy	0.97	0.99	0.92	0.96	0.95	0.97
Power ($\mathsf{\mu }$W)	62	N/A	N/A	35.84	28.43	17.92
Feature Extraction	Yes	No	No	No	No	No
Verification Stage	Pre-layout	Software	Measured	Measured	Measured	Software

N/A: Not available.

compares the proposed HONEO detector with state-of-the-art implementations under the condition of ${\sigma }_n=0.1$. The results demonstrate that the proposed APD achieves superior detection accuracy. Functionally, it uniquely provides half-width extraction, a feature not present in the other designs listed. This additional capability supports downstream spike sorting and neuron classification, extending the utility of the detector beyond simple event counting. The proposed APD consumes $62\mathsf{\mu }\mathrm{W}$ of power. Although this is higher than that of several ultra-low-power designs [21,24,28], it remains within the typical low-power budget for implantable neural recording systems. Overall, the proposed HONEO detector offers high detection accuracy and a distinctive half-width extraction capability, while maintaining acceptable power consumption for implantable applications.

5. Conclusions

This paper presents an APD based on a high-order nonlinear energy operator (HONEO). The APD consists of a HONEO, a positive threshold generator, a negative threshold generator, and an XOR. The APD can detect the half-width of an action potential (AP) since it can determine both the positive peak and the negative peak of the AP by means of the HONEO and two threshold generators. The HONEO can perform a nonlinear time-domain transformation of the AP signal and enhance the SNR of the raw data while preserving the morphological features of the APs. Implemented in a 180 nm CMOS process, the proposed APD has been validated to accurately detect 1 kHz AP signals and measure their half-widths. The APD based on the HONEO is suitable for low-power, implantable neural signal acquisition systems as well as brain–computer interface devices. Future work will focus on post-layout simulations, including parasitic extraction and Monte Carlo analysis, to further evaluate the robustness of the design under process, voltage, and temperature variations. Chip fabrication and experimental measurements are also planned to validate the performance of the proposed APD in real-world conditions. Additionally, multi-channel integration and the incorporation of on-chip spike sorting capabilities will be explored to support higher-density neural recording applications.