Search Results (30)

This study presents a low-cost, small-scale single-chamber microbial fuel cell (MFC) toxicity biosensor fabricated on a printed circuit board (PCB) and a 3D-printed chamber with a volume of 120 μL. The anode consists of a screen-printed carbon electrode on the PCB, while the air cathode is a carbon paper electrode. To address poor adhesion of microorganisms to the smooth anode surface, femtosecond laser processing was used to fabricate a micropore array with 40 μm pores on the electrode. This method can create micropores on the anode surface without damaging the screen-printed electrodes, the PCB substrate, or the pads. These micropores increase the anode’s surface area and hydrophilicity, allowing more microbial coatings to firmly adhere to its surface. In this study, the MFC utilised Rhizobium rosettiformans W3, extracted from activated sludge at a wastewater treatment plant, as the anode microorganism. Its aerobic nature simplifies the design of MFCs, enabling a single-chamber structure and miniaturisation. Using formaldehyde solution as a toxicity sample to test the biosensor’s performance, a 0.1% concentration significantly reduced the sensor’s output power. Full article

Background: Arterial stenosis produces nonlinear changes in vascular impedance that are challenging to investigate in real time using either benchtop flow phantoms or high-fidelity computational fluid dynamics (CFD) models. Objective: This study aimed to develop and evaluate a low-cost printed circuit board (PCB) analog capable of reproducing the hemodynamic effects of progressive arterial stenosis through an R–L–C mapping of vascular mechanics. Methods: A lumped-parameter (0D) electrical network was constructed in which voltage represented pressure, current represented flow, resistance modeled viscous losses, capacitance corresponded to vessel compliance, and inductance represented fluid inertance. A variable resistor simulated focal stenosis and was adjusted incrementally to represent progressive narrowing. Input U_in, output U_out, peak-to-peak V_pp, and mean V_avg voltages were recorded at a driving frequency of 50 Hz. Physiological correspondence was established using the canonical relationships. $R={\displaystyle \frac{8\mu l}{\pi r^4}}$, $L={\displaystyle \frac{pl}{\pi r^2}}$, $C={\displaystyle \frac{3\pi r^3}{2Eh}}$, where μ is blood viscosity, ρ is density, E is Young’s modulus, and h is wall thickness. A calibration constant was applied to convert measured voltage differences into pressure differences. Results: As simulated stenosis increased, the circuit exhibited a monotonic rise in U_out and V_pp, with a precise inflection beyond mid-range narrowing—consistent with the nonlinear growth in pressure loss predicted by fluid dynamic theory. Replicate measurements yielded stable, repeatable traces with no outliers under nominal test conditions. Qualitative trends matched those of surrogate 0D and CFD analyses, showing minimal changes for mild narrowing (≤25%) and a sharp increase in pressure loss for moderate to severe stenoses (≥50%). The PCB analog uses a simplified, lumped-parameter representation driven by a fixed-frequency sinusoidal excitation and therefore does not reproduce fully characterized physiological systolic–diastolic waveforms or heart–arterial coupling. In addition, the present configuration is intended for relatively straight peripheral arterial segments and is not designed to capture the complex geometry and branching of specialized vascular beds (e.g., intracranial circulation) or strongly curved elastic vessels (e.g., the thoracic aorta). Conclusions: The PCB analog successfully reproduces the characteristic hemodynamic signatures of arterial stenosis in real time and at low cost. The model provides a valuable tool for educational and research applications, offering rapid and intuitive visualization of vascular behavior. Current accuracy reflects assumptions of Newtonian, laminar, and lumped flow; future work will refine calibration, quantify uncertainty, and benchmark results against physiological measurements and full CFD simulations. Full article

Automated optical inspection (AOI) technologies are widely used in PCB and semiconductor manufacturing to improve accuracy and reduce human error during quality inspection. While existing AOI systems can perform defect detection, they often rely on pre-defined camera positions and lack flexibility for interactive inspection, especially when the operator needs to visually verify solder pad conditions or examine specific layout regions. This study focuses on the front-end optical positioning and inspection stage of the AOI workflow, providing an automated mechanism to link digitally generated layout reports from EDA layout tools with real PCB inspection tasks. The proposed system operates on component-placement reports exported by EDA layout environments and uses them to automatically guide the camera to the corresponding PCB coordinates. Since PCB design reports may vary in format and structure across EDA tools, this study proposes a vision-based extraction approach that employs Hough transform-based region detection and a CNN-based digit recognizer to recover component coordinates from visually rendered design data. A dual-axis sliding platform is driven through a hierarchical control architecture, where coarse positioning is performed via TB6600 stepper control and Bluetooth-based communication, while fine alignment is achieved through a non-contact, gesture-based interface designed for clean-room operation. A high-resolution autofocus camera subsequently displays the magnified solder pads on a large screen for operator verification. Experimental results show that the proposed platform provides accurate, repeatable, and intuitive optical positioning, improving inspection efficiency while maintaining operator ergonomics and system modularity. Rather than replacing defect-classification AOI systems, this work complements them by serving as a positioning-assisted inspection module for interactive and semi-automated PCB quality evaluation. Full article

This work examines resistance drift in FPGA I/O paths subjected to combined electrical and thermal stress, using a Xilinx Spartan-6 device as a representative platform. A multiplexed measurement approach was employed, in which multiple I/O pins were externally shorted and sequentially activated, enabling precise tracking of voltage, current, and effective series resistance over time, under controlled bias conditions. Two accelerated stress modes were investigated: high-temperature dwell in the range of 80–120 °C and thermal cycling between 80 and 140 °C. Both stress modes exhibited similar sub-linear (power-law) time dependence on resistance change, indicating cumulative degradation behavior. However, Arrhenius analysis revealed a strong contrast in effective activation energy: approximately 0.62 eV for high-temperature dwell and approximately 1.3 eV for thermal cycling. This divergence indicates that distinct physical mechanisms dominate under each stress regime. The lower activation energy is consistent with electrically and thermally driven on-die degradation within the FPGA I/O macro, including bias-related aging of output drivers and pad-level structures. In contrast, the higher activation energy observed under thermal cycling is characteristic of diffusion- and creep-dominated thermo-mechanical damage in package-level interconnects, such as solder joints. These findings demonstrate that resistance-based monitoring of FPGA I/O paths can discriminate between device-dominated and package-dominated aging mechanisms, providing a practical foundation for reliability assessment and self-monitoring methodologies in complex electronic systems. Full article

Precise recognition and localization of electronic components on printed circuit boards (PCBs) are crucial for industrial automation tasks, including robotic disassembly, high-precision assembly, and quality inspection. However, strong visual interference from silkscreen characters, copper traces, solder pads, and densely packed small components often degrades the accuracy of deep learning-based detectors, particularly under complex industrial imaging conditions. This paper presents a two-stage, coarse-to-fine PCB component localization framework based on an optimized YOLOv11 architecture and a sub-pixel geometric refinement module. The proposed method enhances the backbone with a Convolutional Block Attention Module (CBAM) to suppress background noise and strengthen discriminative features. It also integrates a tiny-object detection branch and a weighted Bi-directional Feature Pyramid Network (BiFPN) for more effective multi-scale feature fusion, and it employs a customized hybrid loss with vertex-offset supervision to enable pose-aware bounding box regression. In the second stage, the coarse predictions guide contour-based sub-pixel fitting using template geometry to achieve industrial-grade precision. Experiments show significant improvements over baseline YOLOv11, particularly for small and densely arranged components, indicating that the proposed approach meets the stringent requirements of industrial robotic disassembly. Full article

We present a compact and cost-effective real-time PCR system designed for point-of-care testing (POCT), utilizing a PCB-based disposable chip and an open-platform CMOS camera. The system integrates precise thermal cycling with software-synchronized fluorescence detection and provides real-time analysis through a dedicated user interface. To minimize cost and complexity, a polycarbonate reaction chamber was integrated with a PCB-based heater and thermistor. A slanted LED illumination setup and an open-platform USB camera were employed for fluorescence imaging. Signal alignment was enhanced using device-specific region-of-interest (ROI) tracking based on copper pad corner detection. Thermal cycling performance achieved a heating rate of 8.0 °C/s and a cooling rate of −9.3 °C/s, with steady-state accuracy within ±0.1 °C. Fluorescence images exhibited high dynamic range without saturation, and the 3σ-based ROI correction method improved signal reliability. System performance was validated using Chlamydia trachomatis DNA standard (10³ copies), yielding consistent amplification curves with a Ct standard deviation below 0.3 cycles. These results demonstrate that the proposed system enables rapid, accurate, and reproducible nucleic acid detection, making it a strong candidate for field-deployable molecular diagnostics. Full article

A new radio frequency (RF) probe using pogo pin tips for integrated chip (IC) measurement up to 50 GHz is proposed. It offers high durability due to the pogo pins and meets three key design criteria for general IC measurement: (1) a 45° tilted shape with a 70 μm tip protrusion for easy microscope inspection, (2) linear pogo pin alignment for commercial chip pad contact, and (3) a 250 μm pitch compatible with standard IC pad pitches. This design is distinct from traditional pogo pin probe cards which place pogo pins in vertical form, in a diagonal arrangement, and at wide intervals. The probe exhibits a low insertion loss of 1.6 dB at 45 GHz. A printed circuit board (PCB)-based calibration standard for the calibration of the designed probe is constructed, which is adjusted to inductance and capacitance values using a simulation to form the Vector Network Analyzer (VNA) calibration set. The measurements of a commercial amplifier IC using this probe show a nearly identical performance to commercial RF probes, confirming its accuracy and reliability. Full article

This paper examined the reliability of complex PCB assemblies under random vibration and temperature cycling, which are two primary causes of assembly failure. A combination of finite element simulation and environmental testing was employed to investigate the effects of different reinforcement methods and solder joint morphology on assembly reliability. The linear accumulation of damage was utilized to predict assembly failure, and the predicted failure damage was compared with the damage extracted post-testing to validate the simulation analysis. The results indicate that SAC305 solder exhibits greater strength than Sn63Pb37 solder in withstanding temperature cycling fatigue, yet is weaker than Sn63Pb37 solder in withstanding random vibration fatigue. When the solder is Sn63Pb37, the temperature cycling life of the assembly with the bottom filled and the corners fixed is reduced by 92.3% and 99.3%, respectively, compared to the unreinforced method, while the random vibration life is enhanced by 84 times and 3.9 times, respectively. An increase in pad diameter is advantageous for improving the random vibration life of the assembly, but results in a decrease in the temperature cycling life. When the lower pad diameter ranges from 0.35 mm to 0.55 mm, the assembly temperature cycling life decreases by 28.83%, 82.03%, 90.66%, and 91.22% with the increase of the lower pad diameter, and the random vibration life improves by 4.8 times, 9.5 times, 20.4 times, and 33.6 times, respectively. The predicted locations of vulnerable solder joints for the assembly are consistent with the experimental results, and the failure prediction accuracy of the assembly is 88.89%. Full article

Electrochemical migration (ECM) on the surface of printed circuit boards (PCBs) continues to pose a significant reliability risk in electronics. Nevertheless, the existing literature lacks studies that address the solder mask and solder pad design aspects in the context of ECM. Therefore, the objective of this study was to assess the impact of solder mask type with varying roughness and solder pad design on the susceptibility to ECM using a water drop test and thermal humidity bias test. Hot air solder leveling-coated PCBs were tested. Furthermore, the ECM tests were conducted on PCBs with applied no-clean solder paste to evaluate the influence of flux residues on the resulting ECM behavior. The results indicated that the higher roughness of the solder mask significantly contributes to ECM inhibition through the creation of a mechanical barrier for the dendrites. Furthermore, lower ECM susceptibility was also observed for copper-defined pads, where a similar effect is presumed. However, the influence of the no-clean flux residues can prevail over the effects of the solder mask. Therefore, the use of a rough solder mask and a copper-defined pad design is recommended if the PCB is to be washed from flux residues after the soldering process. Full article

Bi-doped Sn–Ag–Cu (SAC) microelectronic solder is gaining attention for its utility as a material for solder joints that connect substrates to printed circuit boards (PCB) in future advanced packages, as Bi-doped SAC is reported to have a lower melting temperature, higher strength, higher wettability on conducting pads, and lower intermetallic compound (IMC) formation at the solder-pad interface. As solder joints are subjected to aging during their service life, an investigation of aging-induced changes in the microstructure and mechanical properties of the solder alloy is needed before its wider acceptance in advanced packages. This study focuses on the effects of 1 to 3 wt.% Bi doping in an Sn–3.0Ag–0.5Cu (SAC305) solder alloy on aging-induced changes in hardness and creep resistance for samples prepared by high cooling rates (>5 °C/s). The specimens were aged at ambient and elevated temperatures for up to 90 days and subjected to quasistatic nanoindentation to determine hardness and nanoscale dynamic nanoindentation to determine creep behavior. The microstructural evolution was investigated with a scanning electron microscope in tandem with energy-dispersive spectroscopy to correlate with aging-induced property changes. The hardness and creep strength of the samples were found to increase as the Bi content increased. Moreover, the hardness and creep strength of the 0–1 wt.% Bi-doped SAC305 was significantly reduced with aging, while that of the 2–3 wt.% Bi-doped SAC305 increased with aging. The changes in these properties with aging were correlated to the interplay of multiple hardening and softening mechanisms. In particular, for 2–3 wt.% Bi, the enhanced performance was attributed to the potential formation of additional Ag₃Sn IMCs with aging due to non-equilibrium solidification and the more uniform distribution of Bi precipitates. The observations that 2–3 wt.% Bi enhances the hardness and creep strength of the SAC305 alloy with isothermal aging to mitigate reliability risks is relevant for solder samples prepared using high cooling rates. Full article

This research review article provides a detailed examination of SMA (SubMiniature version A) connectors, which are integral components in high-frequency electronic systems. Through extensive S-parameter and time-domain reflectometry (TDR) measurements conducted on various SMA connector constructions, this study aims to evaluate the performance and impact of SMA connectors on signal integrity. Results reveal insights into the comparative performance of different SMA connector types mounted on PCB land pads, highlighting their strengths and limitations. Additionally, this paper explores the application of reference plane cut-outs for discontinuity impedance compensation, aiming to enhance the frequency response of SMA connectors. By linking measured performance parameters with relative market prices, this study offers valuable insights into the economic viability of different SMA connector types. The best and worst performing SMA connector measurements reveal an S₁₁ < −10 dB bandwidth of more than 8 GHz and 1.5 GHz and a transition impedance of 46.5 Ω and 21 Ω, respectively. Overall, this research contributes to advancing the understanding and selection of SMA connectors for RF applications in telecommunications, aerospace, medical devices, and beyond. Full article

Semiconductor chips are packaged in a process that involves creating a path to allow for signals to be exchanged with the outside world and ultimately achieving a form to protect against various external environmental conditions such as heat and moisture. The wire bonding type of packaging is a method in which thin metal wires are bonded to pads to create an electrical connection between the chip and the lead frame. An Epoxy Molding Compound (EMC) can be applied to protect semiconductor chips from external environmental conditions such as heat, shock, and moisture. However, EMC contains halogen elements and sulfides and has hydrophilic properties, which can lead to a corrosive environment. The present study aims to evaluate the influence of chloride, which is a contaminant formed during the PCB manufacturing process. To this end, the galvanic corrosion of bonding wire materials Cu wire, Cu wire alloyed with 1% Pd, and Cu wire coated with Pd was investigated. The first ball bond was bonded to the Al pad and the second stitch bond was bonded to the Au pad of the manufacturing process, after which the galvanic corrosion behavior in the semiconductor packaging module specimen was analyzed. A model of galvanic corrosion behavior was also proposed. Full article

A large amount of multi-layer ceramic capacitor (MLCC) is mounted inside a printed circuit board (PCB) constituting electronic components. The use of MLCC in electric vehicles and the latest mobile phones is rapidly increasing with the latest technology. Environments in which electronic components are used are becoming more diverse and conformal coatings are being applied to protect mounted components from these environments. In particular, MLCCs in electronic components mainly have voltage applied. They might be used in environments where humidity exists for various reasons. In a humid environment, electrochemical migration (ECM) will occur, with the cathode and anode on the surface of the MLCC encountering each other. This can result in product damage due to a short circuit. In this study, the effects of voltage, NaCl concentration, and distance between electrodes on a non-mount MLCC, surface mount MLCC, and solder pad pattern were evaluated using a water drop test (WDT). Based on the analysis of the effects of the presence of conformal coating, applied voltage, concentration of NaCl, and the distance between electrodes, a mechanism model for ECM behavior in MLCCs was proposed. Full article

Modern wireless communication systems are of utmost importance to various sectors such as healthcare, education, the household, and the advancement of emerging technologies like the internet of things, autonomous vehicles, and the enhancement of 5G. Further development and improvement of these systems drives the need for small dimension, high integration and density, and cost-effective electronic devices. Achieving optimal performance in wireless electronic devices involves overcoming engineering challenges related to microstrip line signal integrity. This research addresses the impact of surface mount technology (SMT) component pads on signal integrity, proposing a novel high-frequency microstrip line structure for mitigating impedance discontinuities. The study introduces stepped microstrip lines and explores characteristic impedance compensation techniques. A six-layer printed circuit board (PCB) structure is presented, and the effects of compensation on signal integrity are analyzed using time-domain reflectometry and scattering parameter measurements. The results demonstrate the effectiveness of compensation methods in aligning characteristic impedance with desired values, thereby ensuring improved impedance matching and transmission coefficients. The average over-the-length impedance for the proposed structure with compensation applied was measured to be 52.7 Ω, which is only 1.3 Ω (2.5%) more than that of the reference microstrip. Applying reference plane cut-outs leads to a maximum compensated absolute value of more than 30 Ω to reach the target impedance with a 10% tolerance. This research contributes valuable insights for advancing wireless communication systems and maintaining robustness in high-frequency microstrip transmission lines. Full article

The quad flat no-lead package (QFN) is widely used in integrated circuits due to its advantages in performance and cost. With the increasing power of electronic products, effective heat dissipation from QFN packages has become crucial to prevent product damage. The focus of this study is to investigate the thermal performance of QFN packages soldered onto printed circuit boards (PCB) by finite element analysis (FEA). Conventional QFN, dual-row QFN, and high-lead QFN packages were modeled and compared by ANSYSY software. The effect of thermal via design (the distance, number, distribution, diameter, and thickness of thermal vias) on the QFN package was investigated. The study revealed that the high-lead QFN package consistently demonstrated superior heat dissipation performance than the other two under different conditions. Placing thermal vias closer to the heat source enhances heat dissipation efficiency. Thermal vias positioned beneath the thermal pad were particularly effective. Increasing thermal via quantity and diameter improved heat dissipation, with square distribution layouts showing advantages. However, excessive copper plating thickness can increase thermal resistance and hinder heat dissipation. Full article