Search Results (66)

General-Purpose Graphics Processing Units (GPGPUs) rely on warp scheduling and control flow management to organize parallel thread execution, making efficient control flow mechanisms essential for modern GPGPU design. Currently, the mainstream RISC-V GPGPU Vortex adopts the Single Instruction Multiple Threads (SIMT) stack control mechanism. This approach introduces high complexity and performance overhead, becoming a major limitation for further improving control efficiency. To address this issue, this paper proposes a thread-mask-based branch control mechanism for the RISC-V architecture. The mechanism introduces explicit mask primitives at the Instruction Set Architecture (ISA) level and directly manages the active status of threads within a warp through logical operations, enabling branch execution without jumps and thus reducing the overhead of the original control flow mechanism. Unlike traditional thread mask mechanisms in GPUs, our design centers on RISC-V and realizes co-optimization at both the ISA and microarchitecture levels. The mechanism was modeled and validated on Vortex SimX. Experimental results show that, compared with the Vortex SIMT stack mechanism, the proposed approach maintains correct control semantics while reducing branch execution cycles by an average of 31% and up to 40%, providing a new approach for RISC-V GPGPU control flow optimization. Full article

This paper proposes and implements a method to efficiently parallelize constraint solving in rigid body simulation using GPUs. Rigid body simulation is widely used in robot development, computer games, movies, and other fields, and there is a growing need for faster computation. As current computers are reaching their limits in terms of scale-up, such as clock frequency improvements, performance improvements are being sought through scale-out, which increases parallelism. However, rigid body simulation is difficult to parallelize efficiently due to its characteristics. This is because, unlike fluid or molecular physics simulations, where each particle or lattice can be independently extracted and processed, rigid bodies can interact with a large number of distant objects depending on the instance. This characteristic causes significant load imbalance, making it difficult to evenly distribute computational resources using simple methods such as spatial partitioning. Therefore, this paper proposes and implements a computational method that enables high-speed computation of large-scale scenes by hierarchically clustering rigid bodies based on their number and associating the hierarchy with the hardware structure of GPUs. In addition, to effectively utilize parallel computing resources, we considered a more relaxed parallelization condition for the conventional Gauss–Seidel block parallelization method and demonstrated that convergence is guaranteed. We investigated how speed and convergence performance change depending on how much computational cost is allocated to each hierarchy and discussed the desirable parameter settings. By conducting experiments comparing our method with several widely used software packages, we demonstrated that our approach enables calculations at speeds previously unattainable with existing techniques, while leveraging GPU computational resources to handle multiple rigid bodies simultaneously without significantly compromising accuracy. Full article

Lagrangian Relaxation (LR) is an effective method for solving spatial optimization problems in geospatial analysis and GIS. Among others, it has been used to solve the classic p-median problem that served as a unified local model in GIS since the 1990s. Despite its efficiency, the LR algorithm has seen limited usage in practice and is not as widely used as off-the-shelf solvers such as OPL/CPLEX or GPLK. This is primarily because of the high cost of development, which includes (i) the cost of developing a full gradient descent algorithm for each optimization model with various tricks and modifications to improve the speed, (ii) the computational cost can be high for large problem instances, (iii) the need to test and choose from different relaxation schemes, and (iv) the need to derive and compute the gradients in a programming language. In this study, we aim to solve the first three issues by utilizing the computational power of GPGPU and existing facilities of modern deep learning (DL) frameworks such as PyTorch. Based on an analysis of the commonalities and differences between DL and general optimization, we adapt DL libraries for solving LR problems. As a result, we can choose from the many gradient descent strategies (known as “optimizers”) in DL libraries rather than reinventing them from scratch. Experiments show that implementing LR in DL libraries is not only feasible but also convenient. Gradient vectors are automatically tracked and computed. Furthermore, the computational power of GPGPU is automatically used to parallelize the optimization algorithm (a long-term difficulty in operations research). Experiments with the classic p-median problem show that we can solve much larger problem instances (of more than 15,000 nodes) optimally or nearly optimally using the GPU-based LR algorithm. Such capabilities allow for a more fine-grained analysis in GIS. Comparisons with the OPL solver and CPU version of the algorithm show that the GPU version achieves speedups of 104 and 12.5, respectively. The GPU utilization rate on an RTX 4090 GPU reaches 90%. We then conclude with a summary of the findings and remarks regarding future work. Full article

General-purpose graphics computing on processing units (GPGPUs) face significant performance limitations due to memory access latencies, particularly when traditional memory hierarchies and thread-switching mechanisms prove insufficient for complex access patterns in data-intensive applications such as machine learning (ML) and scientific computing. This paper presents a novel hardware design for a memory prefetching subsystem targeted at DDR (Double Data Rate) memory in GPGPU architectures. The proposed prefetching subsystem features a modular architecture comprising multiple parallel prefetching engines, each handling distinct memory address ranges with dedicated data buffers and adaptive stride detection algorithms that dynamically identify recurring memory access patterns. The design incorporates robust system integration features, including context flushing, watchdog timers, and flexible configuration interfaces, for runtime optimization. Comprehensive experimental validation using real-world workloads examined critical design parameters, including block sizes, prefetch outstanding limits, and throttling rates, across diverse memory access patterns. Results demonstrate significant performance improvements with average memory access latency reductions of up to 82% compared to no-prefetch baselines, and speedups in the range of 1.240–1.794. The proposed prefetching subsystem successfully enhances memory hierarchy efficiency and provides practical design guidelines for deployment in production GPGPU systems, establishing clear parameter optimization strategies for different workload characteristics. Full article

This paper proposes an optimized shared memory access technique to enhance parallel processing performance and reduce memory accesses for the ARIA block cipher in GPU environments. To overcome the limited size of GPU shared memory, we merged ARIA’s four separate S-box tables into a single unified 32-bit table, effectively reducing the total memory usage from 4 KB to 1 KB. This allowed the consolidated table to be replicated 32 times within the limited shared memory, efficiently resolving the memory-bank conflict issues frequently encountered during parallel execution. Additionally, we utilized CUDA’s built-in function __byte_perm() to efficiently reconstruct the desired outputs from the reduced unified table, without imposing additional computational overhead. In exhaustive key-search scenarios, we implemented an on-the-fly key-expansion method, significantly reducing the memory usage per thread and enhancing parallel processing efficiency. In the RTX 3060 environment, profiling was performed to accurately analyze shared memory efficiency and the performance degradation caused by bank conflicts, yielding detailed profiling results. The results of experiments conducted on the RTX 3060 Mobile and RTX 4080 GPUs demonstrated significant performance improvements over conventional methods. Notably, the RTX 4080 GPU achieved a maximum throughput of 1532.42 Gbps in ARIA-CTR mode, clearly validating the effectiveness and practical applicability of the proposed optimization techniques. On the RTX 3060, the performance of 128-bit ARIA-CTR was improved by 2.34× compared to previous state-of-the-art implementations. Furthermore, for exhaustive key searches on the 128-bit ARIA block cipher, a throughput of 1365.84 Gbps was achieved on the RTX 4080 GPU. Full article

This paper presents Boundary-Aware Concurrent Queue (BACQ), a high-performance queue designed for modern GPUs, which focuses on high concurrency in massively parallel environments. BACQ operates at the warp level, leveraging intra-warp locality to improve throughput. A key to BACQ’s design is its ability to replace conflicting accesses to shared data with independent accesses to private data. It uses a ticket-based system to ensure fair ordering of operations and supports infinite growth of the head and tail across its ring buffer. The leader thread of each warp coordinates enqueue and dequeue operations, broadcasting offsets for intra-warp synchronization. BACQ dynamically adjusts operation priorities based on the queue’s state, especially as it approaches boundary conditions such as overfilling the buffer. It also uses a virtual caching layer for intra-warp communication, reducing memory latency. Rigorous benchmarking results show that BACQ outperforms the BWD (Broker Queue Work Distributor), the fastest known GPU queue, by more than 2× while preserving FIFO semantics. The paper demonstrates BACQ’s superior performance through real-world empirical evaluations. Full article

The rapid advancement of deep neural networks has significantly increased demands for computational complexity and data volume. This trend is especially evident with the emergence of large language models, which have rendered traditional architectures such as CPUs and GPGPUs insufficient in meeting performance and energy efficiency requirements. Spatial accelerators present a promising solution by optimizing on-chip compute, storage, and communication resources. In exploring spatial accelerator design spaces, analytical model-based simulators and cycle-accurate simulators are commonly employed, each offering distinct advantages: high computational speed and superior simulation accuracy, respectively. However, the limited accuracy of analytical models and the slow simulation speed of cycle-accurate simulators impede the achievement of globally optimal solutions during design space exploration. Therefore, effectively leveraging the strengths of both simulator types while mitigating their inherent trade-offs is a critical challenge in designing customized spatial accelerators. In this work, we introduce a novel co-exploration methodology that integrates both coarse-grained and fine-grained approaches to navigate design and mapping spaces effectively. We utilize the rapid simulation capabilities of analytical models to perform coarse-grained global exploration, quickly eliminating designs and mapping configurations with inferior performance. Building on the results of this initial exploration, we employ cycle-accurate simulators to conduct fine-grained local exploration within the identified promising regions of the design and mapping spaces. This dual-phase approach aims to identify optimal hardware designs and dataflow mapping strategies that enhance performance and energy efficiency. The experimental results demonstrate that, compared to state-of-the-art methods, our approach reduces the number of exploration points by up to 99%, while achieving a 17.9% reduction in latency, a 2.5% decrease in energy consumption, and a 30.3% improvement in throughput. Full article

Simultaneous Localization and Mapping (SLAM) algorithms are crucial for enabling agents to estimate their position in unknown environments. In autonomous navigation systems, these algorithms need to operate in real-time on devices with limited resources, emphasizing the importance of reducing complexity and ensuring efficient performance. While SLAM solutions aim at ensuring accurate and timely localization and mapping, one of their main limitations is their computational complexity. In this scenario, particle filter-based approaches such as FastSLAM 2.0 can significantly benefit from parallel programming due to their modular construction. The parallelization process involves identifying the parameters affecting the computational complexity in order to distribute the computation among single multiprocessors as efficiently as possible. However, the computational complexity of methodologies such as FastSLAM 2.0 can depend on multiple parameters whose values may, in turn, depend on each specific use case scenario ( ingi.e., the context), leading to multiple possible parallelization designs. Furthermore, the features of the hardware architecture in use can significantly influence the performance in terms of latency. Therefore, the selection of the optimal parallelization modality still needs to be empirically determined. This may involve redesigning the parallel algorithm depending on the context and the hardware architecture. In this paper, we propose a CUDA-based adaptable design for FastSLAM 2.0 on GPU, in combination with an evaluation methodology that enables the assessment of the optimal parallelization modality based on the context and the hardware architecture without the need for the creation of separate designs. The proposed implementation includes the parallelization of all the functional blocks of the FastSLAM 2.0 pipeline. Additionally, we contribute a parallelized design of the data association step through the Joint Compatibility Branch and Bound (JCBB) method. Multiple resampling algorithms are also included to accommodate the needs of a wide variety of navigation scenarios. Full article

Traditional tools, such as 3D Slicer, Fiji, and MATLAB^®, often encounter limitations in rendering performance and data management as the dataset sizes increase. This work presents a GPU-enabled volume renderer with a MATLAB^® interface that addresses these issues. The proposed renderer uses flexible memory management and leverages the GPU texture-mapping features of NVIDIA devices. It transfers data between the CPU and the GPU only in the case of a data change between renderings, and uses texture memory to make use of specific hardware benefits of the GPU and improve the quality. A case study using the ViBE-Z zebrafish larval dataset demonstrated the renderer’s ability to produce visualizations while managing extensive data effectively within the MATLAB^® environment. The renderer is available as open-source software. Full article

Advancements in technology have driven the miniaturization of embedded systems, making them more cost-effective and energy-efficient for wireless applications. As a result, the number of connectable devices in Internet of Things (IoT) networks has increased significantly, creating the challenge of linking them effectively and economically. The space industry has long recognized this challenge and invested in satellite infrastructure for IoT networks, exploiting the potential of edge computing technologies. In this context, it is of critical importance to enhance the onboard computing capabilities of satellites and develop enabling technologies for their advancement. This is necessary to ensure that satellites are able to connect devices while reducing latency, bandwidth utilization, and development costs, and improving privacy and security measures. This paper presents the GPU@SAT DevKit: an ecosystem for testing a high-performance, general-purpose accelerator designed for FPGAs and suitable for edge computing tasks on satellites. This ecosystem provides a streamlined way to exploit GPGPU processing in space, enabling faster development times and more efficient resource use. Designed for FPGAs and tailored to edge computing tasks, the GPU@SAT accelerator mimics the parallel architecture of a GPU, allowing developers to leverage its capabilities while maintaining flexibility. Its compatibility with OpenCL simplifies the development process, enabling faster deployment of satellite-based applications. The DevKit was implemented and tested on a Zynq UltraScale+ MPSoC evaluation board from Xilinx, integrating the GPU@SAT IP core with the system’s embedded processor. A client/server approach is used to run applications, allowing users to easily configure and execute kernels through a simple XML document. This intuitive interface provides end-users with the ability to run and evaluate kernel performance and functionality without dealing with the underlying complexities of the accelerator itself. By making the GPU@SAT IP core more accessible, the DevKit significantly reduces development time and lowers the barrier to entry for satellite-based edge computing solutions. The DevKit was also compared with other onboard processing solutions, demonstrating similar performance. Full article

The training phase of a deep learning neural network (DLNN) is a computationally demanding process, particularly for models comprising multiple layers of intermediate neurons.This paper presents a novel approach to accelerating DLNN training using the particle swarm optimisation (PSO) algorithm, which exploits the GPGPU architecture and the Apache Spark analytics engine for large-scale data processing tasks. PSO is a bio-inspired stochastic optimisation method whose objective is to iteratively enhance the solution to a (usually complex) problem by approximating a given objective. The expensive fitness evaluation and updating of particle positions can be supported more effectively by parallel processing. Nevertheless, the parallelisation of an efficient PSO is not a simple process due to the complexity of the computations performed on the swarm of particles and the iterative execution of the algorithm until a solution close to the objective with minimal error is achieved. In this study, two forms of parallelisation have been developed for the PSO algorithm, both of which are designed for execution in a distributed execution environment. The synchronous parallel PSO implementation guarantees consistency but may result in idle time due to global synchronisation. In contrast, the asynchronous parallel PSO approach reduces the necessity for global synchronization, thereby enhancing execution time and making it more appropriate for large datasets and distributed environments such as Apache Spark. The two variants of PSO have been implemented with the objective of distributing the computational load supported by the algorithm across the different executor nodes of the Spark cluster to effectively achieve coarse-grained parallelism. The result is a significant performance improvement over current sequential variants of PSO. Full article

This paper presents the parallelization of two widely used implicit numerical solvers for the solution of partial differential equations on structured meshes, namely, the ADI (Alternating-Direction Implicit) solver for tridiagonal linear systems and the SIP (Strongly Implicit Procedure) solver for the penta-diagonal systems. Both solvers were parallelized using CUDA (Computer Unified Device Architecture) Fortran on GPGPUs (General-Purpose Graphics Processing Units). The parallel ADI solver (P-ADI) is based on the Parallel Cyclic Reduction (PCR) algorithm, while the parallel SIP solver (P-SIP) uses the wave front method (WF) following a diagonal line calculation strategy. To map the solution schemes onto the hierarchical block-threads framework of the CUDA on the GPU, the P-ADI solver adopted two mapping methods, one block thread with iterations (OBM-it) and multi-block threads (MBMs), while the P-SIP solver also used two mappings, one conventional mapping using effective WF lines (WF-e) with matrix coefficients and solution variables defined on original computational mesh, and a newly proposed mapping using all WF mesh (WF-all), on which matrix coefficients and solution variables are defined. Both the P-ADI and the P-SIP have been integrated into a two-dimensional (2D) hydrodynamic model, the CCHE2D (Center of Computational Hydroscience and Engineering) model, developed by the National Center for Computational Hydroscience and Engineering at the University of Mississippi. This study for the first time compared these two parallel solvers and their efficiency using examples and applications in complex geometries, which can provide valuable guidance for future uses of these two parallel implicit solvers in computational fluids dynamics (CFD). Both parallel solvers demonstrated higher efficiency than their serial counterparts on the CPU (Central Processing Unit): 3.73~4.98 speedup ratio for flow simulations, and 2.166~3.648 speedup ratio for sediment transport simulations. In general, the P-ADI solver is faster than but not as stable as the P-SIP solver; and for the P-SIP solver, the newly developed mapping method WF-all significantly improved the conventional mapping method WF-e. Full article

In cases of accidental or deliberate incidents involving a harmful agent in urban areas, a detailed modelling approach is required to include the building shapes and spatial locations. Simultaneously, when applied to crisis management, a simulation tool must meet strict time constraints. This work presents a Lagrangian particle model (LPM) for computing atmospheric dispersion. The model is implemented in the nuclear decision support system ESTE CBRN, a software tool developed to calculate the atmospheric dispersion of airborne hazardous materials and radiological impacts in the built-up area. The implemented LPM is based on Thomson’s solution for the nonstationary, three-dimensional Langevin equation model for turbulent diffusion. The simulation results are successfully analyzed by testing compatibility with Briggs sigma functions in the case of continuous release. The implemented LPM is compared with the Joint Urban 2003 Street Canyon Experiment for instantaneous puff releases. We compare the maximum concentrations and peak times measured during two intensive operational periods. The modeled peak times are mostly 10–20% smaller than the measured. Except for a few detector locations, the maximum concentrations are reproduced consistently. In the end, we demonstrate via calculation on single computers utilizing general-purpose computing on graphics processing units (GPGPU) that the implementation is well suited for an actual emergency response since the computational times (including dispersion and dose calculation) for an acceptable level of result accuracy are similar to the modeled event duration itself. Full article

The growing number of space objects leads to increases in the potential risks of damage to satellites and generates space debris after colliding. Conjunction assessment analysis is the one of keys to evaluating the collision risk of satellites and satellite operators require the analyzed results as fast as possible to decide and execute collision maneuver planning. However, the computation time to analyze the potential risk of all satellites is proportional to the number of space objects. The conjunction filters and parallel computing techniques can shorten the computation cost of conjunction analysis to provide the analyzed results. Therefore, this paper shows the investigation of the conjunction filter performances (accuracy and computation speed): Smart Sieve, CSieve and CAOS-D (combination of both Smart Sieve and CSieve) in both a single satellite (one vs. all) and all space objects (all vs. all) cases. Then, all the screening filters are developed to implement an algorithm that executes General-purpose computing on graphics processing units (GPGPU) by using NVIDIAs Compute Unified Device Architecture (CUDA). The analyzed results show the comparison results of the accuracy of conjunction screening analysis and computation times of each filter when implemented with the parallel computation techniques. Full article

We report on the development and validation of a 3D hybrid Lattice Boltzmann Model (LBM), with Large Eddy Simulation (LES), to simulate the interactions of incompressible turbulent flows with ocean structures. The LBM is based on a perturbation method, in which the velocity and pressure are expressed as the sum of an inviscid flow and a viscous perturbation. The far- to near-field flow is assumed to be inviscid and represented by potential flow theory, which can be efficiently modeled with a Boundary Element Method (BEM). The near-field perturbation flow around structures is modeled by the Navier–Stokes (NS) equations, based on a Lattice Boltzmann Method (LBM) with a Large Eddy Simulation (LES) of the turbulence. In the paper, we present the hybrid model formulation, in which a modified LBM collision operator is introduced to simulate the viscous perturbation flow, resulting in a novel perturbation LBM (pLBM) approach. The pLBM is then extended for the simulation of turbulence using the LES and a wall model to represent the viscous/turbulent sub-layer near solid boundaries. The hybrid model is first validated by simulating turbulent flows over a flat plate, for moderate to large Reynolds number values, Re $\in [3.7\times {10}^4;1.2\times {10}^6]$; the plate friction coefficient and near-field turbulence properties computed with the model are found to agree well with both experiments and direct NS simulations. We then simulate the flow past a NACA-0012 foil using a regular LBM-LES and the new hybrid pLBM-LES models with the wall model, for Re = $1.44\times {10}^6$. A good agreement is found for the computed lift and drag forces, and pressure distribution on the foil, with experiments and results of other numerical methods. Results obtained with the pLBM model are either nearly identical or slightly improved, relative to those of the standard LBM, but are obtained in a significantly smaller computational domain and hence at a much reduced computational cost, thus demonstrating the benefits of the new hybrid approach. Full article