Search Results (57)

This work presents a fully integrated, two-stage, deep class-AB power amplifier (PA) operating at a center frequency of 60 GHz. High efficiency and suppression of third-order intermodulation products are targeted, achieving improved linearity compared to reported state-of-the-art designs. A current combining architecture is also employed to enhance the output power capability. The PA is designed in a 22 nm FD-SOI CMOS technology and is optimized through a complete schematic-to-layout design flow. Post-layout simulations indicate that the PA achieves a peak power-added efficiency (PAE) of 28%, a saturated output power ($P_{sat}$) of 20.2 dBm, and a maximum large-signal gain ($G_{max}$) of 19.6 dB at 60 GHz, evaluated at an operating temperature of 60 °C. The design maintains high linearity across the targeted output power range, exhibiting effective suppression of third-order intermodulation distortion (IMD3), which enhances its suitability for spectrally efficient modulation schemes. Full article

This paper presents a 0–360° phase shifter in 28 nm FD-SOI CMOS technology, suitable for radar applications and mm-wave wireless communication systems, which adopt high-efficiency transmitter architectures. It exploits a novel switching vector modulator based on a double-balanced Gilbert cell, which guarantees high-resolution phase control while exhibiting inherently high robustness against process and temperature variations. The phase control is performed by merely changing the currents in the Gilbert cells using digitally controlled current generators. The proposed phase shifter operates at 39 GHz and provides RMS phase and gain errors of 2.7–4.7° and 0.3–0.5 dB, respectively, while drawing 13 mA from a 1 V supply voltage. Full article

This work presents a current-controlled CMOS ring oscillator (CCRO) optimized for ultra-low-voltage applications in next-generation energy-constrained systems. Leveraging bulk voltage tuning in 22 nm FDSOI differential inverter stages, the topology enables frequency adjustment while operating MOSFETs in the subthreshold region—critical for minimizing power in sub-1 V environments. Simulations at 0.4 V supply demonstrate robust performance: a three-stage oscillator achieves a 537–800 MHz tuning range with bias current (I_BIAS) modulation from 30–130 nA, while a four-stage configuration spans 388–587 MHz. At 70 nA I_BIAS, the three-stage design delivers a nominal frequency of 666.8 MHz with just 10.23 µW power dissipation, underscoring its suitability for ultra-low-power IoT and biomedical applications. The oscillator’s linear frequency sensitivity (2.63 MHz/nA) allows precise, dynamic control over performance–power tradeoffs. To address diverse application needs, the design integrates three tunability mechanisms: programmable capacitor arrays for coarse frequency adjustments, configurable stage counts (three- or four-stage topologies), and supply voltage scaling. This multi-modal approach extends the operational range to 1 MHz–1 GHz, ensuring compatibility with low-speed sensor interfaces and high-speed edge-computing tasks. The CCRO’s subthreshold operation at 0.4 V—coupled with nanoampere-level current consumption—makes it uniquely suited for battery-less systems, wearable health monitors, and implantable medical devices where energy efficiency and adaptive clocking are paramount. By eliminating traditional voltage-controlled oscillators’ complexity, this topology offers a compact, scalable solution for emerging ultra-low-power technologies. Full article

Unmanned aerial vehicles (UAVs) are promising and powerful aerial platforms that can execute a variety of complex tasks. However, the increasing complexity of tasks and number of UAV nodes pose significant challenges for UAV sensing networks, such as limiting the spectral resources and increasing device complexity. A potential solution is to implement full-duplex (FD) technology in UAV sensor network transceivers. Although appropriate self-interference (SI) cancellation techniques have been employed in the digital domain, the amplitude of the signal of interest (SoI) is relatively small and can be obscured by SI, especially over longer distances. Moreover, the introduction of phase offsets when filtering measurement signals can lead to signal distortion, resulting in estimation errors in the measurement results. To address these issues, this paper presents a joint transmit (TX) and receive (RX) beamforming algorithm based on the penalty dual decomposition (PDD) algorithm, which considers the constraints of transmission power, reception power, and residual SI power. The simulation analyses demonstrate that with a limited number of antennas, the proposed joint TX-RX beamforming algorithm can effectively suppress SI by up to 140 dB, yielding high-precision measurements in UAV sensor networks without compromising the accuracy of the control signals. Compared with that of the traditional frequency-division duplex (FDD) mode, the measurement accuracy is not decreased; compared with those of the time-division duplex (TDD) mode, the distance and speed measurement accuracies of the UAVs are increased by 10 m and 1.5 m/s, respectively, in the FD mode because there is no interruption of the tracking loop and no continuous retracking in the FD mode. Full article

Low-pass filters with bandwidths larger than several GHz are required in many applications, such as anti-aliasing filters in high-speed ADCs and pulse-shaping filters in high-speed DACs. In highly integrated applications, low area occupation and power consumption are key specifications, so inductor-less implementations are to be preferred. Furthermore, full CMOS implementations provide an advantage in terms of technology availability and cost. In this paper, we present an inductor-less CMOS biquad stage based on the super source follower topology that provides an 8 GHz cutoff frequency and a low power consumption of 0.42 mW per pole, showing remarkable performance also in terms of bandwidth and dynamic range. The availability of two separate current sources allows independent tuning of natural frequency and quality factor. The stage can be implemented in two complementary ways, exploiting NMOS and PMOS input devices, respectively, thus simplifying cascadability. The two complementary biquads have been implemented in the STMicroelectronics FDSOI 28 nm CMOS process and extensively simulated and provide stable performance under PVT variations and mismatches. The area occupation is about 387.5 μm² per biquad, one of the lowest in the literature. The figures-of-merit are remarkable, as the filters achieve excellent power efficiency, very low area occupation, and good dynamic range. Full article

The core–shell junctionless MOSFET (CS-JL FET) meets the process requirements of FD-SOI technology. The transistor body comprises a heavily doped ultrathin layer (core linking the source and the drain), located underneath an undoped layer (shell). Drain current, transconductance, and capacitance characteristics demonstrate striking performance improvement compared with conventional junctionless MOSFETs. The addition of the shell results in one order of magnitude higher mobility (peak value), transconductance, and drive current. The doping and thickness of the core can be engineered to achieve a positive threshold voltage for normally-off operation. The CS-JL FET is compatible with back-biasing and downscaling schemes. The physical mechanisms are revealed by emphasizing the roles of the main device parameters. Full article

A low-power, high-speed adder circuit topology based on current-starved inverters is presented to provide a basic arithmetic function for low-power, high-frequency signal processing systems. The adder is designed in 22 nm FDSOI (Fully-Depleted Silicon-on-Insulator) technology and is suitable for operation up to 5 GHz (Giga-Hertz). The proposed adder utilizes current-starved inverters to implement low-power operation while still maintaining signal integrity for high-frequency sine signals. The circuit uses a differential input and output structure to mitigate potential noise coupling onto any high-frequency signal pathways. The proposed solution differs from standard adder architectures by utilizing a fully analog signal processing design, accepting analog inputs while outputting an analog signal, and offering suitable functionality at Giga-Hertz level signals as compared to other relevant works. The simulated experimental results show the power consumption to be approximately 150 nW at 0.8 V supply with an input-referred noise of 6.091 nV/Hz at 5 GHz. Full article

The non-ideality aspects of phase change memory (PCM) such as drift and resistance variability can pose significant obstacles in neuromorphic hardware implementations. A unique drift and variability compensation strategy is demonstrated and implemented in an FD-SOI SNN hardware unit composed of embedded phase change memories (ePCMs), current attenuators, and spiking neurons. The effect of drift and variability compensation on inference accuracy is tested on the MNIST dataset to show that our drift and variability mitigation strategy is effective in sustaining its accuracy over time. The variability is reduced by up to 5% while the drift coefficient is reduced by up to 57.8%. The drift is compensated and the SNN classification accuracy is sustained for up to 2 years with intrinsic control-free hardware that tracks the ePCM current over time and consumes less than 30 µW. The results are based on ePCM chip experimental data and pos-layout simulation of a test chip comprising the proposed circuit solution. Full article

Binary neural networks (BNNs) that use 1-bit weights and activations have garnered interest as extreme quantization provides low power dissipation. By implementing BNNs as computation-in-memory (CIM), which computes multiplication and accumulations on memory arrays in an analog fashion, namely, analog CIM, we can further improve the energy efficiency to process neural networks. However, analog CIMs are susceptible to process variation, which refers to the variability in manufacturing that causes fluctuations in the electrical properties of transistors, resulting in significant degradation in BNN accuracy. Our Monte Carlo simulations demonstrate that in an SRAM-based analog CIM implementing the VGG-9 BNN model, the classification accuracy on the CIFAR-10 image dataset is degraded to below 50% under process variations in a 28 nm FD-SOI technology. To overcome this problem, we present a variation-aware BNN framework. The proposed framework is developed for SRAM-based BNN CIMs since SRAM is most widely used as on-chip memory; however, it is easily extensible to BNN CIMs based on other memories. Our extensive experimental results demonstrate that under process variation of 28 nm FD-SOI, with an SRAM array size of $128\times 128$, our framework significantly enhances classification accuracies on both the MNIST hand-written digit dataset and the CIFAR-10 image dataset. Specifically, for the CONVNET BNN model on MNIST, accuracy improves from 60.24% to 92.33%, while for the VGG-9 BNN model on CIFAR-10, accuracy increases from 45.23% to 78.22%. Full article

Some applications, such as satellites, require ultralow power and high-radiation resilience. We developed a12Tsoft error-resilient SRAM cell, TA-Quatro, to deliver in-memory computing (IMC) for those applications. Based on our TA-Quatro cell, we implemented an IMC circuit to support binary weights and ternary activations in a single SRAM cell. Our simulation under 28 nm FD-SOI technology demonstrates that the TA-Quatro IMC circuit maintains good IMC stability at a scaled supply of 0.7Vand achieves ternary activation without needing analog-to-digital converters. These advancements significantly enhance the power efficiency of the proposed IMC circuit compared to state-of-the-art works. Full article

In this paper, we propose a cost-effective way to tune RF process technology to achieve well-optimized RF and mmWave performances/power/area by tweaking back-end-of-line (BEOL) configurations. This paper suggests that the most favorable altitude is that of an ultra-thick-metal (UTM) layer from the silicon substrate, and the effort also focuses on the calibration of the via height/pitch underneath the UTM to satisfy the least ohmic loss in the interface between the active and passive device components. We implemented a process optimization in a 28 nm fully depleted silicon-on-insulator (FD-SOI) process technology, and the results show performance enhancements on the inductor, achieving a 14.8% quality factor improvement and a 13.1% self-resonance frequency improvement. This paper also showcases how the process optimization boosts 29 GHz LNA performances, with a 31.8% gain in boosting and a 9.1% reduction in noise-figure. Full article

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR). Full article

After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures. Full article

In this paper, a low-power Injection-Locked Clock and Data Recovery (ILCDR) using a 28 nm Ultra-Thin Body and Box-Fully Depleted Silicon On Insulator (UTBB-FDSOI) technology is presented. The back-gate auto-biasing of UTBB-FDSOI transistors enables the creation of a Quadrature Ring Oscillator (QRO) reducing both size and power consumption compared to an LC tank oscillator. By injecting a digital signal into this circuit, we realize an Injection-Locked Oscillator (ILO) with low jitter. Thanks to the good performance of this oscillator, we propose a low-power ILCDR with fast locking time and low jitter for burst-mode applications. The main novelty consists of the implementation of a complementary QRO based on back-gate control using FDSOI technology to realize a simple and efficient ILCDR circuit. With a Pseudo-Random Binary Sequence (PRBS7) at 868 Mbps, the recovered clock jitter is 26.7 ps (2.3% UIp-p) and the recovered data jitter is 11.9 ps (1% UIp-p). With a 0.6 V power supply, the power consumption is 318μW. All the results presented here are based on post-layout simulations, as no prototypes have been produced. Similarly, we can estimate the surface area of the chip (without the pad ring) at around 6600 μm². Full article

This paper presents a broadband millimeter-wave (mm-Wave) low noise amplifier (LNA) designed in a 22 nm fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Electromagnetic (EM) simulations suggest that the LNA has a 3-dB bandwidth (BW) from 17.8 to 42.4 GHz and a fractional bandwidth (FBW) of 81.7%, covering the key frequency bands within the mm-Wave 5G FR2 band, with its noise figure (NF) ranging from 2.9 to 4.9 dB, and its input-referred 1-dB compression point (IP1dB) of −17.9 dBm and input-referred third-order intercept point (IIP3) of −8.5 dBm at 28 GHz with 15.8 mW DC power consumption (P_DC). Using the FOM (figure-of-merit) developed for broadband LNAs (FOM = 20 × log((Gain[V/V] × S₂₁-3 dB-BW [GHz])/(P_DC [mW] × (F-1)))), this LNA achieves a competitive FOM (FOM = 18.9) among reported state-of-the-art mm-Wave LNAs in the literature. Full article