Pathogenic variants in DNA-damage regulated autophagy modulator 2 gene (DRAM2) cause a rare autosomal recessive retinal dystrophy and its disease course is not well understood. We present two Slovenian patients harboring a novel DRAM2 variant and a d...
DRAM2-associated retinopathy is a rare inherited retinal dystrophy, and its outcome has not been determined. A single retinal involvement by a mutation of the DRAM2 gene is unexplained. We found three unrelated patients with a disease-causing DRAM2 v...
Recently, 3D-stacked dynamic random access memory (DRAM) has become a promising solution for ultra-high capacity and high-bandwidth memory implementations. However, it also suffers from memory wall problems due to long latency, such as with typical 2...
The cells in dynamic random access memory (DRAM) degrade over time as a result of aging, leading to poor performance and potential security vulnerabilities. With a globalized horizontal supply chain, aged counterfeit DRAMs could end up on the market,...
Damage-Regulated Autophagy Modulator 1 (DRAM1) is an infection-inducible membrane protein, whose function in the immune response is incompletely understood. Based on previous results in a zebrafish infection model, we have proposed that DRAM1 is a ho...
Recent developments have increased the demand for adequate security solutions, based on primitives that cannot be easily manipulated or altered, such as hardware-based primitives. Security primitives based on Dynamic Random Access Memory (DRAM) can p...
Recently, one-transistor dynamic random-access memory (1T-DRAM) cells having a polysilicon body (poly-Si 1T-DRAM) have attracted attention as candidates to replace conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). P...
In response to the increasing manufacturing complexity/cost in maintaining DRAM advancements through traditional scaling, three-dimensional integrated circuits (3D ICs) and 2.5-dimensional ICs with Si interposers are known as promising candidates to...
This paper presents a pseudo-static gain cell (PS-GC) with extended retention time for an embedded dynamic random-access memory (eDRAM) macro for analog processing-in-memory (PIM). The proposed eDRAM cell consists of a two-transistor (2T) gain cell w...
A novel vertical dual surrounding gate transistor with embedded oxide layer is proposed for capacitorless single transistor DRAM (1T DRAM). The embedded oxide layer is innovatively used to improve the retention time by reducing the recombination rate...
A capacitorless one-transistor dynamic random-access memory device (1T-DRAM) is proposed to resolve the scaling problem in conventional one-transistor one-capacitor random-access memory (1T-1C-DRAM). Most studies on 1T-DRAM focus on device-level oper...
The performance bottleneck arising from the speed disparity between the CPU and DRAM highlights the inherent limitations of the von Neumann architecture. To address this issue, we propose a PIM architecture based on a 2T DRAM structure. The proposed...
DNA damage-regulated autophagy modulator protein 1 (DRAM1), a multi-pass membrane lysosomal protein, is reportedly a tumor protein p53 (TP53) target gene involved in autophagy. During cerebral ischemia/reperfusion (I/R) injury, DRAM1 protein express...
Dynamic random access memory (DRAM) circuits require periodic refresh operations to prevent data loss. As DRAM density increases, DRAM refresh overhead is even worse due to the increase of the refresh cycle time. However, because of few the cells in...
With technology scaling, maintaining the reliability of dynamic random-access memory (DRAM) has become more challenging. Therefore, on-die error correction codes have been introduced to accommodate reliability issues in DDR5. However, the current sol...
Capacitorless one-transistor dynamic random-access memory cells that use a polysilicon body (poly-Si 1T-DRAM) have been studied to overcome the scaling issues of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM). Gen...
In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using tech...
A capacitorless one-transistor dynamic random-access memory device that uses a poly-silicon body (poly-Si 1T-DRAM) has been suggested to overcome the scaling limit of conventional one-transistor one-capacitor dynamic random-access memory (1T-1C DRAM)...
This paper introduces an n-type pseudo-static gain cell (PS-nGC) embedded within dynamic random-access memory (eDRAM) for high-speed processing-in-memory (PIM) applications. The PS-nGC leverages a two-transistor (2T) gain cell and employs an n-type p...
A multi-layer stacked Dynamic Random Access Memory (DRAM) platform is introduced to address the memory wall issue. This platform features high-density vertical interconnects established between DRAM units for high-capacity memory and logic units for...
The Distress Risk Assessment Method (DRAM) was presented by Main, Wood and Hillis in 1992 as a simple means of assessing the risk of failure due to psychosocial factors in spine surgery. To our knowledge, it has not been used in our setting. The aim...
In this article, we systematically analyze the electrical characteristics of 2T0C DRAM unit cells for compute-in-memory (CIM) applications, focusing on the on/off current ratio, coupling effects, and retention time, with respect to the NN (NMOS-NMOS)...
This study investigates the impact of four parameters—gate angles, fin height controlled through gate overlaps and the distance from fin to source/drain, and substrate bottom doping concentration—on the row hammer effect (RHE) in DRAM cel...
The Pass Gate Effect (PGE), often referred to as adjacent cell interference, presents a significant challenge in dynamic random-access memory (DRAM). In this study, we investigate the impact of PGE and propose innovative solutions to address this iss...
With the significant growth in modern computing systems, dynamic random access memory (DRAM) has become a power/performance/energy bottleneck in data-intensive applications. Both the power management mechanism and downscaling method face decreasing p...
The compute-in-memory (CIM) which embeds computation inside memory is an attractive scheme to circumvent von Neumann bottlenecks. This study proposes a logic-compatible embedded DRAM architecture that supports data storage as well as versatile digita...
High-grade gliomas are extremely fatal tumors, marked by severe hypoxia and therapeutic resistance. Autophagy is a cellular degradative process that can be activated by hypoxia, ultimately resulting in tumor advancement and chemo-resistance. Our stud...
Traditional authentication techniques, such as cryptographic solutions, are vulnerable to various attacks occurring on session keys and data. Physical unclonable functions (PUFs) such as dynamic random access memory (DRAM)-based PUFs are introduced a...
In digital pixel sensors (DPS), memory elements typically occupy large silicon area of the pixel, which significantly reduces the pixel’s fill factor while increases its size, power and cost. In this work, we propose to reduce DPS memory’s area and p...
Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume high...
These days, the demand on electronic systems operating at high temperature is increasing owing to bursting interest in applications adaptable to harsh environments on earth, as well as in the unpaved spaces in the universe. However, research on memor...
Dynamic random access memory (DRAM) serves as a critical component in medical equipment. Given the exacting standards demanded by medical equipment products, manufacturers face pressure to improve their product quality. The electrical characteristics...
The environment-dependent feature of physical unclonable functions (PUFs) is capable of sensing environment changes. This paper presents an analysis and categorization of a variety of PUF sensors. Prior works have demonstrated that PUFs can be used a...
Emerging applications like deep neural networks require high off-chip memory bandwidth and low dynamic loaded Double Data Rate SDRAM (DDR) latency. However, under the stringent physical constraints of chip packages and system boards, it is extremely...
The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedd...
To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tool...
In modern multi-core processors, memory request latency critically constrains overall performance. Prefetching, a promising technique, mitigates memory access latency by pre-loading data into faster cache structures. However, existing core-side prefe...
In mobile dynamic random access memory (DRAM) receivers, the data strobe complement (DQS_c) and data strobe true (DQS_t) signals must be maintained at high and low voltage levels in the write data strobe off (WDQS_OFF) mode. Therefore, we developed a...
This paper presents, for the first time, a comprehensive detailed design of experiment (DOE) based system level electrostatic discharge (ESD) coupling analysis of high-speed dynamic random access (DRAM) memory modules. The sensitive traces and planes...
As the scope of artificial intelligence (AI) expands and the structure becomes more complex, the amount of data for inference and training has increased. In traditional computer architectures, the memory bandwidth limitations have intensified bottlen...
As semiconductor devices become smaller, their performance and integration density improve, but new negative effects emerge due to the reduced distance between structures. In DRAM, these effects can lead to data loss or require additional refresh cyc...
16 August 2022
The emergence of different virus variants, the rapidly changing epidemic, and demands for economic recovery all require continual adjustment and optimization of COVID-19 intervention policies. For the purpose, it is both important and necessary to ev...
In this paper, we proposed the development of stackable 3D ferroelectric random-access memory (FeRAM), with two select transistors and n capacitors (2TnC), to address scaling limitations for bit density growth and the complicated manufacturing of 3D...
Physical Unclonable Functions (PUFs) based on the retention times of the cells of a Dynamic Random Access Memory (DRAM) can be utilised for the implementation of cost-efficient and lightweight cryptographic protocols. However, as recent work has demo...
High-bandwidth memory 2 (HBM2) vertically stacks multiple dynamic random-access memory (DRAM) dies to achieve a small form factor and high capacity. However, it is difficult to diagnose HBM2 issues owing to their structural complexity and 2.5D integr...
Computation of convolutional neural network (CNN) requires a significant amount of memory access, which leads to lots of energy consumption. As the increase of neural network scale, this phenomenon is further obvious, the energy consumption of memory...
The widespread computer network has been changing drastically and substantially since blockchain and IoT entered the stage. Blockchain is good at protecting data transactions between logical nodes with a desirable guaranty. Internet of Things (IoT),...
The key challenges of manycore systems are the large amount of memory and high bandwidth required to run many applications. Three-dimesnional integrated on-chip memory is a promising candidate for addressing these challenges. The advent of on-chip me...
With the downscaling in device sizes, process-induced parameter variation has emerged as one of the most serious problems. In particular, the parameter fluctuation of the dynamic random access memory (DRAM) sense amplifiers causes an offset voltage,...
General-purpose graphics computing on processing units (GPGPUs) face significant performance limitations due to memory access latencies, particularly when traditional memory hierarchies and thread-switching mechanisms prove insufficient for complex a...
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