Search Results (641)

This paper presents a low-noise analog front-end (AFE) integrated circuit (IC) circuit for capacitive micro-electromechanical system (MEMS) accelerometers that can be used for optical image stabilization (OIS) in various optical imaging systems. The AFE circuit design features a fully differential chopper stabilization technique that efficiently minimizes low-frequency 1/f noise and parasitic coupling. The AFE circuit chip is fabricated in a 0.18 $\mathsf{\mu }$m complementary metal-oxide-semiconductor (CMOS) technology and co-packaged with an x-axis capacitive MEMS accelerometer based on a silicon-on-glass (SOG) process. The SOG accelerometer has a footprint of 1000 $\mathsf{\mu }\mathrm{m}$ $\times$ 950 $\mathsf{\mu }\mathrm{m}$. The packaged system demonstrates a sensitivity of 342 mV/g and a nonlinearity of 1.1% between −1 g and +1 g, a dynamic range of 88 dB, and an equivalent noise floor of 14 $\mathsf{\mu }\mathrm{g}/\sqrt{\mathrm{H}\mathrm{z}}$. Full article

A monolithic digital Silicon Photomultiplier (SiPM) featuring 1024 microcells with a 30-micrometer pitch and a 50% fill factor has been designed in a 110-nanometer CMOS image sensor technology. The device under consideration integrates both SPAD sensors and front-end electronics in the same substrate. It can count up to 1024 photons in less than 22 ns, while assigning timestamps to the first and last detected photons with a time resolution of less than 100 ps. A parallel counter structure combined with a fast adder tree provides photon counting in digital form with low latency, whereas a carefully balanced fast NAND tree ensures a fixed-pattern time uncertainty not exceeding 26 ps. The architecture incorporates in-pixel memory for individual cell disabling and configurable thresholding on the timing signal for noise mitigation. In order to optimize the fill factor, a part of the electronics is placed outside the array, while the most sensitive elements of the timing and counting circuits are laid out close to the sensor, in the SPAD array. A serial readout is employed to provide a single output connection per SiPM, thereby simplifying system integration. Full article

The goal of this research is to develop a predictive model that determines how low-frequency Electromagnetic Interference (EMI) affects the leakage current behavior of CMOS transistors. Although developed and validated using NMOS devices, the modeling framework can be extended to PMOS transistors; experimental validation of PMOS devices is planned for future work. The model provides essential physical parameter-based analysis of nanoscale device EMI susceptibility during low-frequency operation. The model demonstrates high accuracy and practicality through experimental verification of test chips built with standard TSMC CMOS technology nodes. The findings highlight that modern CMOS designs must account for low-frequency EMI, which can induce leakage shifts significant enough to impact EMC compliance, functional robustness, and reliability in ultra-low-power and near-threshold applications. The research delivers a practical method for designers to evaluate and reduce EMI-induced leakage in integrated circuits. Full article

The 100 GHz-class ultrafast photonic integrated circuit (PIC) positions itself as a promising technology in the post-Moore era, when the bandwidth limit of metallic interconnections constrains current electronic integrated circuits. Nevertheless, the lack of an effective on-chip, CMOS-compatible laser source challenges the ongoing development of PIC. Germanium straintronics facilitate bandgap transformation from indirect to direct, thereby enabling effective band-to-band radiative recombination. Some parameters, such as nanowire diameters or crystalline orientation and strain direction, have a profound effect on the bandgap transformation of Ge nanowires. In this review, we will discuss changes in the fundamental physical properties of Ge nanowires under strain, including mechanical, electronic, optical, and thermal properties. Subsequently, we summarize common methods for strain engineering, as well as novel approaches that have emerged in recent years. Some notable application cases reported in the last few decades will be discussed in detail. This review may fill knowledge gaps and provide a solid background for forthcoming investigations of on-chip strained Ge lasers. Full article

Secondary power supplies are an integral part of any complex device that requires power to different circuit nodes. This includes various kinds of telecommunication equipment, the aerospace industry, battery chargers, etc. Secondary power supplies include the most common pulse converters of both the boost, buck, and buck–boost variety, as well as forward, flyback, and push–pull converters. In particular, a galvanic isolation option may be considered for push–pull types. The use of multi–channel secondary power supplies is relevant for the space industry and satellites, where it is necessary to support the operation of many related devices. The efficiency of such devices is high due to their small number of elements and their simplicity of control. PWM (pulse width modulation) controllers can be considered as the last statement. In turn, the presence of radiation-resistant CMOS technology is required in outer space conditions, which is possessed by the PWM controller considered in this paper. Also, high efficiency and small dimensions can be achieved using planar technology. Here, one such secondary power supply, based on the PWM controller 5315EU015 with a power of 10 W, is considered, as well as the proposed design of a planar transformer. A mathematical model obtained from the algebraization of differential equations method, and from the PSIM software v. 22.2 simulation results and experiments is presented. Full article

Memristors are valuable elements with very good memory and switching features. They have minimal power consumption, nano-scale sizes, and a possibility for integration with high-density Complementary Metal Oxide Semiconductor (CMOS) integrated circuits. They are applicable in neural networks, memory crossbars, and different electronic devices. This work considers some improved and existing models for memristors, functioning at high-frequency signals with a high speed and very good effectiveness. The main parasitic parameters—series resistance, capacitance, and small-signal direct current (DC) voltage and current shifting signals—are taken into account. An additional leakage conductance is analyzed as a parasitic component. The influence of the parasitic parameters on the normal functioning of memristor-based circuits is analyzed and evaluated at hard-switching and soft-switching modes. For investigations of the main characteristics of the considered models and their applicability in memory arrays, Linear Technology Simulation Program with Integrated Circuits Emphasis (LTSPICE) library models are generated and analyzed. The considered models operate at low-, middle- and high-frequency signals, clearly demonstrating the main properties of memristors. Their appropriate operation in passive memory arrays is analyzed and established. The proposed models have a 26% enhanced accuracy in fitting experimental i-v relations. They ensure good memory and switching properties for memory arrays. This work could be a suitable step towards the design and manufacturing of ultra-high-density memristor-based integrated chips. Full article

This paper presents a novel, minimalist floating memristor emulator circuit designed for low-power biomedical analog front ends. The proposed topology requires only two dynamic threshold MOS (DTMOS) transistors and one capacitor, constituting one of the most compact memristor emulators reported. The circuit operates without static power consumption and exploits the body-effect coupling in DTMOS devices to generate a state-dependent resistance. Comprehensive simulation in a 0.18 μm CMOS process verifies core memristive characteristics: a frequency-dependent pinched hysteresis loop tunable via capacitance, non-volatile memory, and robustness across temperature and process variations. Experimental validation using a discrete CD4007-based prototype confirms the pinched hysteresis loop from 100 Hz to 800 kHz, with a maximum simulated operating frequency of 500 MHz. A comparative analysis demonstrates that the design achieves a favorable trade-off, simultaneously minimizing transistor count and power while providing floating operation and high-speed performance. These attributes make the emulator a compelling candidate for integration into adaptive, area and power constrained biomedical signal conditioning systems. Full article

This work presents a systematic design flow for the fundamental building blocks (namely, the low-noise amplifier and the down-conversion mixer) of an analog receiver for 5G backhauling systems implemented in SiGe BiCMOS technology. The proposed methodology enables the sizing and optimization of receiver blocks up to post-layout simulations, starting from the specified performance requirements. It accounts for both the parasitic effects of active devices and the distributed effects of interconnects. The design flow was applied using STMicroelectronics BiCMOS55X technology to develop low-noise amplifiers and D-band to E-band downconverters capable of covering the 130–150 GHz and 150–165 GHz sub-bands. Preliminary measurement results obtained from both the standalone LNA blocks and the complete receivers are presented and discussed. Full article

Mixers are integral components in RF circuits for frequency conversion and are present in almost all RF front-ends. The relentless advancement of mobile communication standards, particularly towards 5G-Advanced and 6G, imposes ever more stringent and multi-dimensional performance requirements on mixer design. While previous surveys have capably summarized mixer technologies, this review distinguishes itself by providing a comprehensive and critical examination of millimeter-wave and sub-THz silicon-based integrated mixers, with explicit coverage extended from core RF bands to beyond 170 GHz. We place particular emphasis on the unique challenges and trade-offs inherent to silicon (CMOS and SiGe BiCMOS) platforms at these high frequencies. This work first summarizes the structural frameworks and underlying principles of mixers, examines multiple mixer variants, and performs an in-depth analysis of their key performance characteristics, encompassing conversion gain, noise figure (with distinctions between single-sideband (SSB) and double-sideband (DSB) definitions), isolation, and related metrics. Then, it compares and discusses the design of several mixers, especially analyzing their innovative points and key technologies, while critically evaluating their inherent limitations and trade-offs. Furthermore, a dedicated section synthesizes the most recent research trends, including heterogeneous integration, AI/ML-assisted design, and mixer architectures for integrated sensing and communication (ISAC), thereby addressing a notable gap in the current literature. Finally, it concludes with an outlook on future challenges and opportunities for mixers in next-generation communication systems. Full article

This paper proposes a corner analysis approach for CMOS circuits taking into the account radiation effects. The presented simulation approach is implemented using the open-source design automation (EDA) software QUCS-S 25.2.0 and Ngspice 45. It was developed a radiation-sensitive field-effect transistor (RADFET) SPICE macromodel representing threshold voltage shift versus radiation dose. The extraction procedure for this model is based on statistical measurements of pMOS transistors and process corner models (Slow, Typical, Fast) and involves percentile analysis. The article proposes an original design of the RADFET-based radiation sensor with RADFET device and CMOS readout circuit placed on the same die, which allows us to simplify the dosimeter schematic. The sensor output parameter dependency on process parameters, supply voltage, and temperature was investigated using the proposed simulation approach. Full article

A polarization-insensitive compact optical modulator based on a graphene-hybrid surface plasmon polariton waveguide is proposed. The inverted U-shaped structure enables the synchronous control of TE/TM modes via Fermi level tuning, achieving a maximum attenuation of 0.247 dB/μm (E_f = 0.3 eV) and a minimum attenuation of 0.026–0.028 dB/μm (E_f = 1.0 eV) at 3 THz, with a polarization-dependent modulation error of only 0.002 dB/μm. The 100 μm × 30 μm device operates effectively at 2.5 THz (120 μm), demonstrating its potential for integrated photonic circuits. Additionally, the proposed modulator is compatible with Complementary Metal-Oxide-Semiconductor (CMOS) technology. The excellent ultra-broadband modulation performance of the graphene-hybrid plasmonic waveguide (GHPW) thereby paves the way for high-speed communication, non-destructive testing, biomedical sensing and optical computing. Full article

For sensing applications, a complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a lateral overflow integration capacitor (LOFIC) is in high demand. The LOFIC CIS can achieve high-dynamic-range (HDR) imaging by combining a low-conversion-gain (LCG) signal for large maximum signal electrons and a high-conversion-gain (HCG) signal for a low electron-referred noise floor. However, the LOFIC CIS faces challenges regarding the power consumption and circuit area when reading both HCG and LCG signals. To address these issues, this study proposes a readout circuit composed of area-efficient MOS capacitors using a folding DC operating point technique and an in-column signal selector for an on-chip HDR merger of HCG and LCG signals. A 10-bit test chip was fabricated with a $0.18$ µm CMOS process with MOS capacitors. The fabricated chip maintains high linearity, achieving an integral nonlinearity (INL) of +7.17/−6.93 LSB for the HCG signal and +7.95/−7.41 LSB for the LCG signal. Furthermore, the proposed design achieves a $14.92\%$ reduction in the average power consumption of the total readout circuit and a $36.5\%$ reduction in the readout circuit area. Full article

The inherently high-voltage-length product (V_πL) of thin-film lithium niobate (TFLN) modulators in the O-, C-, and L-telecom bands restricts further scaling of photonic integrated circuits’ bandwidth density, driving their migration toward shorter operating wavelengths. Nevertheless, the corresponding grating couplers, as critical optical input/outputs (optical I/Os) interfaces, remain largely undeveloped. Here, we demonstrate an 850 nm TFLN grating coupler designed based on topological unidirectional guided resonance (UGR). By breaking C₂ symmetry of the unit cell and precisely tailoring its geometry, we achieve unidirectional upward radiation with a 63.7 dB up/down intensity ratio. Subsequent apodization of groove widths and periods enables precise control of the electrical field distribution in both real and momentum spaces. This yields a vertical-cavity surface-emitting laser (VCSEL)-matched, highly fabrication-tolerant TFLN grating coupler that attains, to the best of our knowledge, the highest simulated coupling efficiency of −0.6 dB without mirrors or hybrid materials. This work delivers a high-efficiency, layout-flexible, and complementary metal oxide semiconductor (CMOS)-compatible optical I/Os solution for short-wavelength TFLN modulators with low V_πL. It offers substantial engineering value and broad applicability for on-chip light source integration and high-bandwidth-density short-reach optical interconnects. Full article

Infrared (IR) photodetectors are indispensable to modern optoelectronic systems, ranging from night vision imaging, surveillance, and industrial process control to environmental monitoring and medical diagnostics. However, traditional detectors based on bulk semiconductors are constrained by prohibitive fabrication costs and the stringent requirement for bulky cryogenic cooling, which severely hinders their widespread deployment in Size, Weight, and Power (SWaP)-sensitive scenarios. Silicon-based on-chip integration, leveraging compatibility with mature CMOS processes, has emerged as a transformative paradigm. It enables the realization of fully functional photonic integrated circuits (PICs) capable of on-chip sensing and high-speed data transmission, offering a pathway toward miniaturized and cost-effective architectures. This article provides a review of recent progress in silicon-based infrared photodetectors across three core material systems: Group IV (Ge/GeSn), III–V compounds, and two-dimensional (2D) materials. In the end, we offer an outlook on the development trends of next-generation intelligent sensing systems driven by optoelectronic convergence. Full article

As the mainstream technology solution for deep imaging LiDAR, dToF measurement has been widely applied in emerging fields such as environmental perception and obstacle recognition, 3D terrain reconstruction, real-time motion capture, and drone obstacle avoidance navigation due to its advantages of high resolution, long-range detection capability, and high sensitivity. In order to adapt to functional applications in different scenarios, the resolution of TDC needs to be adjustable and can work normally in different environments. In view of this, this article studies the pixel array and TDC circuit in the chip and locks a voltage-controlled ring oscillator (VCRO) with the same structure as the pixel to a fixed frequency through a PLL structure. Then copy the control voltage of the locked VCRO to the control terminal of the TDC in each pixel. In an ideal situation, this control voltage can make the oscillation frequency of VCRO within the pixel consistent with the locking frequency of VCRO within the PLL, and insensitive to changes in PVT. This study developed a module expandable 16 × 16-pixel array dToF sensor chip based on TDC architecture using CMOS technology. Finally, six configurable 16 × 16-pixel subarrays were integrated and constructed into a 32 × 48 large-scale dToF sensor chip through modular splicing. The top-level layout design was completed using SMIC 180 nm technology, with a layout area of 5285 µm × 3669 µm. Post-simulation verification showed that, under the testing conditions of a 400 MHz system clock and a 33.3 kHz frame rate, the dToF chip system performance indicators were: time measurement resolution of 156 ps, DNL < 1 LSB, INL < 0.85 LSB, and absolute ranging accuracy better than 2.5 cm. Full article