An LOFIC Image Sensor Readout Circuit with an On-Chip HDR Merger Achieving 36.5% Area and 14.9% Power Reduction ^†

Abstract

For sensing applications, a complementary metal oxide semiconductor (CMOS) image sensor (CIS) with a lateral overflow integration capacitor (LOFIC) is in high demand. The LOFIC CIS can achieve high-dynamic-range (HDR) imaging by combining a low-conversion-gain (LCG) signal for large maximum signal electrons and a high-conversion-gain (HCG) signal for a low electron-referred noise floor. However, the LOFIC CIS faces challenges regarding the power consumption and circuit area when reading both HCG and LCG signals. To address these issues, this study proposes a readout circuit composed of area-efficient MOS capacitors using a folding DC operating point technique and an in-column signal selector for an on-chip HDR merger of HCG and LCG signals. A 10-bit test chip was fabricated with a $0.18$ µm CMOS process with MOS capacitors. The fabricated chip maintains high linearity, achieving an integral nonlinearity (INL) of +7.17/−6.93 LSB for the HCG signal and +7.95/−7.41 LSB for the LCG signal. Furthermore, the proposed design achieves a $14.92\%$ reduction in the average power consumption of the total readout circuit and a $36.5\%$ reduction in the readout circuit area.

1. Introduction

In the development of the Internet of Things (IoT), complementary metal oxide semiconductor (CMOS) image sensors are expected to be deployed for machine vision under extreme illumination conditions, such as outdoor environments. In such scenarios, a high-dynamic-range (HDR) CMOS image sensor (CIS) is required to prevent objects from being overexposed or underexposed [1,2].

Many approaches have been proposed to realize HDR CISs. Nonlinear response techniques, such as logarithmic [3,4,5,6] compression, can reduce the data bandwidth by using a lower bit resolution. However, they are often avoided because the image signal processing required to create the final image is complex. In contrast, linear response technologies are preferred. These technologies include multi-exposure HDR (ME-HDR) [7,8,9,10] and single-exposure HDR (SE-HDR), which are favored, because their signal processing is simple. While ME-HDR is susceptible to motion artifacts, such as motion blur caused by the time lag between exposures, SE-HDR mitigates this problem. An SE-HDR CIS is primarily realized by dual conversion gain (DCG) pixels [11,12,13,14,15,16,17,18] or lateral overflow integration capacitor (LOFIC) pixels [13,16,19,20,21,22,23,24,25,26], which combine a low-conversion-gain (LCG) signal and a high-conversion-gain (HCG) signal. DCG and LOFIC technologies read out two signals from a pixel within a single exposure period: the HCG and LCG signals. The HCG readout improves the signal visibility under low-light conditions due to its low input-referred noise. However, its signal voltage range limits the maximum number of handling signal electrons. In contrast, the LCG readout increases the effective full-well capacity (FWC) to prevent saturation under high-light conditions. Consequently, DCG and LOFIC pixels achieve a high dynamic range. Notably, the LOFIC CIS achieves a higher dynamic range than the DCG CIS by integrating photoelectrons not only in the photodiode (PD) but also in an overflow capacitor. However, a two-channel readout circuit is required because the HCG and LCG signals from the LOFIC pixel have opposite polarities [23,25,26]. To overcome this limitation, our research group has proposed a single-channel readout circuit that sequentially processes the HCG and LCG signals [27]. In this approach, the HCG signal is processed by an inverting amplifier to further reduce the input-referred noise, while the LCG signal is processed by a non-inverting attenuator to further increase the effective FWC. This readout circuit employs a single analog-to-digital converter (ADC), but it requires dual SRAM to store both the HCG and LCG signals. Subsequently, a digital signal processing circuit selects the HCG signal if the LCG signal is below a given threshold. Otherwise, it selects the LCG signal and applies an appropriate digital gain. Thus, an HDR image is merged on a pixel-by-pixel basis using the HCG and LCG signals. A chip incorporating an HDR merger that integrates multiple readout data in a digital signal processor to achieve a high dynamic range has also been proposed [28]. However, analog readout circuits for the LOFIC pixel have been rarely addressed in the published literature.

In this work, we propose an improved single-channel readout circuit incorporating an in-column HDR merger for the LOFIC CIS. In the proposed circuit, the selection between the HCG and LCG signals is performed by an in-column signal selector to reduce the SRAM required for the converted digital signals. To further reduce the circuit area, we replace the metal–insulator–metal (MIM) capacitors, which occupy a significant portion, with MOS capacitors, whose capacitance density is higher. Furthermore, to reduce the average power consumption, the HCG/LCG selector halts the A/D conversion of the LCG signal if the initially converted HCG signal is selected. A bias sampling technique mitigates the interference noise caused by the selective A/D conversion of LCG signals in column-parallel ADCs. A test chip was fabricated with a 0.18 µm CMOS process.

Update from the Conference Proceeding

A conference proceeding version of this work appeared in IEEE SENSORS 2025 [29], and this extended version contains the following new content:

• An output signal range extension technique in the inverting amplifier (Section 3.1.1);
• An overview of the test chip and details of the evaluation setup (Section 4);
• Measurement results of the input–output characteristics and improved integral nonlinearity (INL) (Section 4);
• Measured images for a ramp input signal (Section 4);
• Measurement results of the selection ratio between HCG and LCG signals during column FPN evaluation (Section 4);
• Measured images in static-current mode (Section 4);
• Measured images in current-saving mode (Section 4).

This paper is organized as follows. Section 2 describes the pixel architecture and operation timing of the LOFIC CIS. Section 3 details the proposed readout circuit. Section 4 presents the evaluation results of the fabricated test chip. Finally, Section 5 concludes this paper.

2. Lateral Overflow Integration Capacitor (LOFIC) Pixel

Figure 1a shows the schematic of a one column readout circuit for the LOFIC CIS [27]. This column signal chain is configured with a single-channel readout circuit. This column is composed of a pixel array, a double sampling (DS) circuit, a 10-bit ADC, and a 2 × 10-bit SRAM. Each pixel includes the $\mathrm{PD}$, a transfer gate (${\mathrm{M}}_{\mathrm{TG}}$), a switching gate (${\mathrm{M}}_{\mathrm{SG}}$), a reset gate (${\mathrm{M}}_{\mathrm{RST}}$), a source-follower transistor (${\mathrm{M}}_{\mathrm{SF}}$), a select transistor (${\mathrm{M}}_{\mathrm{SEL}}$), the parasitic capacitance of the FD node (${\mathrm{C}}_{\mathrm{FD}}$), and an overflow charge sampling capacitor (${\mathrm{C}}_{\mathrm{S}}$). The DS circuit is composed of an inverting amplifier and a non-inverting attenuator. It derives the voltage difference between a reset level (${\mathrm{V}}_{\mathrm{RST}}$) and a signal level (${\mathrm{V}}_{\mathrm{SIG}}$) from the LOFIC pixel. The ADC converts this voltage difference into a digital value, which is then stored in the SRAM. Photoelectrons from the pixel are read out twice by the ${\mathrm{M}}_{\mathrm{SF}}$, which is a source-follower biased by a current source (${\mathrm{I}}_{\mathrm{BIAS}}$). First, while ${\mathrm{M}}_{\mathrm{SG}}$ is turned off, photoelectrons integrated in the PD are read out in HCG mode. When the PD becomes saturated, photoelectrons overflow into the FD node, passing beyond the potential barrier of ${\mathrm{M}}_{\mathrm{TG}}$. Similarly, when ${\mathrm{C}}_{\mathrm{FD}}$ is saturated, the photoelectrons further overflow into the ${\mathrm{C}}_{\mathrm{S}}$ capacitor, passing beyond the potential barrier of ${\mathrm{M}}_{\mathrm{SG}}$. Second, while ${\mathrm{M}}_{\mathrm{SG}}$ is turned on, photoelectrons integrated in the PD, ${\mathrm{C}}_{\mathrm{FD}}$, and ${\mathrm{C}}_{\mathrm{S}}$ are read out in LCG mode. Both the HCG and LCG signals stored in the SRAM are read out from the column-parallel ADCs. Subsequently, a digital signal processing circuit merges the HDR signal based on the HCG signal under low-illumination conditions or on the LCG signal under high-illumination conditions.

Figure 1b shows the operation timing diagram for the LOFIC pixel, while Figure 1c shows its corresponding electric potential diagram. At the beginning of the exposure period (${\mathrm{t}}_1$), transistors ${\mathrm{M}}_{\mathrm{TG}}$, ${\mathrm{M}}_{\mathrm{RST}}$, and ${\mathrm{M}}_{\mathrm{SG}}$ are turned on, resetting the PD, ${\mathrm{C}}_{\mathrm{FD}}$, and ${\mathrm{C}}_{\mathrm{S}}$. During the exposure period (${\mathrm{t}}_2$), photoelectrons under low illuminance are integrated in the PD. Conversely, under high illuminance, photoelectrons are integrated in the PD, ${\mathrm{C}}_{\mathrm{FD}}$, and ${\mathrm{C}}_{\mathrm{S}}$. At the end of the exposure period, ${\mathrm{M}}_{\mathrm{SEL}}$ is turned on to select the pixel row for readout.

The HCG reset level ${\mathrm{V}}_{\mathrm{RH}}$ is read out at ${\mathrm{t}}_3$ after ${\mathrm{M}}_{\mathrm{SG}}$ is toggled to share the dark current charge from the small ${\mathrm{C}}_{\mathrm{FD}}$ with the large ${\mathrm{C}}_{\mathrm{S}}$. The HCG signal level ${\mathrm{V}}_{\mathrm{SH}}$ is read out at ${\mathrm{t}}_4$, after ${\mathrm{M}}_{\mathrm{TG}}$ is toggled to transfer the photoelectron charge from the $\mathrm{PD}$ to ${\mathrm{C}}_{\mathrm{FD}}$. The voltage difference between ${\mathrm{V}}_{\mathrm{RH}}$ and ${\mathrm{V}}_{\mathrm{SH}}$ is derived by the subsequent DS circuit. The ${\mathrm{C}}_{\mathrm{FD}}$ reset noise, which is present in both ${\mathrm{V}}_{\mathrm{RH}}$ and ${\mathrm{V}}_{\mathrm{SH}}$, can be effectively eliminated by correlated double sampling (CDS) to produce a low-noise signal. This differential HCG signal exhibits a linear photo-conversion response under low illumination. However, under high illumination, the differential HCG signal decreases due to the overflow charge integrated in the ${\mathrm{V}}_{\mathrm{RH}}$ level. The conversion gain given by ${\mathrm{q}}_0/{\mathrm{C}}_{\mathrm{FD}}$ was as high as 160 µV/e⁻ in our previous work [30], where ${\mathrm{q}}_0$ and ${\mathrm{C}}_{\mathrm{FD}}$ are the elementary charge and the parasitic capacitance of the FD node, respectively.

The LCG signal level ${\mathrm{V}}_{\mathrm{SL}}$ is read out at ${\mathrm{t}}_5$, after the ${\mathrm{M}}_{\mathrm{SG}}$ gate is turned on, and ${\mathrm{M}}_{\mathrm{TG}}$ is toggled again to merge all the photoelectrons integrated in the $\mathrm{PD}$, ${\mathrm{C}}_{\mathrm{FD}}$, and ${\mathrm{C}}_{\mathrm{S}}$. Then, the LCG reset level ${\mathrm{V}}_{\mathrm{RL}}$ is read out at ${\mathrm{t}}_6$, after ${\mathrm{M}}_{\mathrm{RST}}$ is toggled again to reset ${\mathrm{C}}_{\mathrm{FD}}$ and ${\mathrm{C}}_{\mathrm{S}}$. The voltage difference between ${\mathrm{V}}_{\mathrm{SL}}$ and ${\mathrm{V}}_{\mathrm{RL}}$ is also derived by the DS circuit. The conversion gain provided by ${\mathrm{q}}_0/({\mathrm{C}}_{\mathrm{FD}}+{\mathrm{C}}_{\mathrm{S}})$ is as low as 10 µV/e⁻ [30], and thus, the LCG signal maintains a linear photo-conversion response even under high illumination. Although the LCG reset noise is large due to the differential double sampling between ${\mathrm{V}}_{\mathrm{SL}}$ and ${\mathrm{V}}_{\mathrm{RL}}$, it remains inconspicuous under high illumination if it is lower than the optical shot noise.

The subsequent digital signal processing circuit selects the HCG signal if the LCG signal is below a predetermined threshold. If the LCG signal is above that threshold, it selects the LCG signal. The combination of the low-noise HCG signal and the high FWC LCG signal enables the generation of a linear merged HDR signal by scaling the LCG signal. The selection between the HCG and LCG signals is performed based on the LCG signal level. This is because the HCG signal decreases under high illumination due to the saturation of the PD. Therefore, both the HCG and LCG signals must be A/D converted and stored in the SRAM for post-processing.

3. Proposed Readout Circuit

Figure 2 shows the schematic diagram for a single column of the proposed readout circuit with an in-column HDR merger for the LOFIC pixel. This architecture fundamentally consists of two main blocks, a DS circuit and a successive approximation register (SAR) ADC. The DS circuit provides two distinct signal paths consisting of an inverting amplifier dedicated to the HCG signal and a non-inverting attenuator for the LCG signal [27]. The polarity-inverted pixel output, the HCG and LCG signals, are polarity-aligned at the ADC input. The analog output of the DS circuit (${\mathrm{V}}_{\mathrm{ADC}}$) is subsequently digitized by the SAR-ADC. The SAR-ADC integrates a signal selector in addition to the typical components: a comparator, a 10-bit DAC, and a 10-bit SRAM. The comparator was designed with careful consideration of offset, power consumption, and bit error rate (BER) as a function of regeneration time.

This work proposes three key design features. First, the readout circuit area is reduced by using MOS capacitors, which offer a higher capacitance density than MIM capacitors. While MIM capacitors require a larger layout area, leading to longer signal lines and increased coupling, MOS capacitors enable a compact layout that reduces the coupling length. Additionally, a DC operating point folding technique is proposed to maintain high linearity. Second, the SRAM area is reduced by implementing an in-column signal selector for the HCG and LCG signals. This signal selector directs the merged HDR data to a single SRAM for storage. Third, a bias sampling circuit is introduced to suppress the column-to-column interference noise caused by halting the current based on the signal selection result. The interference noise is exacerbated when the signal selector selects the HCG signal and puts the ADC into sleep mode in certain columns during the A/D conversion of the LCG signal to save power consumption.

The operational principles of these circuits are detailed in the following subsections.

3.1. Readout Circuit Using MOS Capacitor

3.1.1. Inverting Amplifier

The inverting amplifier for the HCG signal is based on a switched-capacitor amplifier equipped with additional capacitors ${\mathrm{C}}_{\mathrm{AZ}}$ and ${\mathrm{C}}_{\mathrm{R}}$. The purpose of ${\mathrm{C}}_{\mathrm{AZ}}$ is to ensure that the MOS capacitors (${\mathrm{C}}_{\mathrm{S}}$ and ${\mathrm{C}}_{\mathrm{F}}$) operate in the inversion region. Even though a smaller ${\mathrm{C}}_{\mathrm{AZ}}$ would be preferred for area efficiency, ${\mathrm{C}}_{\mathrm{AZ}}$ is 100 fF because aggressive ${\mathrm{C}}_{\mathrm{AZ}}$ reduction would make the circuit excessively sensitive to the charge injection from the auto-zeroing switch. ${\mathrm{C}}_{\mathrm{S}}$ and ${\mathrm{C}}_{\mathrm{F}}$ are 800 and 100 fF, respectively, considering the kTC noise and device mismatch. During the autozeroing operation, when $\mathrm{\Phi }\mathrm{AZ}1$ and $\mathrm{\Phi }\mathrm{AZ}2$ are “High”, the bottom plates of ${\mathrm{C}}_{\mathrm{S}}$, ${\mathrm{C}}_{\mathrm{F}}$, and ${\mathrm{C}}_{\mathrm{AZ}}$ are biased to the ground AVSS. Figure 3a shows that the pixel reset voltage, ${\mathrm{V}}_{\mathrm{RH}}^{\prime }$ (2.1 V), accounting for both the feedthrough voltage drop from AVDD to ${\mathrm{C}}_{\mathrm{FD}}$ and ${\mathrm{V}}_{\mathrm{GS}}$ of ${\mathrm{M}}_{\mathrm{SF}}$, is higher than the MOS capacitor threshold voltage (0.7 V). Similarly, the amplifier negative input (1.4 V), which is a virtual short to ${\mathrm{V}}_{\mathrm{B}1}$, is higher than the threshold voltage. These conditions force ${\mathrm{C}}_{\mathrm{S}}$, ${\mathrm{C}}_{\mathrm{F}}$, and ${\mathrm{C}}_{\mathrm{AZ}}$ into the inversion region. ${\mathrm{C}}_{\mathrm{S}}$ remains in the inversion region for the subsequent pixel signal ${\mathrm{V}}_{\mathrm{SH}}^{\prime }$ because the HCG signal swing is limited. Similarly, ${\mathrm{C}}_{\mathrm{AZ}}$ remains in the inversion region because its voltage difference is held constant due to the virtual short of the op-amp, while ${\mathrm{C}}_{\mathrm{F}}$ also remains in the inversion region as the amplifier output voltage increases. Consequently, the inverting amplifier maintains a linear input–output characteristic. A typical inverting amplifier without ${\mathrm{C}}_{\mathrm{AZ}}$ suffers from nonlinear input–output characteristics because the ${\mathrm{C}}_{\mathrm{F}}$ capacitance decreases due to its accumulation or depletion region when $\mathrm{\Phi }\mathrm{AZ}1$ is “High”. The amplifier output is sampled and then held at the ADC input stage by a PMOS capacitor, ${\mathrm{C}}_{\mathrm{SH}}$. The bias voltage, ${\mathrm{V}}_{\mathrm{B}2}$, is set low (0.2 V) to ensure that ${\mathrm{C}}_{\mathrm{SH}}$ operates in the inversion region. When $\mathrm{\Phi }\mathrm{CL}$ is “High” for the reset phase, the top and bottom plates of ${\mathrm{C}}_{\mathrm{SH}}$ are biased to ${\mathrm{V}}_{\mathrm{B}2}$ and ${\mathrm{V}}_{\mathrm{B}1}$ (1.4 V), respectively. The substrate of ${\mathrm{C}}_{\mathrm{SH}}$ is shorted to its bottom plate to prevent the back-bias effect, as the voltage difference across ${\mathrm{C}}_{\mathrm{SH}}$ is critical in the readout circuit. The PMOS capacitor enables back-gate isolation even in column-parallel arrays.

The purpose of ${\mathrm{C}}_{\mathrm{R}}$ is to expand the output signal range of the telescopic op-amp adopted in this inverting amplifier. Figure 4 shows the schematic diagram and the output signal of the telescopic amplifier used in the circuit. In this context, the NMOS threshold voltage and the saturation drain voltage are ${\mathrm{V}}_{\mathrm{TH}}$ and ${\mathrm{V}}_{\mathrm{ON}}$, respectively. The amplifier is designed considering the speed, gain error, power consumption, and both input and output signal ranges, where the telescopic op-amp provides high gain, leading to a small gain error. However, a challenge with the telescopic op-amp is its limited output signal range, given by $AVDD-4V_{ON}-V_{TH}$. Therefore, this design expands the output signal range by adding capacitor ${\mathrm{C}}_{\mathrm{R}}$. An inverted AZ1 pulse, $\overline{\mathrm{\Phi }\mathrm{AZ}1}$, is applied to bottom plate of ${\mathrm{C}}_{\mathrm{R}}$ (see Figure 2). During autozeroing, when $\overline{\mathrm{\Phi }\mathrm{AZ}1}$ is “Low”, a charge of ${\mathrm{C}}_{\mathrm{R}}·{\mathrm{V}}_{\mathrm{B}1}$ is accumulated in ${\mathrm{C}}_{\mathrm{R}}$. After autozeroing, when $\overline{\mathrm{\Phi }\mathrm{AZ}1}$ is turned to “High”, charge ${\mathrm{C}}_{\mathrm{R}}·\mathrm{AVDD}$ is discharged (injected) from ${\mathrm{C}}_{\mathrm{R}}$ into the op-amp virtual ground node. Since the op-amp virtual ground node voltage (${\mathrm{V}}_{\mathrm{X}}$) is forced to ${\mathrm{V}}_{\mathrm{B}1}$, the amplifier’s output voltage $V_{DS}$ after autozeroing is dropped, as given by Equation (1).

$${\mathrm{V}}_{\mathrm{B}1}^{\prime }={\mathrm{V}}_{\mathrm{B}1}-{\displaystyle \frac{{\mathrm{C}}_{\mathrm{S}}+{\mathrm{C}}_{\mathrm{F}}+{\mathrm{C}}_{\mathrm{AZ}1}}{{\mathrm{C}}_{\mathrm{F}}·{\mathrm{C}}_{\mathrm{AZ}1}}}({\mathrm{C}}_{\mathrm{R}}·\mathrm{AVDD})$$

(1)

Thus, the additional ${\mathrm{C}}_{\mathrm{R}}$ of 1.2 fF expands the output signal range by approximately 400 mV in this design.

3.1.2. Non-Inverting Attenuator

The non-inverting attenuator for the LCG signal consists of ${\mathrm{C}}_{\mathrm{SH}}$ and ${\mathrm{C}}_{\mathrm{ATN}}$ (Figure 2). ${\mathrm{C}}_{\mathrm{SH}}$ and ${\mathrm{C}}_{\mathrm{ATN}}$ are 1 pF and 350 fF, respectively, considering the kTC noise and device mismatch. Figure 3b shows that ${\mathrm{C}}_{\mathrm{SH}}$ operates in the inversion region for the LCG signal even for the maximum photoelectron charge, where the bottom plate of the PMOS capacitor ${\mathrm{C}}_{\mathrm{SH}}$ is biased to ${\mathrm{V}}_{\mathrm{SL}}^{\prime }$ (1.15 V), and the top plate is biased to ${\mathrm{V}}_{\mathrm{B}2}$ (0.2 V). When the attenuator reset signal $\mathrm{\Phi }\mathrm{CL}$ is “High”, the bottom and top plates of ${\mathrm{C}}_{\mathrm{ATN}}$ are also biased to DVDD (1.8 V) and ${\mathrm{V}}_{\mathrm{B}2}$, respectively. This biasing guarantees operation in the inversion region. The voltage difference in ${\mathrm{C}}_{\mathrm{ATN}}$ decreases for the subsequent reset voltage ${\mathrm{V}}_{\mathrm{RL}}^{\prime }$ (3.3 V), where the feedthrough from AVDD is negligible at approximately 0 mV due to the large capacitance of ${\mathrm{C}}_{\mathrm{S}}$, but it stays in the inversion region because the DVDD is high enough.

3.1.3. Digital/Analog Converter (DAC)

The DAC in the SAR-ADC is composed of PMOS capacitors for the MSB array ${\mathrm{C}}_{\mathrm{MSB}}$ and the split capacitor ${\mathrm{C}}_{\mathrm{split}}$ and NMOS capacitors for the LSB array ${\mathrm{C}}_{\mathrm{LSB}}$, as shown in Figure 2. The unit capacitance of the DAC is 15 fF, considering the kTC noise and device mismatch. Figure 3a shows that the DC operating point of ${\mathrm{C}}_{\mathrm{LSB}}$ is folded into that of ${\mathrm{C}}_{\mathrm{MSB}}$ and ${\mathrm{C}}_{\mathrm{split}}$. This configuration ensures all MOS capacitors operate in the inversion region for a linear response. During the comparator’s autozeroing, $\mathrm{\Phi }\mathrm{AZ}3$ is “High”, and the top and bottom plates of the PMOS capacitor ${\mathrm{C}}_{\mathrm{MSB}}$ are biased to ${\mathrm{V}}_{\mathrm{B}2}$ (0.2 V) and ${\mathrm{V}}_{\mathrm{REF}\_\mathrm{PL}}$ (2.47 V), respectively. ${\mathrm{C}}_{\mathrm{MSB}}$ is maintained in the inversion region throughout the subsequent successive approximation process, even for the maximum input signal when ${\mathrm{V}}_{\mathrm{ADC}}$ and ${\mathrm{V}}_{\mathrm{MSB}}$ approach 1.0 V. Similarly, during autozeroing, the PMOS capacitor ${\mathrm{C}}_{\mathrm{split}}$ is biased between ${\mathrm{V}}_{\mathrm{B}2}$ (0.2 V) and ${\mathrm{V}}_{\mathrm{B}3}$ (2.47 V), and the NMOS capacitor ${\mathrm{C}}_{\mathrm{LSB}}$ is biased between ${\mathrm{V}}_{\mathrm{B}3}$ (2.47 V) and ${\mathrm{V}}_{\mathrm{REF}\_\mathrm{NL}}$ (0.2 V). Both ${\mathrm{C}}_{\mathrm{split}}$ and ${\mathrm{C}}_{\mathrm{LSB}}$ are maintained in the inversion region during the successive approximation process, even for the maximum input signal when ${\mathrm{V}}_{\mathrm{ADC}}$ and ${\mathrm{V}}_{\mathrm{MSB}}$ approach 1.0 V.

3.1.4. Simulated Linearity Characteristics Using MOS Capacitors

The proposed readout circuit was designed with a 0.18 µm CMOS process. The corner conditions used in the PVT simulations are based on the operating conditions commonly assumed for consumer-grade devices. According to the SPICE simulations results under PVT variations, transistor process variations (Slow, Typical, Fast), supply voltages (3.0, 3.3, 3.6 V), and operating temperatures (0, 25, 60 °C), the integral nonlinearity (INL) was, respectively, +4.35/−4.28 LSB in a typical condition, +5.21/−6.08 LSB in a slow condition, and +4.69/−7.48 LSB in a fast condition for 10-bit resolution. The results confirm that the INL remains below 1% relative to the ideal output, demonstrating favorable linearity despite the use of MOS capacitors.

3.2. In-Column HDR Merger

Figure 5 shows the operational timing of the SAR-ADC, in which the appropriate signal is selected from HCG and LCG signals for HDR signal merging. Since the HCG signal decreases when oversaturation occurs, signal selection is performed by comparing the LCG signal against a predefined threshold voltage. The LCG threshold is determined by the HCG FWC, as well as by the ratio between the conversion gains of the HCG and LCG signal paths from the pixel to the readout circuit [31]. This comparison is enabled by inputting a decision bit into the DAC. The selection result, which is a flag signal, is stored in a 1-bit SRAM (see Figure 2). If the LCG signal is lower than the threshold voltage, the HCG signal is selected; otherwise, the LCG signal is selected. If the initially converted HCG signal is selected, the signal selector halts the A/D conversion of the LCG signal to decrease the average power consumption. The average power consumption is evaluated using SPICE simulations. The supply current of each circuit block (e.g., op-amp and comparators) is individually monitored, and the average power is obtained by time integration over one operation cycle. The average power consumption for different signal selection ratios is summarized in

Table 1. Average power consumption of a single readout column.

Signal Selection Ratio (HCG:LCG)	DS (µW)	SAR-ADC (µW)	Total (µW)
w/o Signal Selector	10.77	98.36	109.13
6:4		78.83	89.59 (−17.90%)
5:5		82.08	92.85 (−14.92%)
4:6		85.34	96.10 (−11.94%)

. According to the SPICE simulation results, compared with the reference case without the signal selector, the proposed technique reduces the total power consumptions by 17.90%, 14.92%, and 11.94% for HCG:LCG signal ratios of 6:4, 5:5, and 4:6, respectively. Since the signal selection is executed on a column-by-column basis, this topology can be easily adapted to large-scale column parallel readout circuit. However, the signal selection process adds 2 µs to the readout cycle of 30 µs, which indicates that the readout time increase by 6.7%. Assuming a CIS with 640 × 480 pixels, the frame rate decreases from 69.4 to 65.1 fps. Interference noise is also caused by sparse LCG A/D conversion in the column-parallel ADCs.

To mitigate the impact of column interference noise, a bias sampling circuit [32] is utilized at the comparator’s current source (see Figure 2). Figure 6 highlights only the ground side from the comparator’s ${\mathrm{M}}_1$ transistor and the timing diagram. First, at time ${\mathrm{t}}_1$, the control pulse $\mathrm{\Phi }\mathrm{tail}\_\mathrm{SW}$ of ${\mathrm{M}}_1$ is “Low” before the comparator operates. This “Low” state means the comparator current is stopped. Therefore, the ground bounce generated by the wiring resistance is zero. Concurrently, the control pulse $\mathrm{\Phi }\mathrm{BIAS}\_\mathrm{hold}$ for ${\mathrm{M}}_2$ is “High,” which stores the bias voltage, ${\mathrm{V}}_{\mathrm{BIAS}}$, in the ${\mathrm{C}}_{\mathrm{BIAS}}$ capacitor. Next, at time ${\mathrm{t}}_2$, $\mathrm{\Phi }\mathrm{tail}\_\mathrm{SW}$ is “High”, and $\mathrm{\Phi }\mathrm{BIAS}\_\mathrm{hold}$ is “Low,” which activates the comparator. As a result, the ${\mathrm{C}}_{\mathrm{BIAS}}$ capacitor maintains a constant gate-to-source voltage for ${\mathrm{M}}_{\mathrm{BIAS}}$, even under column interference noise caused by ground bounce variations, due to sparse LCG A/D conversion across columns.

4. Fabrication and Evaluation of a Test Chip

Figure 7 shows an overview of the test chip used to evaluate the concept of the proposed readout circuit. The HCG and LCG reset voltage (${\mathrm{V}}_{\mathrm{R}}$), HCG signal voltage (${\mathrm{V}}_{\mathrm{SH}}$), and LCG signal voltage (${\mathrm{V}}_{\mathrm{SL}}$) are supplied externally as pseudo-pixel signals. Similarly, the DAC reference voltages (${\mathrm{V}}_{\mathrm{REF}\_\mathrm{PH}}$, ${\mathrm{V}}_{\mathrm{REF}\_\mathrm{PL}}$, ${\mathrm{V}}_{\mathrm{REF}\_\mathrm{NH}}$, ${\mathrm{V}}_{\mathrm{REF}\_\mathrm{NL}}$, and ${\mathrm{V}}_{\mathrm{B}3}$) are also provided externally. In contrast, the bias voltages (${\mathrm{V}}_{\mathrm{B}1}$ and ${\mathrm{V}}_{\mathrm{B}2}$) are generated on-chip. Furthermore, 86 columns of readout circuits are implemented, and their output signals are read sequentially using a horizontal scanner (H-SCAN).

Figure 8 shows a photograph of the fabricated test chip, which was fabricated with a 0.18 µm CMOS process with MOS capacitors. The chip includes the DS circuit, a 10-bit SAR-ADC, BIAS circuits, and an H-SCAN. It should be noted that the LOFIC pixel is not implemented on this test chip. To represent the layout constraints inherent in the CIS, 86 columns of DS circuits and ADCs are laid out in parallel with a column pitch of 11.22 µm. For a consistent comparison with an MIM capacitor-based circuit, which is constrained to a 11.22 µm column pitch, the proposed MOS capacitor-based circuit was also laid out with the same pitch. The total layout height of a single column circuit is 1071 µm, where 173 and 898 µm are allocated to the DS circuit and SAR-ADC, respectively. Compared with a design with MIM capacitors and 20-bit SRAM without a signal selector, the area of the proposed readout circuit is reduced by 36.5%. It is noted that the design rules for this process prohibit placing transistors under MIM capacitors. The detailed area breakdown and comparison results are summarized in

Table 2. Height comparison between MIM and MOS capacitor-based readout circuits (with a fixed column pitch of 11.22 µm).

	MIM Capacitor- Based Circuit	MOS Capacitor- Based Circuit	Reduction (%)
DS (µm)	533.72	172.95	67.6
SAR-ADC (µm)	1152.37	897.72	22.1
Total (µm)	1686.09	1070.67	36.5

.

Figure 9 shows the measurement setup for the test chip. The fabricated test chip and an FPGA are mounted on a PCB board. The power supply voltages, DAC reference voltages, and the pseudo-pixel reset voltage, ${\mathrm{V}}_{\mathrm{R}}$, are supplied from external DC power sources. Pseudo-pixel signal voltages ${\mathrm{V}}_{\mathrm{SH}}$ and ${\mathrm{V}}_{\mathrm{SL}}$ are supplied by a function generator. Control signals for the test chip are provided by the FPGA. The digital output of the test chip is transferred to the FPGA and then to a PC via USB.

Figure 10 shows the measurement results of the test chip. Figure 10a shows the input–output characteristics, and Figure 10b shows the INL. In Figure 10a, the X-axis represents the difference between the pseudo-pixel reset level and the signal level. This value is converted into the number of electrons, assuming conversion gains of 160 µV/e⁻ for HCG and 10 µV/e⁻ for LCG, based on our prior work [30]. The blue solid line on the left Y-axis represents the RAW signal, while the red dashed line on the right Y-axis represents the merged HDR signal. The RAW signal is the output prior to flag signal processing, while the merged HDR signal is linearized using the flag information. The signal synthesis is performed by scaling the LCG signal by the circuit gain and conversion gain. In the zoomed-in view, the output signal transitions from the HCG signal to the LCG signal when the number of electrons reaches 900 e⁻. In Figure 10b, the X-axis similarly represents the number of electrons, and the Y-axis shows the INL. The measured INL was +7.17/−6.93 LSB for the HCG signal and +7.95/−7.41 LSB for the LCG signal. Despite the utilization of MOS capacitors, an INL of less than $1.0\%$ was achieved. The readout circuit exhibits a noise floor of approximately 3.5 ${\mathrm{e}}_{\mathrm{rms}}^{-}$. Regarding the maximum signal charge, the pixel FWC is 120,000 ${\mathrm{e}}^{-}$ [30], whereas the maximum number of signal electrons of the readout circuit is 118,670 ${\mathrm{e}}^{-}$. Since the effective maximum signal is limited to 118,670 ${\mathrm{e}}^{-}$, the dynamic range is estimated at 90.7 dB.

Figure 11 shows the measured image for the ramp input signal to ${\mathrm{V}}_{\mathrm{SH}}$ and ${\mathrm{V}}_{\mathrm{SL}}$. Figure 11a shows the pre-synthesis image, where the X-axis corresponds to the column number, and the Y-axis corresponds to the output code. The red dashed line indicates the transition point of the flag signal from the HCG signal to the LCG signal. A zoomed-in view of this transition, shown on the right, demonstrates that the in-column HDR merger is operating correctly.

Figure 12 shows the measured column fixed pattern noise (FPN) of the readout circuit for evaluating the column interference noise. The test chip provides two operating modes to evaluate the column FPN. The first is the “static-current” mode, where the comparator current flows continuously. The second is the “current-saving” mode, where the signal selector halts the comparator current during the A/D conversion of the LCG signal. We assumed that the column FPN at the HCG-to-LCG transition point represents the column interference noise in the “current-saving” mode because the HCG-selected columns stop their comparator current. This transition point varies between columns due to the inter-column offset variations. Even though the change in conversion gain increases the column FPN at the transition point, the difference in the column FPN between the “static-current” and “current-saving” modes remains negligibly small. This result confirms that the bias sampling circuit keeps the impact of the interference noise negligibly small.

Figure 13 shows the measured images in the static-current mode. Figure 13a,b show the pre-synthesis image and the post-synthesis images, respectively, where the signal level crosses the flag transition point. Although the column FPN in the pre-synthesis image is significant when LCG-selected columns are mixed with HCG-selected columns, the column FPN in the post-synthesis image is significantly reduced. Figure 14a,b show the pre-synthesis image and the post-synthesis image in the current-saving mode, respectively. Similarly, the column FPN observed in the pre-synthesis image is significantly reduced in the post-synthesis image. When comparing Figure 13b and Figure 14b, no degradation of the column FPN is visible. This visual result demonstrates that the bias sampling circuit effectively prevents FPN degradation from the sparse A/D conversion.

Table 3. Specifications and performance of the proposed readout circuit for the LOFIC CIS with an on-chip HDR merger.

Parameter	Value
Process	0.18 µm 1P5M CMOS process
Supply voltage	3.3 V
ADC resolution	10-bit
Readout circuit area	11.22 µm × 1071 µm (−36.5%)
Simulated total power consumption	92.85 µW (−14.92%)
INL	+7.17/−6.93 LSB (HCG)
	+7.95/−7.41 LSB (LCG)

summarizes the specifications and performance of the proposed readout circuit for the LOFIC CIS with an on-chip HDR merger.

5. Discussion

Although the analog readout circuit for the LOFIC pixel has been rarely addressed in published literature, we have provided a specification and performance comparison, as shown in

Table 4. Comparison with other readout circuits applicable to LOFIC CIS. Reprinted with permission from [29], ©2025 IEEE.

	[33]	[34]	This Work
Process	90 nm 1P5M	180 nm 1P3M	180 nm 1P5M
#Readout circuit	1	2	1
LCG autozeroing	No	Possible	Possible
ADC resolution [bit]	12	N/A	10
Power consumption [µW]	N/A	N/A	92.85 (simulation)
Period [µs]	N/A	N/A	32
DR [dB]	83	101	90.7 (estimation)

. Sakakibara et al. proposed an SE-HDR global-shutter CIS with in-pixel dual storage, in which the dual storage signals are read out through a single ADC channel [33]. Even though the pixel itself is not an LOFIC pixel, the readout circuit is applicable to an LOFIC CIS. However, the comparator reset noise is not canceled for the LCG signal, resulting in an SNR drop at the switching point from the HCG to the LCG signal. Nasuno et al. proposed an LOFIC CIS [34], in which the HCG and LCG signals are read out through two separate readout channels. Because each channel employs two sample-and-hold capacitors for the reset and signal levels, as well as circuitry for CDS and ADC processing, the overall readout circuit can become large.

6. Conclusions

We propose a small-area low-power column-parallel readout circuit for the LOFIC CIS. The proposed circuit employs area-efficient MOS capacitors with a DC operating point folding technique. It also implements an in-column signal selector for the HDR signal, merged from the HCG and LCG signals. The signal selector allows the SRAM to store only the selected signal and reduces the circuit area. The signal selector also reduces the average power consumption by halting the LCG A/D conversion of the HCG-selected columns. The bias sampling technique is introduced to mitigate the interference noise caused by sparse LCG A/D conversion. We fabricated a test chip with a 0.18 µm CMOS process to evaluate the proposed circuit. The measurement results demonstrate that the INL of +7.17/−6.93 LSB for the HCG signal and +7.95/−7.41 LSB for the LCG signal are achieved, even with the use of MOS capacitors. Regarding the circuit area, the design achieves a significant total area reduction of $36.5\%$ with the proposed techniques. Regarding power consumption, the average SAR-ADC power is reduced by 16.55% to 82.08 µW. Even considering the inverting amplifier power (10.77 µW), the total power reduction is 14.92%. Furthermore, the estimated dynamic range is 90.7 dB. We also demonstrated that the column interference noise remains negligibly small. In future work, the impact of global bias distribution and inter-column noise will be evaluated using a large-scale prototype with LOFIC pixels, and the impact of the measured INL of the test chip on the overall imaging system will also be investigated.