Search Results (206)

This paper presents a fully integrated three-stage stacked power amplifier (PA) operating in the K-/Ka-band, fabricated using a TSMC 65 nm CMOS process for fifth-generation (5G) millimeter-wave applications. To improve the output power without sacrificing reliability, a two-stacked-FET configuration is adopted in the power stage, which distributes the voltage stress across series-connected transistors and permits a higher supply voltage than a conventional cascode structure. A differential topology with capacitive neutralization is employed in both the common-source driver stage and the stacked power stage. The neutralization capacitance is determined from a stability- and gain-oriented analysis based on the Rollett stability factor (K) and the maximum available gain (MAG), which clarifies the trade-off between feedback cancelation and wideband gain flatness over the operating band. The fabricated PA occupies a total chip area of 0.51 mm², including pads, with a core area of 0.18 mm². The measurement results demonstrate a measured 3 dB bandwidth of 6.7 GHz from 24.6 GHz to 31.3 GHz, a peak small-signal gain of 32.9 dB, a saturated output power of 20.8 dBm, an output 1 dB compression point of 16 dBm, and a peak power-added efficiency of 20.4% at 28.5 GHz. Over the 26–30 GHz range in which the large-signal characterization was performed, the saturated output power varies by less than 1 dB and the efficiency by less than 2 percentage points, indicating that the combination of capacitive neutralization and stacked-FET operation provides a compact solution for wideband K-/Ka-band CMOS power amplification. Full article

Rapid, point-of-care detection of Escherichia coli O157:H7 remains an unmet clinical need, as culture and molecular methods are slow and poorly suited to decentralized or emergency settings. A label-free, monolithic aptasensor biochip was fabricated in a standard 65 nm CMOS process, featuring three aptamer-functionalized gold sensing pads with matched reference pads for differential readout. A 37-mer DNA aptamer targeting the E. coli O157:H7 lipopolysaccharide was immobilized via thiol–gold self-assembled monolayer chemistry. Binding events were transduced into surface-potential shifts, amplified by an on-chip analog front-end (~100 V/V gain, 101.5 µW), and evaluated using calibration standards, patient specimens, and hospital environmental samples, with fluorescence microscopy for validation. The sensor achieved 47.42 mV/decade sensitivity across 1–10,000 CFU/mL, an IUPAC detection limit near 3.74 CFU/mL, and an empirical LOD of about 11 CFU/mL, with outputs tracking bacterial load and ~5.7% matrix-related deviation. Hospital samples were detectable to 28 CFU/mL. Because the patient-derived and hospital-acquired cohorts (n = 10 and n = 6, respectively) were assembled for pilot analytical and matrix-tolerance characterization rather than for diagnostic-accuracy determination, these results establish detectability and matrix robustness in real clinical and environmental specimens rather than clinical diagnostic sensitivity or specificity, which will require a larger, prospectively enrolled cohort in future work. Sensor kinetics followed Langmuir-type adsorption, saturating within 16–25 min for target pathogens versus slower responses for non-target strains. Selectivity tests against six bacterial species showed discrimination, with cross-reactivity decreasing from related E. coli pathotypes to Enterobacteriaceae to Gram-positive species. Inter-pad variability stayed below 1.5 mV, supporting this compact, low-power platform for scalable, enrichment-free point-of-care pathogen detection. Full article

This paper presents an electronically tunable first-order universal filter capable of operating in multiple analog modes, realized through a compact architecture built around multiple-input operational transconductance amplifiers (MI-OTAs). By leveraging the MI-OTA’s ability to accommodate several input signals within a single transconductance stage—allowing direct arithmetic operations such as summation and subtraction—the proposed design minimizes the number of active elements traditionally required for mixed-mode filtering. Consequently, both inverting and non-inverting forms of low-pass, high-pass, and all-pass responses can be generated in voltage mode, current mode, transadmittance mode, and transimpedance mode, enabling a total of 24 distinct first-order transfer functions using one unified circuit topology. The pole for all responses can be conveniently adjusted by electronically tuning the OTA transconductance. The multiple-input capability is realized using a multi-input MOS technique, while subthreshold-biased bulk-driven transistors allow the circuit to function from a 0.5 V supply with an extended input voltage range and ensure ultra-low power dissipation. The filter was designed and evaluated in Cadence Virtuoso using a 65 nm TSMC CMOS process. Under a 7 nA bias current, the low-pass configuration achieves a consumption of 87.5 nW and a dynamic range of 44.7 dB. Additionally, experimental verification was performed using the commercial LM13700 OTA, confirming the correct operation and practicality of the proposed approach. Full article

Electromagnetic interference (EMI) has become a serious challenge for signal integrity (SI) in modern high-speed digital systems. With the technology scaling down into nanometric CMOS technologies and lowering supply voltage, EMI induced signal integrity effects are becoming more significant compared to voltage margins. This work presents experimental results of controlled RF interference affecting the eye diagrams of the CMOS inverter. The test circuits were fabricated in 65 nm, 130 nm, and 180 nm CMOS technologies. A dedicated measurement methodology has been developed to inject RF to the supply node and to capture both time domain and eye diagram signals to visualize EMI effects. Unlike previous works that analyzed effects of channel-induced impairments or presented simulation results on EMI effects, we present an experimental evaluation of the impact of EMI on circuit functionality. Experimental results reveal that EMI predominantly modulates the logic-high amplitude, leading to progressive eye closure. The eye height decreases monotonically with increasing RF injection power across all investigated technology nodes, whereas the logic-low level remains comparatively stable. This behavior indicates that the dominant degradation mechanism is consistent across technologies and is primarily governed by the conduction state of the CMOS inverter. To illustrate the degradation caused by EMI, a compact, analytical expression for the reduction of the eye height is derived. The reduction is given as a function of the RF interference amplitude and expressed through a technology-dependent scaling parameter. Good agreement is observed between the analytical model predictions and experimental measurements for varying interference amplitudes and different technology generations, with an average absolute prediction error below 2%. Results are presented to demonstrate eye height as a sensitive and reliable metric of EMI susceptibility. Additionally, a practical framework for rapid estimation of signal degradation is presented for high-speed digital systems operating in complex electromagnetic environments. Full article

This paper presents an 11-bit linear-tracking digital low-dropout (DLDO) regulator with variable step size control and transient enhancement (TE) techniques to achieve low output voltage overshoot/undershoot and high current efficiency. To address overflow issues and enable multi-step cooperative regulation, a novel feed/borrow bidirectional shift register (SR) array is proposed. Based on a standard 65 nm CMOS process, the effective core layout area is 2960 μm², and post-layout simulation results show that the proposed DLDO consumes a quiescent current of 21 μA and provides a maximum load current of 15 mA, with a peak current efficiency of 99.87%. At a 1 V input and 0.9 V output, the maximum voltage overshoot/undershoot is only 40 mV under full load step change, corresponding to an overshoot/undershoot ratio of 4.4%. The DLDO is achieved with high resolution, fast transient response, low voltage ripple, and the competitive figures of merit (FOMs), which is suitable for low-power and high-precision power management applications. Full article

In this article, we present a 60 GHz low-phase-error current-reuse variable-gain amplifier (VGA) in 65 nm CMOS. The proposed VGA consists of an input stage, a variable gain stage, and an output stage. An impedance-invariant VGA is used to reduce phase error during gain control. Furthermore, a transformer-based current-reuse technique is adopted to reduce dc power consumption and enhance the gain. Implemented in 65 nm CMOS technology, the proposed VGA occupies a chip area of 0.38 mm², including pads, and consumes a dc power of 15 mW. The implemented design achieves a gain of 13.2 dB, a gain control range of 20 dB, and an RMS phase error less than 2.65° over 50–67 GHz. Additionally, the input 1-dB compression point is −11 dBm at 60 GHz. Full article

A low-latency, low-complexity digital demodulator is presented for chirp spread spectrum (CSS)-modulated RF packets targeting low-power IoT wireless systems operating in spectrally congested environments. Conventional CSS receivers rely on fast-fourier transform (FFT)-based synchronization and long preamble sequences, resulting in increased latency and computational complexity. To address these limitations, the proposed receiver employs amplitude-domain synchronization using oversampled sub-chirp windows and maximum likelihood estimation without requiring FFT processing. A digital demodulator co-designed with receiver’s fractional-N phase-locked loop (PLL) architecture enables rapid sub-chirp generation and fast frequency settling, while compensation techniques mitigate symbol boundary offset (SBO) error due to PLL non-idealities during synchronization. The proposed system achieves packet synchronization within 17.5 preamble symbol cycles while maintaining symbol boundary offset estimation error below ±1%. Simulation results demonstrate a syncword misdetection probability below 10⁻³ at SNRs of 9 dB and 1 dB without and with 8× repetition, respectively. In the presence of interferences, the receiver tolerates worst-case in-band signal-to-noise ratio (SIR) levels down to −16.2 dB while consuming 877 µW and 830 µW average power at the digital demodulator, and fractional-N PLL, respectively. Implemented in 65 nm CMOS, the proposed architecture occupies 0.195 mm² active area. Full article

This paper presents a 7-bit 1.6 GS/s hybrid capacitive-to-charge-injection DAC (C-CIDAC)-based flash-assisted time-interleaved (FATI) successive-approximation-register (SAR) analog-to-digital converter (ADC) that improves the limited input range and temperature-induced gain variation in conventional CIDAC-based SAR ADCs. In the proposed architecture, a DAC voltage common-mode (V_CM) shift up to 48 LSBs is internally generated during the coarse conversion, enabling a rail-to-rail ADC input range while improving V_CM independence. In addition, a fully on-chip background gain-calibration scheme is introduced to compensate for the gain error between the CDAC and CIDAC caused by temperature variation. By taking advantage of the pulse-activation-based CIDAC operation scheme, the proposed calibration achieves robust gain tracking without any external bias control. The proposed four-channel FATI-SAR ADC was designed using a 65 nm CMOS process and occupies 13,628 μm², including the background calibration circuitry. The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.60/−0.60 LSB and +0.72/−0.76 LSB at −40 °C and 105 °C, respectively. At Nyquist input, the simulated SNDR and SFDR are 41.52 dB and 53.36 dB, respectively. The ADC consumes 8.551 mW and achieves an FoM_W of 54.6 fJ/conversion step. Comprehensive post-layout simulation results show that the proposed FATI-SAR ADC operates at 1.6 GS/s and maintains an ENOB above 6.3 across a temperature range from −40 °C to 105 °C at Nyquist input. Full article

A low-cost, high-robust, high-gain preamplifier is fabricated in a 65 nm CMOS for Hall sensors. A semi-open loop that combines an optimized differential–difference amplifier with a simplified open-loop amplifier is proposed to achieve stringent transconductance matching, with the same DC and AC conditions. A two-stage reconfigurable structure, together with an embedded offset-accumulation elimination scheme, relieves open-loop stress and achieves both high fidelity and accurate gain. The experimental results show that the preamplifier has a variable gain of 34.6–46.6 dB and a gain error no more than 0.12% under process/voltage/temperature variations and without error calibration, at the cost of an active area of 0.076 mm² and a current dissipation of 0.7 mA under a 2.5–3.3 V supply. Specifically, both the loop topology and the transconductance match are different from the existing works. Full article

This paper presents a nanowatt-scale operational transconductance amplifier (OTA) and an electronically tunable third-order low-pass filter (LPF) designed for energy-constrained biomedical signal conditioning. The circuits are implemented in a 65 nm CMOS process and verified through comprehensive schematic-level simulations. Biased in the deep subthreshold region at 1 nA, the OTA achieves a 50 dB low-frequency gain, a 225 Hz unity-gain bandwidth at 10 pF load capacitance and an input-referred noise floor of 1.55 μV/√Hz, with a total power consumption of only 1.75 nW. The integrated third-order LPF provides a wide tuning range (37–668 Hz) via bias current modulation, exhibiting excellent linearity with a THD of 0.059% and a 65.3 dB dynamic range. Monte Carlo and PVT corner analyses demonstrate the design’s theoretical robustness against process variations and environmental fluctuations. ECG signal simulations validate the circuit’s effectiveness in suppressing high-frequency artifacts while preserving morphological integrity, providing a proof-of-concept for ultra-low-power wearable healthcare architectures. Full article

This paper presents a K-band four-channel phased array beamformer with temperature compensation in 65 nm CMOS for 5G and satellite communications. The beamformer includes a four-way power divider/combiner, four RF channels, and digital control circuits. Each RF channel comprises a receive chain, a transmit chain, and a pair of receive/transmit (TX/RX) single-pole double-throw (SPDT) switches. The receive chain consists of a low-noise amplifier (LNA), a six-bit reflective-type phase shifter (RTPS), a drive amplifier (DA), two temperature-compensation attenuators (TCAs), and a six-bit attenuator (ATT); the transmit chain integrates a power amplifier (PA), two TCAs, a six-bit RTPS, a DA, and a six-bit ATT. Measurements show the chip exhibits 0–4.5 dB gain, noise figure (NF) < 7.8 dB, root mean square (RMS) phase error < 3.5°, and RMS gain error < 0.4 dB in receive mode operating in 19–23 GHz. In transmit mode operating in 21–23 GHz, it provides 6–10 dB gain range, RMS phase error < 3.4°, RMS gain error < 0.25 dB, and output power at 1 dB compression point (OP1dB) > 6.5 dBm. In addition, the receive and transmit gain variations are within 0.8 dB and 0.4 dB, respectively, when temperature ranges from −55 °C to 85 °C. With a compact footprint of 3.5 × 4.8 mm², the beamformer consumes 110 mW (receive) and 190 mW (transmit) DC power per channel. Full article

In this paper, a 12-bit, 10 MS/s two-step sub-ranging successive approximation register (SAR) analog-to-digital converter (ADC) is proposed. The proposed architecture enables residue amplification within a single-stage SAR ADC by dividing the top-plate sampling node, thereby avoiding the requirement for a multi-stage design. This structure also eliminates gain and offset mismatches between the coarse and fine conversions, enhancing robustness and linearity. Owing to the two-step operation, the total capacitance of the capacitive digital-to-analog converter (CDAC) is reduced by 86% compared to that of a conventional SAR ADC with the same unit-capacitor size. In addition, the residue amplifier drives only one-fourth of the total CDAC capacitance, significantly relaxing its power consumption. A prototype fabricated in a 65 nm CMOS process occupies an area of 252 $\mathsf{\mu }$m × 227 $\mathsf{\mu }$m and demonstrates a signal-to-noise and distortion ratio (SNDR) of 65.7 dB at Nyquist-rate input. The total power consumption is 227.7 $\mathsf{\mu }$W under a 1.2 V supply, resulting in a Walden figure of merit (FoM) of 14.5 fJ/conversion step. These results confirm competitive performance and energy efficiency, even with the use of an analog residue amplifier. Full article

This work describes the development of the Multi-channel Integrated Zone-sampling Analogue-memory based Readout (MIZAR) ASIC. This 64-channel chip was designed as part of NASA’s POEMMA Balloon with RADIO (PBR) mission, which aims to detect Ultra-High-Energy Cosmic Rays (UHECRs) and $\tau$ showers produced by the interaction of Cosmic Neutrinos (CNs) in the crust. The ASIC was implemented to read out a tile of 8 × 8 Silicon Photomultipliers (SiPMs) used to acquire the optical Cherenkov signals generated by Extensive Air Showers (EASs). A channel is partitioned into 256 cells where each one integrates an analogue memory, a Wilkinson Analog-to-Digital Converter (ADC) and a digital memory operating at the nominal sampling rate of 200 MS/s (with a 5 ns integration time). The signal is digitized on-chip, then the converted data is read out by an FPGA. The MIZAR also provides a 64-bit hitmap as a first-level trigger which can be elaborated by an external firmware. This ASIC can also be configured to further segment the channels into units of 32 or 64 cells each and the ADC resolution can be set to a range between 8 and 12 bits. The chip was designed in a commercial 65 nm CMOS technology node and it was submitted for production in December 2024. The ASICs were delivered in March 2025. Full article

In this paper we present a low-noise, high-frame-rate global shutter CMOS image sensor with UHD resolution (3840 × 2160), targeting high-speed machine vision applications. The sensor (ForzaFAST581) supports video capture at up to 1141 FPS at 12 bits and 1694 FPS at 8 bits at full resolution, consuming a total power of 5.5 W. Fabricated in a 65 nm, four-metal BSI process, the imager features a 5 µm voltage-domain global shutter pixel with dual-gain capability for improved dynamic range and a read noise of 3.04 e⁻ in global shutter and 2.15 e⁻ in rolling shutter mode for high-gain at maximum frame rate operation. For compact camera integration and low power consumption, the sensor is designed to stream video through 16 CML data ports, each operating at 7.44 Gbps, achieving a total aggregate throughput of 119 Gbps. Additionally, the sensor supports selectable output bit depths—8-bit, 10-bit, and 12-bit—allowing frame rate optimization based on application-specific requirements. Full article

While circuit parameter optimization has matured significantly, the systematic discovery of novel circuit topologies remains a bottleneck in analog design automation. This work presents SymXplorer, an open-source Python framework designed for automated topology exploration through symbolic modeling of analog components. The framework enables a component-agnostic approach to architecture-level synthesis, integrating stability analysis and higher-order filter exploration within a streamlined API. By modeling non-idealities as lumped parameters, the framework accounts for physical constraints directly within the symbolic analysis. To facilitate circuit sizing, SymXplorer incorporates a multi-objective optimization toolbox featuring Bayesian optimization and evolutionary algorithms for simulation-in-the-loop evaluation. Using this framework, we conduct a systematic search for differential Common-Gate (CG) Bandpass Transimpedance Amplifier (TIA) topologies tailored for 5G New Radio (NR) Radio-over-Fiber applications. We propose a novel, orthogonally tunable Bandpass TIA architecture identified by the tool. Implementation in 65 nm CMOS technology demonstrates the efficacy of the framework. Post-layout results exhibit a tunable gain of 30–50 dBΩ, a center frequency of 3.5 GHz, and a tuning range of 500 MHz. The design maintains a power consumption of less than 400 μW and an input-referred noise density of less than 50 pA/$\sqrt{\mathrm{Hz}}$ across the passband. Finally, we discuss how this symbolic framework can be integrated into future agentic EDA workflows to further automate the analog design cycle. SymXplorer is open-sourced to encourage innovation in symbolic-driven analog design automation. Full article