Search Results (88)

We propose a high-speed all-optical logic gate design based on silicon racetrack and ring resonators patterned on a silica substrate. The architecture features racetrack resonators at both the input and output, with a central ring resonator enabling the required phase-sensitive interference for logic processing. Logic operations are achieved through the interplay of constructive and destructive interference induced by phase-shifted input beams. Using the finite-difference time-domain (FDTD) method in Lumerical software, we simulate and demonstrate seven fundamental Boolean logic functions, namely XOR, AND, OR, NOT, NOR, NAND, and XNOR, at an operating wavelength of 1.33 µm. The system supports a data rate of 47.94 Gb/s, suitable for ultrafast optical computing. The performance is quantitatively evaluated using the contrast ratio (CR) as the reference metric, with more than acceptable values of 13.09 dB (XOR), 13.84 dB (AND), 13.14 dB (OR), 13.80 dB (NOT), 14.53 dB (NOR), 13.80 dB (NAND), and 14.67 dB (XNOR), confirming strong logic level discrimination. Comparative analysis with existing optical gate designs underscores the advantages of our compact silicon-on-silica structure in terms of speed, CR performance, and integration potential. This study validates the effectiveness of racetrack–ring configurations for next-generation all-optical logic circuits. Full article

Three-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase operation. Therefore, the gate-induced drain leakage (GIDL) erase method, which utilizes band-to-band tunneling (BTBT) to raise the channel potential, is employed. However, compared to bulk erase, the BTBT-based erase method requires a longer time to generate holes in the channel, leading to erase speed degradation. To address this issue, we propose a structure which enhances the erase speed by surrounding the bitline (BL) PAD with SiGe. In the case of a SiGe thickness (t_SiGe) of 13 nm, the lower bandgap of SiGe increases the BTBT generation rate, boosting the channel potential rise at the end of the erase voltage ramp-up by 861% compared to the Si-only structure, while limiting the reduction in read on-current to within 4%. We modeled the voltage and electric field across the SiGe layer, as well as BTBT generation rate and GIDL current in the SiGe layer, by varying t_SiGe, Ge composition ratio (SiGe_X), and the voltage difference between V_BL and V_{GIDL_TR}. Full article

The continuous demand for faster processing systems, driven by the rise of artificial intelligence, has exposed limitations in traditional transistor-based electronics, including quantum tunneling, heat dissipation, and switching delays due to challenges in further miniaturization. This study explores optical systems as a promising alternative, leveraging the speed of photons over electrons. Specifically, we design and simulate optical NAND and NOR logic gates using a two-dimensional photonic crystal structure with a square lattice. Symmetrical waveguides are used for the input paths to make the structure relatively more straightforward to fabricate. A key innovation is the ability to realize both gates within a single structure by adjusting the phases of the input sources. To optimize the phase parameters efficiently, we employ the ML-FOLD (Meta-Learning and Formula Optimization for Logic Design) optimization formula, which outperforms traditional methods and machine learning approaches in terms of computational efficiency and data requirements. Through finite-difference time-domain (FDTD) simulations, the proposed optical structure demonstrates successful implementation of NAND and NOR gate logic, achieving high contrast ratios of 4.2 dB and 4.8 dB, respectively. The results validate the effectiveness of the ML-FOLD method in identifying optimal configurations, offering a streamlined approach for the design of all-optical logic devices. Full article

In this study, we propose a neuromorphic computing system based on a 3D-NAND flash architecture that utilizes analog input voltages applied through wordlines (WLs). The approach leverages the velocity saturation effect in short-channel MOSFETs, which enables a linear increase in drain current with respect to gate voltage in the saturation region. A NAND flash array with a TANOS (TiN/Al₂O₃/Si₃N₄/SiO₂/poly-Si) gate stack was fabricated, and its electrical and reliability characteristics were evaluated. Output characteristics of short-channel (L = 1 µm) and long-channel (L = 50 µm) devices were compared, confirming the linear behavior of short-channel devices due to velocity saturation. In the proposed system, analog WL voltages serve as inputs, and the summed bitline (BL) currents represent the outputs. Each synaptic weight is implemented using two paired devices, and each WL layer corresponds to a fully connected (FC) layer, enabling efficient vector-matrix multiplication (VMM). MNIST pattern recognition is conducted, demonstrated only a 0.32% accuracy drop for the short-channel device compared to the ideal linear case, and 0.95% degradation under 0.5 V threshold variation, while maintaining robustness. These results highlight the strong potential of 3D-NAND flash memory, which offers high integration density and technological maturity, for neuromorphic computing applications. Full article

Microring resonators, known for their compact size, wavelength selectivity, and high-quality factor, enable efficient light manipulation, making them ideal for photonic logic applications. This paper presents the design and simulation of seven fundamental all-optical logic gates—XOR, AND, OR, NOT, NOR, NAND, and XNOR—using a seven-microring silicon-on-silica waveguide. Operating at the standard telecommunication wavelength of 1.55 µm, the proposed design exploits constructive and destructive interferences caused by phase changes in the input optical beams to perform logic operations. Numerical simulations, conducted using Lumerical FDTD Solutions, validate the performance of the logic gates, with the contrast ratio (CR) as the primary evaluation metric. The proposed design achieves CR values of 14.04 dB for XOR, 15.14 dB for AND, 15.85 dB for OR, 13.42 dB for NOT, 12.02 dB for NOR, 12.75 dB for NAND, and 14.10 dB for XNOR, significantly higher than those reported in previous works. This results in a data rate of 199.8 Gb/s, facilitated by a compact waveguide size of 1.30 × 1.35 μm². These results highlight the potential of silicon photonics and microring resonators in enabling high-performance, energy-efficient, and densely integrated optical computing and communication systems. Full article

The bandgap-engineered tunneling oxide (BE-TOX) structure has been proposed to address the incompatibility between erase efficiency and retention performance in NAND flash memory. Previous studies have primarily focused on single flash memory cells, whose architecture significantly differs from that of 3D NAND flash memory. Thus, the BE-TOX structure requires further research and optimization to improve device performance. In this study, the impact of varying proportions of the SiO₂/SiO_xN_y/SiO₂ (O1/N/O2) structure on performance is investigated using Technology Computer-Aided Design (TCAD) simulations. The results indicate that as the thickness of the N layer increases, the program/erase (P/E) speed improves, but reliability deteriorates. By adjusting the ratio of the O1 and O2 layers, the P/E speed can be optimized, and an optimal thickness can be identified. The simulation results demonstrate that the phenomenon is attributed to the combined effects of different barrier heights for charge tunneling and variations in band bending across the material layers. This study paves the way for further designing BE-TOX structures with balanced P/E performance and reliability. Full article

This work investigates a new erase scheme in NAND flash memory to improve the lifetime and performance of modern solid-state drives (SSDs). In NAND flash memory, an erase operation applies a high voltage (e.g., >20 V) to flash cells for a long time (e.g., >3.5 ms), which degrades cell endurance and potentially delays user I/O requests. While a large body of prior work has proposed various techniques to mitigate the negative impact of erase operations, no work has yet investigated how erase latency and voltage should be set to fully exploit the potential of NAND flash memory; most existing techniques use a fixed latency and voltage for every erase operation, which is set to cover the worst-case operating conditions. To address this, we propose Revisiting Erase Operation, (REO) a new erase scheme that dynamically adjusts erase latency and voltage depending on the cells’ current erase characteristics. We design REO by two key apporaches. First, REO accurately predicts such near-optimal erase latency based on the number of fail bits during an erase operation. To maximize its benefits, REO aggressively yet safely reduces erase latency by leveraging a large reliability margin present in modern SSDs. Second, REO applies near-optimal erase voltage to each WL based on its unique erase characteristics. We demonstrate the feasibility and reliability of REO using 160 real 3D NAND flash chips, showing that it enhances SSD lifetime over the conventional erase scheme by 43% without change to existing NAND flash chips. Our system-level evaluation using eleven real-world workloads shows that an REO-enabled SSD reduces average I/O performance and read tail latency by 12% and 38%, respectivley, on average over a state-of-the-art technique. Full article

The impacts of total ionizing dose (TID) were investigated in 28 nm 3D charge trapping (CT) NAND Flash memories. This study focused on the variations in the raw bit error rate (RBER) of irradiated flash across different operational modes and bias states. It was observed that the data pattern stored in Flash influences the bit error count after irradiation. The experimental findings demonstrated a dose-dependent relationship with standby current, read operation current, and threshold voltage shifts. Additionally, TID was found to affect the time required for erasure and programming operations. These results were then bench-marked against similar NAND Flash devices, revealing superior resistance to TID effects. Full article

Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays. First of all, experimental data collected down to the cryogenic regime on both charge-trap and floating-gate arrays are provided to demonstrate that the reduction in temperature makes cells harder to Erase irrespective of the nature of their storage layer. This evidence is then attributed to the weakening, with the decrease in temperature, of the gate-induced drain leakage (GIDL) current exploited to set the electrostatic potential of the body of the nand strings during Erase. Modeling results for the GIDL-assisted Erase operation, finally, allow not only to support this conclusion but also to directly correlate the change with temperature of the electrostatic potential of the string body with the change with temperature of the erased threshold-voltage of the memory cells. Full article

To successfully meet the various requirements of modern storage systems, NAND flash memory should be highly optimized by precisely tuning a huge number of internal operating parameters. Although 3D NAND flash memory succeeds in increasing the capacity of storage systems, its complex architecture and unique error behavior make such optimization a more difficult and time-consuming process during NAND manufacturing. In this paper, we introduce HAIPO, a novel methodology for post-fabrication optimization of NAND flash memory, which is an essential step in the manufacturing process of modern 3D NAND flash memory to simultaneously meet various requirements on reliability, performance, yield, etc. HAIPO is based on simple machine-learning approaches that consist of (i) a lightweight deep-learning (DL) model to generate initial device parameters and (ii) an evolutionary algorithm (EA) to explore device parameters automatically. To more effectively explore device parameters, we introduce three key guidelines for each generation in the EA: (1) domain-specific rules, (2) recent optimization results, and (3) online Bayesian simulation, respectively, to enable quick optimization for a huge number of device parameters within the limited product turnaround time (TAT). In addition, we integrate two optimization modules with HAIPO to improve optimization efficiency even in environments with severe process variation. We demonstrate the feasibility and effectiveness of HAIPO using real 320 3D TLC/QLC NAND flash chips, showing significant performance and reliability improvements by up to 8.8% and 12% on average, respectively, within a quite limited optimization TAT. Full article

With vertical stacking, 3D NAND’s flash memory can achieve continuous capacity growth. However, the endurance variation between the stacked layers becomes more and more significant due to process variation, which will lead to the underutilization of many pages and seriously affect the lifetime of 3D NAND’s flash memory. We investigated the endurance variation characteristics between layers and divided the stacked layers into the top, middle, and bottom layers according to the endurance characteristics. We found that the endurance of the bottom layer pages is much weaker than that of the other two layers, which is the primary factor that affects the lifetime of 3D NAND’s flash memory. In response to this endurance variation feature, we proposed a new layer-aware write strategy, called LA-Write. First of all, the write–skip unit in LA-Write will reduce the wear pressure of the pages through write–skip operations. Secondly, LA-Write maintains a layer-aware table, which stores the probability of pages in different layers performing the write–skip operation. Setting the probability of the bottom pages to the highest value will result in more write–skip operations on the bottom layers, mitigating endurance variations between layers. We carried out our experiments of LA-Write on DiskSim, a popular SSD simulator. Compared to existing schemes, experimental results show that LA-Write can greatly increase SSD’s lifetime. Full article

The semiconductor industry increasingly relies on high aspect ratio etching facilitated by Amorphous Carbon Layer (ACL) masks for advanced 3D-NAND and DRAM technologies. However, carbon contamination in ACL deposition chambers necessitates effective fluorine-based plasma cleaning. This study employs a high-temperature inductively coupled plasma (ICP) system and Time-of-Flight Mass Spectrometry (ToF-MS) to analyze gas species variations under different process conditions. We applied Principal Component Analysis (PCA) and Non-negative Matrix Factorization (NMF) to identify key gas species, and used the First-Order Plus Dead Time (FOPDT) model to quantify dynamic changes in gas signals. Our analysis revealed the formation of ${\mathrm{COF}}_3$ at high gas temperatures and plasma power levels, indicating the presence of additional reaction pathways under these conditions. This study provides a comprehensive understanding of high-temperature plasma interactions and suggests new strategies for optimizing ACL processes in semiconductor manufacturing. Full article

In this paper, we proposed the development of stackable 3D ferroelectric random-access memory (FeRAM), with two select transistors and n capacitors (2TnC), to address scaling limitations for bit density growth and the complicated manufacturing of 3D dynamic random-access memory (DRAM). The proposed 3D FeRAM has a 3D NAND-like architecture, with stacked metal–ferroelectric–metal (MFM) capacitors serving as memory cells in a unit string. A similar manufacturing process is used to achieve a cost-effective process and high bit density for next-generation DRAM applications. The two access transistors, string–select–line (SSL) and ground–select–line (GSL), are perfect string selections. We confirmed that the grounded back gate (GBG) of the proposed architecture can significantly improve the worst disturbance case compared to a floating back gate (FBG) like the 1TnC structure. Also, we confirmed the feasibility of performing the random-access operation during the read operation regardless of the data pattern of the selected string. Full article

Three-dimensional charge-trapping (CT) NAND flash memory has attracted extensive attention owing to its unique merits, including huge storage capacities, large memory densities, and low bit cost. The reliability property is becoming an important factor for NAND flash memory with multi-level-cell (MLC) modes like triple-level-cell (TLC) or quad-level-cell (QLC), which is seriously affected by the intervals between program (P) and erase (E) operations during P/E cycles. In this work, the impacts of the intervals between P&E cycling under different temperatures and P/E cycles were systematically characterized. The results are further analyzed in terms of program disturb (PD), read disturb (RD), and data retention (DR). It was found that fail bit counts (FBCs) during the high temperature (HT) PD process are much smaller than those of the room temperature (RT) PD process. Moreover, upshift error and downshift error dominate the HT PD and RT PD processes, respectively. To improve the memory reliability of 3D CT TLC NAND, different intervals between P&E operations should be adopted considering the operating temperatures. These results could provide potential insights to optimize the lifetime of NAND flash-based memory systems. Full article

Increasing the bit density in 3D NAND flash memory involves reducing the pitch of ON (Oxide-Nitride) molds in the Z-direction. However, this reduction drastically increases Z-interference, adversely affecting cell distribution and accelerating degradation of reliability limits. Previous studies have shown that programming from the top word line (WL) to the bottom WL, instead of the traditional bottom-to-top approach, alleviates Z-interference. Nevertheless, detailed analysis of how Z-interference varies at each WL depending on the programming sequence remains insufficient. This paper investigates the causes of Z-interference variations at Top, Middle, and Bottom WLs through TCAD analysis. It was found that as more electrons are programmed into WLs within the string, Z-interference variations increase due to increased resistance in the poly-Si channel. These variations are exacerbated by tapered vertical channel profiles resulting from high aspect ratio etching. To address these issues, a method is proposed to adjust bitline biases during verification operations of each WL. This method has been validated to enhance the performance and reliability of 3D NAND flash memory. Full article