Search Results (10)

This paper presents a successive approximation register (SAR) and incremental sigma-delta modulator (ISDM) hybrid analog-to-digital converter (ADC) that operated at a minimum voltage supply of 0.575 V. A thorough analysis of the non-linearities caused by PVT variations and common-mode voltage (VCM) shifts in the ISDM stage is presented. The ADC employs an improved high-precision double-bootstrapped switch, and the synchronous clock is also double-bootstrapped to work under the low supply voltage. A modified merged capacitor switching (MCS) approach is presented to maintain a stable VCM at the differential input. The chip was fabricated using a 0.18 µm CMOS process, with a core area of 0.21 mm². It consumed only 0.42 µW at a 0.6 V supply and a sampling rate of 10 kS/s, which achieved an effective number of bits (ENOB) of 11.03. The resulting figure of merit (FOM_W) was 20.05 fJ/conversion-step, which is the lowest reported for ADCs of this architecture in a 0.18 µm process. Full article

This work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The proposed architecture effectively reduces the kT/C noise power from the loop filter by as much as the squared gain of the added gain stage. The gain stage greatly relaxes the loop filter’s sampling capacitor requirements. The target resolution is 20 bit. The sampling frequency is 512 kHz, and the oversampling ratio (OSR) is only 256 for a target resolution. Therefore, the proposed ΔΣ ADC structure allows for high-resolution ADC design in an environment with a limited OSR. The proposed ADC designed in 65 nm CMOS technology operates at supply voltages of 1.2 V and achieves a peak signal-to-noise ratio (SNR) and Schreier Figure of Merit (FoMs) of 117.7 dB and 180.4 dB, respectively. Full article

This paper introduces a digital interface application-specific integrated circuit (ASIC) for a micro-electromechanical systems (MEMS) vibratory gyroscope. The driving circuit of the interface ASIC uses an automatic gain circuit (AGC) module instead of a phase-locked loop to realize a self-excited vibration, which gives the gyroscope system good robustness. In order to realize the co-simulation of the mechanically sensitive structure and interface circuit of the gyroscope, the equivalent electrical model analysis and modeling of the mechanically sensitive structure of the gyro are carried out by Verilog-A. According to the design scheme of the MEMS gyroscope interface circuit, a system-level simulation model including mechanically sensitive structure and measurement and control circuit is established by SIMULINK. A digital-to-analog converter (ADC) is designed for the digital processing and temperature compensation of the angular velocity in the MEMS gyroscope digital circuit system. Using the positive and negative diode temperature characteristics, the function of the on-chip temperature sensor is realized, and the temperature compensation and zero bias correction are carried out simultaneously. The MEMS interface ASIC is designed using a standard 0.18 μM CMOS BCD process. The experimental results show that the signal-to-noise ratio (SNR) of sigma-delta (ΣΔ) ADC is 111.56 dB. The nonlinearity of the MEMS gyroscope system is 0.03% over the full-scale range. Full article

This paper proposes a wide dynamic range (DR) and high-resolution discrete-time (DT) 2-order 4-bit sigma-delta modulator with a novel dynamic-modulated scaling-down (DM-SD) technology for non-invasive electroencephalogram (EEG) acquisition. The DM-SD technology can expand the input dynamic range and suppress large input offsets at the same time. The modulator was designed with 180nm CMOS technology with an area of 0.49 mm${}^2$. We achieve a 118.1 dB SNDR when the input signal is 437.5 Hz and the signal bandwidth is 1500 Hz. Due to the proposed DM-SD technology, the DR is expanded to 126 dB. The power consumption of the whole modulator is 1.6 mW and a 177.8 dB Schreier figure-of-merit (FoMs) is realized. Full article

Digital and smart sensors are commonly implemented using multi-bit $\mathsf{\Sigma }\mathsf{\Delta }$ Modulators. Undesired signals can be present at the ADC input, such as low-frequency signals with medium or high amplitude, as a consequence of mechanical artifacts in the MEMS and/or temporary signal overload. Simulations and measurements of those sensors with such signals show temporary increments of in-band noise power. This paper investigates the factors that produce this transient performance loss. Interestingly, noise increments happen when the modulator is forced to toggle between three adjacent levels and is not correlated with the typical tonal behavior of $\mathsf{\Sigma }\mathsf{\Delta }$ Modulators. Hence, the sensor performance is sensitive to some specific input patterns even if tonal behavior is decreased by dithering the input of the ADC. Different error sources, such as the mismatch between DAC cells, loop filter linearity error, and quantization error, contribute to the observed noise increments. Our aim is to analyze each of these error sources to understand and quantify in-band noise power increments, and to desensitize the ADC from the undesired input patterns. Some estimation equations are proposed and verified through extensive simulations, by means of deterministic and stochastic methods. These equations are influenced by some modulator parameters and can be used to optimize them in order to reduce such in-band noise power increments. Full article

A digital closed-loop system design of a microelectromechanical systems (MEMS) disk resonator gyroscope (DRG) is proposed in this paper. Vibration models with non-ideal factors are provided based on the structure characteristics and operation mode of the sensing element. The DRG operates in force balance mode with four control loops. A closed self-excited loop realizes stable vibration amplitude on the basis of peak detection technology and phase control loop. Force-to-rebalance technology is employed for the closed sense loop. A high-frequency carrier loaded on an anchor weakens the effect of parasitic capacitances coupling. The signal detected by the charge amplifier is demodulated and converted into a digital output for subsequent processing. Considering compatibility with digital circuits and output precision demands, a low passband sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented with a 111.8dB signal-to-noise ratio (SNR). The analog front-end and digital closed self-excited loop is manufactured with a standard 0.35 µm complementary metal-oxide-semiconductor (CMOS) technology. The experimental results show a bias instability of 2.1 °/h and a nonlinearity of 0.035% over the ± 400° full-scale range. Full article

This paper proposes an interface application-specific-integrated-circuit (ASIC) for micro-electromechanical systems (MEMS) vibratory gyroscopes. A closed self-excited drive loop is employed for automatic amplitude stabilization based on peak detection and proportion-integration (PI) controller. A nonlinear multiplier terminating the drive loop is designed for rapid resonance oscillation and linearity improvement. Capacitance variation induced by mechanical motion is detected by a differential charge amplifier in sense mode. After phase demodulation and low-pass filtering an analog signal indicating the input angular velocity is obtained. Non-idealities are further suppressed by on-chip temperature drift calibration. In order for better compatibility with digital circuitry systems, a low passband incremental zoom sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented for digital output. Manufactured in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, the whole interface occupies an active area of 3.2 mm². Experimental results show a bias instability of 2.2 °/h and a nonlinearity of 0.016% over the full-scale range. Full article

This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm². Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB. Full article

Micro-electromechanical system (MEMS) magnetic sensors are widely used in the nanosatellites field. We proposed a novel high-precision miniaturized three-axis digital tunneling magnetic resistance-type (TMR) sensor. The design of the three-axis digital magnetic sensor includes a low-noise sensitive element and high-performance interface circuit. The TMR sensor element can achieve a background noise of 150 pT/Hz^1/2 by the vertical modulation film at a modulation frequency of 5 kHz. The interface circuit is mainly composed of an analog front-end current feedback instrumentation amplifier (CFIA) with chopper structure and a fully differential 4th-order Sigma-Delta (ΣΔ) analog to digital converter (ADC). The low-frequency 1/f noise of the TMR magnetic sensor are reduced by the input-stage and system-stage chopper. The dynamic element matching (DEM) is applied to average out the mismatch between the input and feedback transconductor so as to improve the gain accuracy and gain drift. The digital output is achieved by a switched-capacitor ΣΔ ADC. The interface circuit is implemented by a 0.35 μm CMOS technology. The performance test of the TMR magnetic sensor system shows that: at a 5 V operating voltage, the sensor can achieve a power consumption of 120 mW, a full scale of ±1 Guass, a bias error of 0.01% full scale (FS), a nonlinearity of x-axis 0.13% FS, y-axis 0.11% FS, z-axis 0.15% FS and a noise density of x-axis 250 pT/Hz^1/2 (at 1 Hz), y-axis 240 pT/Hz^1/2 (at 1 Hz), z-axis 250 pT/Hz^1/2 (at 1 Hz), respectively. This work has a less power consumption, a smaller size, and higher resolution than other miniaturized magnetometers by comparison. Full article

This paper presents a novel parasitic-insensitive switched-capacitor (PISC) sensing circuit design in order to obtain high sensitivity and ultra linearity and reduce the parasitic effect for the out-of-plane single-gimbaled decoupled CMOS-MEMS gyroscope (SGDG). According to the simulation results, the proposed PISC circuit has better sensitivity and high linearity in a wide dynamic range. Experimental results also show a better performance. In addition, the PISC circuit can use signal processing to cancel the offset and noise. Thus, this circuit is very suitable for gyroscope measurement. Full article