Integrated Circuits and Systems for Smart Sensor Applications
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Editors
Dr. Francesc Serra-Graells
Dr. Francesc Serra-Graells
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Collection Editor
1. Institut de Microelectrònica de Barcelona IMB-CNM (CSIC), 08193 Barcelona, Spain
2. Dept. of Microelectronics and Electronic Systems, Universitat Autònoma de Barcelona, 08193 Barcelona, Spain
Interests: integrated circuits; ASIC; ROIC; CMOS; low-power; mixed-signal; hearing aids; IR and X-ray digital imagers; low-cost smart chemical sensors; integrated smart N/MEMS sensors; massive neural recording systems; high-resolution space instruments
Prof. Dr. Kyoungrok Cho
Prof. Dr. Kyoungrok Cho
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Website
Collection Editor
Department of Information and Communication Engineering College of Electrical and Computer Engineering, Chungbuk National University, Cheongju 362763, Korea
Interests: low-power and high speed digital circuit design; artificial retina modeling; memristor-CMOS logic design, neuromorphic circuits; CMOS image sensors; LVDS and MIPI interface circuits; IoT sensor applications; embedded controller design
Topical Collection Information
Dear Colleagues,
Connected intelligent sensing reshapes our society by empowering people with increasing new ways of mutual interactions. As integration technologies keep their scaling roadmap, the horizon of sensor applications is rapidly widening thanks to myriad lightweight self-powered smart devices with high-connectivity capabilities. Furthermore, the cost-effective large-scale manufacturing associated with these integration technologies makes their usage in low-end and disposable sensing devices also possible. In any case, integrated circuits based on CMOS technologies is clearly the best candidate to supply the required smartness and to pioneer these emerging sensor systems. As a result, new challenges are arising around the design of these integrated circuits and systems for sensor applications in terms of low-power edge computing, remote and self-powering strategies, low-range wireless communications, and low-cost device packaging.
This Special Issue aims to track the recent advances in application-specific integrated circuits and systems for smart sensor applications among, but not limited to, the following emerging topics:
- Wearable systems capable of combining physical and chemical sensing of the body and environment;
- Self-powered autonomous systems, including miniaturized sensing fuel cells, for the recognition of chemical analytes;
- Smart swallowable pills for in-body diagnostic and drug delivery;
- Implantable devices for multiparametric physiological monitoring and for neural signal recording and tracking;
- Disposables smart devices, such as sensing tags for perishable goods;
- Hybrid sensors combining smart integrated circuits and low-cost large-area printed electronics.
Dr. Francesc Serra-Graells
Prof. Dr. Kyoungrok Cho
Dr. Michele Dei
Collection Editors
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Keywords
- Smart sensors
- Integrated circuits and systems
- CMOS
- Wearable
- Self-powered
- Disposable
- Swallowable
- Implantable
- Printed electronics
Published Papers (1 paper)
2023
Open AccessArticle
An N-Type Pseudo-Static eDRAM Macro with Reduced Access Time for High-Speed Processing-in-Memory in Intelligent Sensor Hub Applications
by
Subin Kim, Ingu Jeong and Jun-Eun Park
Viewed by 624
Abstract
This paper introduces an n-type pseudo-static gain cell (PS-nGC) embedded within dynamic random-access memory (eDRAM) for high-speed processing-in-memory (PIM) applications. The PS-nGC leverages a two-transistor (2T) gain cell and employs an n-type pseudo-static leakage compensation (n-type PSLC) circuit to significantly extend the eDRAM’s
[...] Read more.
This paper introduces an n-type pseudo-static gain cell (PS-nGC) embedded within dynamic random-access memory (eDRAM) for high-speed processing-in-memory (PIM) applications. The PS-nGC leverages a two-transistor (2T) gain cell and employs an n-type pseudo-static leakage compensation (n-type PSLC) circuit to significantly extend the eDRAM’s retention time. The implementation of a homogeneous NMOS-based 2T gain cell not only reduces write access times but also benefits from a boosted write wordline technique. In a comparison with the previous pseudo-static gain cell design, the proposed PS-nGC exhibits improvements in write and read access times, achieving 3.27 times and 1.81 times reductions in write access time and read access time, respectively. Furthermore, the PS-nGC demonstrates versatility by accommodating a wide supply voltage range, spanning from 0.7 to 1.2 V, while maintaining an operating frequency of 667 MHz. Fabricated using a 28 nm complementary metal oxide semiconductor (CMOS) process, the prototype features an efficient active area, occupying a mere 0.284 µm
2 per bitcell for the 4 kb eDRAM macro. Under various operational conditions, including different processes, voltages, and temperatures, the proposed PS-nGC of eDRAM consistently provides speedy and reliable read and write operations.
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