Dear Colleagues,

In recent years, deep neural networks (DNNs) have achieved overwhelming success in different artificial intelligence applications. This great success is mainly due to the availability of the GPU and TPU clusters that can train very deep models with thousands of layers and millions/billions of parameters on large-scale datasets. However, such cumbersome DNNs require heavy computation resources, which makes their deployment on devices with limited computational capacity and memory (embedded devices, mobile phones, etc.) very difficult. To overcome this limitation, algorithmic, architectural, and technological efforts could be made. From the algorithmic point of view, DNN compression techniques seem to be an attractive solution. Moreover, some innovative architectures and design flows have been attempted for deployment to reach the compromise between precision and energy efficiency. To summarize, the main challenge is to propose heavy architectures or optimized algorithms that achieve approximately the same performance when compared to the original versions.

This Special Issue aims to cover the new developments and recent advances in the compression of the deep neural networks for real-time applications. The topic includes but is not limited to the following:

• Cloud/FoG/Edge DNN challenges;
• Knowledge distillation;
• Parameters pruning and quantization;
• Design flow and low power systems;
• Low-rank factorization;
• Transferred compact convolutional filters;
• Hardware accelerators.

Dr. Jridi Maher
Dr. Thibault Napoléon
Dr. Ayoub Karine
Guest Editors

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• deep neural networks
• knowledge distillation
• pruning/quantization model compression
• computer visions
• internet of things
• CNN
• FPGA, SoPC, GPU
• IoMT : internet of multimedia things
• algorithmic optimization
• computational complexity reduction
• AI implementation challenges
• image processing

Title: Embedded Deep Learning Accelerators on RISC-V Processors: A Survey on Recent Advances
Authors: Ghattas Akkad
Affiliation: [email protected], VISION-AD, ISEN Yncrea Ouest, 44470 Carquefou, France
Abstract: The exponential increase in generated data as well as the advances in high-performance computing have paved the way for the use of complex machine learning methods. Indeed, the availability of Graphical Processing Units (GPU) and Tensor Processing Units (TPU) have made it possible to train and prototype Deep Neural Networks (DNN) on large-scale data sets and for a variety of applications, i.e., vision, robotics, medical, etc. The popularity of these DNNs originates from their efficacy and state-of-the-art inference accuracy, however at the cost of a considerably high computational complexity. Rendering their implementation on limited resources, edge devices, without a major loss in inference accuracy, a dire and challenging task. To this extent, it has become extremely important to design innovative architectures and dedicated accelerators to port these DNNs to embedded and re-configurable processors with a high-performance low complexity structure. In this study, we present an extensive survey on recent advances in deep learning accelerators (DLA) for RISC-V processors given their open-source nature, accessibility, customizability and universality. After scanning through this article, the reader should have a comprehensive overview of the recent progress in this domain as well as cutting edge knowledge of up-to-date embedded machine learning trends.