Special Issue "Building Three-Dimensional Integrated Circuits and Microsystems"

A special issue of Processes (ISSN 2227-9717). This special issue belongs to the section "Automation Control Systems".

Deadline for manuscript submissions: closed (30 September 2022) | Viewed by 3216

Special Issue Editors

Prof. Dr. Zhiyuan Zhu
E-Mail Website
Guest Editor
College of Electronic and Information Engineering, Southwest University, Chongqing 400715, China
Interests: micro/nano fabrication process; nano energy harvesting process
Special Issues, Collections and Topics in MDPI journals
Dr. Shenglin Ma
E-Mail Website
Guest Editor
Department of Mechanical and Electrical Engineering, Xiamen University, Xiamen 361005, China
Interests: 3D integration; Through Silicon Vias (TSVs); wafer bonding technology; embedded microfluidic cooling technology; PMUT and its applications
Special Issues, Collections and Topics in MDPI journals
Dr. Ziyu Liu
E-Mail Website
Guest Editor
School of Microelectronic, 220 Handan Rd., Fudan University, Shanghai 200433, China
Interests: through silicon vias (TSVs); interposer; reiability; simulation

Special Issue Information

Dear Colleagues,

With continuous innovation in chip technologies, three-dimensional (3D) integration technology has made great contributions to the development of microsystems. By stacking and bonding multi-layer integrated circuits in the vertical direction, 3D integration realizes complex microsystems at a low cost while maintaining high performance and high integrated functions. Advanced integration technologies for building 3D integrated circuits and microsystems have greatly promoted the diversified development of the semecondutor industry by promoting chip integration from devices/components packaging to system packaging. Therefore, in order to meet the needs of the development of the times, it is of great value to revisit research on three-dimensional integrated circuits and microsystems.

This Special Issue on "Building Three-Dimensional Integrated Circuits and Microsystems" aims to collect all outstanding research results and comprehensive reports related to 3D integrated circuits and microsystems, covering all kinds of innovative technologies and various technical optimization methods, which include both contemporary and future prospects. Topics include, but are not limited to:

  • Micro/nano fabrication technology related to 3D integration, e.g., Cu–Cu pilar bump bonding, high-density RDL, TSV fabrication, Cu pillar, wafer bonding, etc.;
  • 2.5D/3D heterogeneous integration, fan-out packaging, 3D hybrid integration, RF 3D integration, 3D passive device, 3D antenna, 3D heterogeneous opto-electronic integration, and thermal management;
  • Design Automation, process/device/packaging simulation, and thermal mechanical reliability of 3D integration;
  • Novel materials, components, circuits and technology to be used in 3D integration, e.g., 2D materials, triboelectronic nanogenerator, artificial intelligence, etc.

Prof. Dr. Zhiyuan Zhu
Dr. Shenglin Ma
Dr. Ziyu Liu
Guest Editors

Manuscript Submission Information

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Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-blind peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Processes is an international peer-reviewed open access monthly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 2000 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • 3D integration
  • microsystems
  • wafer bonding
  • through silicon vias (TSVs)
  • interposer
  • reiability
  • simulation

Published Papers (5 papers)

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Research

Article
Design, Manufacture and Assembly of 3D Integrated Optical Transceiver Module Based on an Active Photonic Interposer
Processes 2022, 10(11), 2342; https://doi.org/10.3390/pr10112342 - 10 Nov 2022
Viewed by 222
Abstract
The new generation of data centers is further evolving towards the direction of high speed and intelligence, which puts forward a great demand for the iteration of optical interconnection technology. Three-dimensional integration based on active photonic interposers can achieve the advantages of high [...] Read more.
The new generation of data centers is further evolving towards the direction of high speed and intelligence, which puts forward a great demand for the iteration of optical interconnection technology. Three-dimensional integration based on active photonic interposers can achieve the advantages of high integration, high bandwidth and low power consumption, which has become the main direction for next generation optical module technology. The fabrication and assembly of 3D optical modules based on active interposer-integrated edge couplers and TSV are realized in this paper. Different active interposer processes with integrated edge couplers and RDL-TSV-RDL structures are discussed, manufactured, analyzed and evaluated. The problem of the co-fabrication of the TSV and edge coupler was solved, and perfect electrical and optical characteristics were also achieved. Finally, the fabrication of the substrate and the assembly of the 3D optical module were completed. This paper lays a solid foundation for the further research and large-scale application of 3D optical modules in the future. Full article
(This article belongs to the Special Issue Building Three-Dimensional Integrated Circuits and Microsystems)
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Article
Al-Sn-Al Bonding Strength Investigation Based on Deep Learning Model
Processes 2022, 10(10), 1899; https://doi.org/10.3390/pr10101899 - 20 Sep 2022
Viewed by 363
Abstract
Al-Sn-Al wafer bonding is a new semiconductor manufacturing technology that plays an important role in device manufacturing. Optimization of the bonding process and testing of the bonding strength remain key issues. However, using only physical experiments to study the above problems presents difficulties [...] Read more.
Al-Sn-Al wafer bonding is a new semiconductor manufacturing technology that plays an important role in device manufacturing. Optimization of the bonding process and testing of the bonding strength remain key issues. However, using only physical experiments to study the above problems presents difficulties such as repeating many experiments, high costs, and low efficiency. Deep learning algorithms can quickly simulate complex physical correlations by training large amounts of data, which is a good solution to the difficulties in studying wafer bonding. Therefore, this paper proposes the use of deep learning models (2-layer CNN and 50-layer ResNet) to achieve autonomous recognition of bonding strengths corresponding to different bonding conditions, and the results from a comparative test set show that the ResNet model has an accuracy of 99.17%, outperforming the CNN model with an accuracy of 91.67%. Then, the identified images are analyzed using the Canny edge detector, which showed that the fracture surface morphology of the wafer is a hole-shaped structure, with the smaller the area of hole movement on the wafer surface, the higher the bonding strength. In addition, the effects of bonding time and bonding temperature on bonding strength are verified, showing that relatively short bonding times and relatively low bonding temperatures resulted in better wafer bonding strength. This research demonstrates the potential of using deep learning to accelerate wafer bonding strength identification and process condition optimization. Full article
(This article belongs to the Special Issue Building Three-Dimensional Integrated Circuits and Microsystems)
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Article
Optimization of Two-Dimensional Extended Warranty Scheme for Failure Dependence of a Multi-Component System with Improved PSO–BAS Algorithm
Processes 2022, 10(8), 1479; https://doi.org/10.3390/pr10081479 - 28 Jul 2022
Cited by 2 | Viewed by 356
Abstract
Human society is entering the era of Industry 4.0; engineering systems are becoming more complex, which increases the difficulties of maintenance support work. Failure dependence exists widely in multi-component systems. In this work, a model of two-dimensional (2D) warranty decision making was constructed [...] Read more.
Human society is entering the era of Industry 4.0; engineering systems are becoming more complex, which increases the difficulties of maintenance support work. Failure dependence exists widely in multi-component systems. In this work, a model of two-dimensional (2D) warranty decision making was constructed by using a failure-dependence analysis for multi-component systems and by considering the extended warranty cost and the system availability. The decision was to cut the warranty cost as much as possible for manufacturers, while the constraint condition was the minimum acceptable availability for the customer. The model combined preventive maintenance as well as corrective maintenance strategies. Under the condition that the multi-component system is replaced upon the expiration of the extended warranty (EW), the optimal 2D EW duration and preventive maintenance interval could be obtained through the model. In a case analysis, the optimal EW scheme for the gearbox of an electric multiple unit (EMU) system was obtained by using a grid search algorithm, a PSO algorithm, and a PSO–BAS algorithm. Through comparison, the PSO–BAS algorithm obtained a better scheme with lower warranty costs and higher system availability. A comparative analysis and a sensitivity analysis showed that the model provides a theoretical basis for manufacturers to optimize their 2D extended gearbox warranties. Full article
(This article belongs to the Special Issue Building Three-Dimensional Integrated Circuits and Microsystems)
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Article
Sub-THz Small-Signal Equivalent Circuit Model and Parameter Extraction for 3 nm Gate-All-Around Nanosheet Transistor
Processes 2022, 10(6), 1198; https://doi.org/10.3390/pr10061198 - 16 Jun 2022
Viewed by 507
Abstract
This paper presents a novel RF small-signal equivalent circuit model and parameter extraction for 3 nm nanosheet gate-all-around field effect transistor (GAAFET). The extrinsic parasitic effect induced by ground-signal-ground (GSG) layout is evaluated by 3D full-wave electromagnetic simulation, and an improved five-step analytical [...] Read more.
This paper presents a novel RF small-signal equivalent circuit model and parameter extraction for 3 nm nanosheet gate-all-around field effect transistor (GAAFET). The extrinsic parasitic effect induced by ground-signal-ground (GSG) layout is evaluated by 3D full-wave electromagnetic simulation, and an improved five-step analytical parameter extraction method is proposed for such extrinsic GSG layout. The model parameters for the intrinsic device are analytically determined with the help of nonlinear rational function fitting. The accuracy of the proposed extraction method was confirmed via comparisons between device simulator and electromagnetic simulator with frequency responses up to 300 GHz. Excellent agreement is obtained between the simulated and modeled S-parameters, and the calculated error is lower than 2.689% for the extrinsic layout, and 0.897% for the intrinsic device in the whole frequency range among multi-bias points. Full article
(This article belongs to the Special Issue Building Three-Dimensional Integrated Circuits and Microsystems)
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Article
Crosstalk Noise of Octagonal TSV Array Arrangement Based on Different Input Signal
Processes 2022, 10(2), 260; https://doi.org/10.3390/pr10020260 - 28 Jan 2022
Viewed by 690
Abstract
This paper proposes an octagonal layout for enhancing the ability of resisting electromagnetic interference in Through Silicon Via (TSV) array. The influential factors of crosstalk noise between TSVs are investigated, including the TSV pitch, signal and ground TSVs location, and signal types (single-end [...] Read more.
This paper proposes an octagonal layout for enhancing the ability of resisting electromagnetic interference in Through Silicon Via (TSV) array. The influential factors of crosstalk noise between TSVs are investigated, including the TSV pitch, signal and ground TSVs location, and signal types (single-end and differential signal) by using a coplanar wave guide (CPW) testing structure. These results, based on traditional TSV arrays, show that a staggered TSV layout with differential signals had lower crosstalk noise. On this basis, the octagonal layout of TSV array is proposed and we show that it has obvious superiority in reducing occupied silicon area and crosstalk noise. Compared with traditional TSV arrays, the crosstalk noise is almost reduced by 44%. In order to further reduce the silicon area occupied by TSV without worsening crosstalk noise, the new division TSV structure is proposed in which a large TSV was substituted by four smaller TSVs. The area occupied by a single TSV and TSV array are both reduced by 60% without decreasing signal integrity when the regular TSV in the octagonal layout are replaced by a new TSV structure. Full article
(This article belongs to the Special Issue Building Three-Dimensional Integrated Circuits and Microsystems)
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