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Neuromorphic Chips at the Intersection of Neuroscience, Electronics and AI
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Neuromorphic Chips at the Intersection of Neuroscience, Electronics and AI

A Special Issue of Chips (ISSN 2674-0729).

Deadline for manuscript submissions: 31 December 2026 | Viewed by 21311

Editors

Dr. Liangshun Wu

E-Mail Website
Guest Editor
School of Integrated Circuit and School of Information Science and Electronic Engineering, Shanghai Jiao Tong University, Shanghai, China
Interests: neuromorphic computing; brain-inspired computing; integrated circuits; machine learning hardware; FPGA; AI hardware acceleration; edge AI
Dr. Pak Kwong Chan

E-Mail Website
Guest Editor
School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore, Singapore
Interests: sensor interface ICs; smart sensor systems; low-energy low-noise circuit design; sensor power management ICs; PVT-insensitive circuits and systems
Special Issues, Collections and Topics in MDPI journals

Special Issue Information

Dear Colleagues,

Neuromorphic chips—integrating concepts from neuroscience, electronics, and artificial intelligence—are revolutionizing the landscape of intelligent hardware and computing systems. By mimicking the neural structures and processes of the brain, neuromorphic devices offer new opportunities for efficient, adaptive, and low-power computation well-suited for edge AI, brain–computer interfaces, robotics, sensory processing, and more.

Recent advances in device technologies, circuit architectures, and computational models have enabled the development of neuromorphic systems that can process information in real time, adapt to changing environments, and learn from experience—just like biological brains. These innovations bridge the gap between neuroscience-inspired algorithms and scalable silicon implementations, fostering a new generation of chips that combine the best of biological and artificial intelligence.

This Special Issue aims to showcase recent breakthroughs in neuromorphic hardware and systems at the intersection of neuroscience, electronics, and AI. We welcome submissions covering innovative circuit and system designs, emerging device technologies, brain-inspired algorithms, in-memory and event-driven computing, sensory processing hardware, and real-world applications of neuromorphic chips. We particularly encourage interdisciplinary works that highlight the synergy among neuroscience, microelectronics, and artificial intelligence.

We look forward to your contributions that will drive the future of intelligent, brain-inspired hardware.

Dr. Liangshun Wu
Dr. Pak Kwong Chan
Guest Editors

Manuscript Submission Information

Manuscripts should be submitted online at www.mdpi.com by registering and logging in to this website. Once you are registered, click here to go to the submission form. Manuscripts can be submitted until the deadline. All submissions that pass pre-check are peer-reviewed. Accepted papers will be published continuously in the journal (as soon as accepted) and will be listed together on the special issue website. Research articles, review articles as well as short communications are invited. For planned papers, a title and short abstract (about 250 words) can be sent to the Editorial Office for assessment.

Submitted manuscripts should not have been published previously, nor be under consideration for publication elsewhere (except conference proceedings papers). All manuscripts are thoroughly refereed through a single-anonymized peer-review process. A guide for authors and other relevant information for submission of manuscripts is available on the Instructions for Authors page. Chips is an international peer-reviewed open access quarterly journal published by MDPI.

Please visit the Instructions for Authors page before submitting a manuscript. The Article Processing Charge (APC) for publication in this open access journal is 1200 CHF (Swiss Francs). Submitted papers should be well formatted and use good English. Authors may use MDPI's English editing service prior to publication or during author revisions.

Keywords

  • neuromorphic computing
  • integrated circuits
  • brain-inspired computing
  • analog and mixed-signal IC design
  • in-memory computing
  • AI hardware
  • sensor interfaces
  • edge computing
  • memristive devices
  • spiking neural networks
  • low-power design
  • machine learning accelerators
  • biomedical circuits
  • IoT hardware
  • bio-sensing chips

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Published Papers (3 papers)

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Research

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11 pages, 795 KB  
Article
Hardware Efficient FPGA Implementation of a Layered QC-LDPC Decoder for Ultra-Reliable Low-Latency Communications
by Bilal Mejmaa, Chakir Aqil, Abdelaziz Lberni, Ismail Akharraz and Abdelaziz Ahaitouf
Chips 2026, 5(3), 22; https://doi.org/10.3390/chips5030022 - 4 Aug 2026
Viewed by 451
Abstract
Low-Density Parity-Check (LDPC) codes have traditionally performed better at longer code lengths. This research develops and rigorously evaluates a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G and subsequent technologies. The paper investigates LDPC codes [...] Read more.
Low-Density Parity-Check (LDPC) codes have traditionally performed better at longer code lengths. This research develops and rigorously evaluates a layered Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder architecture intended for Ultra-Reliable Low-Latency Communication (URLLC) applications in 5G and subsequent technologies. The paper investigates LDPC codes in short-length contexts through architectural optimization based on a layered decoding approach, which provides improved convergence speed and reduced latency compared with traditional flooding techniques. The short block-length QC-LDPC code (280,176) addresses the dual challenge of achieving ultra-low latency while maintaining high performance relative to existing work. For a target BLER of 10−2, the decoder outperforms the shorter reference codes (60,40) and (96,64), with an Eb/N0 gain of up to 0.9 dB, part of which is attributable to the longer block length rather than to the decoder alone. The FPGA implementation results demonstrate that the design is hardware-efficient: it operates at a maximum frequency of 218.62 MHz, resulting in a throughput of 155.77 Mbps, while maintaining a decoding latency of only 1.129 µs and a power consumption of 0.201 W. Full article
(This article belongs to the Special Issue Neuromorphic Chips at the Intersection of Neuroscience, Electronics and AI)
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25 pages, 3750 KB  
Article
The Spike Processing Unit (SPU): An IIR Filter Approach to Hardware-Efficient Spiking Neurons
by Hugo Puertas de Araújo
Chips 2026, 5(2), 11; https://doi.org/10.3390/chips5020011 - 30 Apr 2026
Viewed by 494
Abstract
This paper presents the Spike Processing Unit (SPU), a digital spiking neuron model based on a discrete-time second-order Infinite Impulse Response (IIR) filter. By constraining filter coefficients to powers of two, the SPU implements all internal operations via shift-and-add arithmetic on 6-bit signed [...] Read more.
This paper presents the Spike Processing Unit (SPU), a digital spiking neuron model based on a discrete-time second-order Infinite Impulse Response (IIR) filter. By constraining filter coefficients to powers of two, the SPU implements all internal operations via shift-and-add arithmetic on 6-bit signed integers, eliminating general-purpose multipliers. Unlike traditional models, computation in the SPU is fundamentally temporal; spike timing emerges from the interaction between input events and internal IIR dynamics rather than signal intensity accumulation. The model’s efficacy is evaluated through a temporal pattern discrimination task. Using Particle Swarm Optimization (PSO) within a hardware-constrained parameter space, a single SPU is optimized to emit pattern-specific spikes while remaining silent under stochastic noise. Results from cycle-accurate Python simulations and synthesizable VHDL implementations indicate that the learned temporal dynamics are preserved under hardware-constrained digital execution, supporting the feasibility of the proposed approach. This work demonstrates that discrete-time IIR-based neurons enable reliable temporal spike processing under strict quantization and arithmetic constraints. Full article
(This article belongs to the Special Issue Neuromorphic Chips at the Intersection of Neuroscience, Electronics and AI)
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Review

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45 pages, 14875 KB  
Review
A New Era in Computing: A Review of Neuromorphic Computing Chip Architecture and Applications
by Guang Chen, Meng Xu, Yuying Chen, Fuge Yuan, Lanqi Qin and Jian Ren
Chips 2026, 5(1), 3; https://doi.org/10.3390/chips5010003 - 22 Jan 2026
Cited by 7 | Viewed by 17294
Abstract
Neuromorphic computing, an interdisciplinary field combining neuroscience and computer science, aims to create efficient, bio-inspired systems. Different from von Neumann architectures, neuromorphic systems integrate memory and processing units to enable parallel, event-driven computation. By simulating the behavior of biological neurons and networks, these [...] Read more.
Neuromorphic computing, an interdisciplinary field combining neuroscience and computer science, aims to create efficient, bio-inspired systems. Different from von Neumann architectures, neuromorphic systems integrate memory and processing units to enable parallel, event-driven computation. By simulating the behavior of biological neurons and networks, these systems excel in tasks like pattern recognition, perception, and decision-making. Neuromorphic computing chips, which operate similarly to the human brain, offer significant potential for enhancing the performance and energy efficiency of bio-inspired algorithms. This review introduces a novel five-dimensional comparative framework—process technology, scale, power consumption, neuronal models, and architectural features—that systematically categorizes and contrasts neuromorphic implementations beyond existing surveys. We analyze notable neuromorphic chips, such as BrainScaleS, SpiNNaker, TrueNorth, and Loihi, comparing their scale, power consumption, and computational models. The paper also explores the applications of neuromorphic computing chips in artificial intelligence (AI), robotics, neuroscience, and adaptive control systems, while facing challenges related to hardware limitations, algorithms, and system scalability and integration. Full article
(This article belongs to the Special Issue Neuromorphic Chips at the Intersection of Neuroscience, Electronics and AI)
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