Chips, Volume 3, Issue 4

This work introduces a novel custom-designed 16-bit RISC-V processor, intended for educational purposes and for use in low-resource equipment. The implementation, despite providing registers of 16 bits, is based on RV32E RISC-V ISA, but with some key...

We have developed SWA: SoftWare for Analog design automation. Its commands can describe analog and mixed-signal (AMS) layouts and schematics to replace the graphic editor with a program reflecting the knowledge of design experts. Also, it is able to...

This paper presents an advanced Controller Area Network (CAN) bus transceiver designed to enhance security using frame-level authentication with the concept of a nonphysical virtual auxiliary data channel. We describe the newly conceived transceiver...

FPGAs are popular in many fields but have yet to gain wide acceptance for accelerating HPC codes. A major cause is that whilst the growth of High-Level Synthesis (HLS), enabling the use of C or C++, has increased accessibility, without widespread alg...

Physical side-channel attacks utilize power, electromagnetic (EM), or timing signatures from cryptographic implementations during operation to retrieve sensitive information from security-critical devices. This paper provides a comprehensive review o...

The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs. Among the various NS-SAR approaches, the recent eme...

With the development of artificial intelligence and edge computing, the demand for high-performance non-volatile memory devices has been rapidly increasing. Two-dimensional materials have ultrathin bodies, ultra-flattened surfaces, and superior physi...