# Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering

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## Abstract

**:**

## 1. Introduction

## 2. Principle of Integrator with Capacitor Stacking and Buffering

#### 2.1. One-Time Integration

#### 2.2. Continual Integration

#### 2.3. Differential Integration

## 3. Noise-Shaping SAR ADC with CSB Integrator

## 4. Design Consideration and Circuit Implementation

#### 4.1. The Parasitic Capacitance from Capacitor Stacking

#### 4.2. Non-Idealities from Switches

#### 4.3. Integrator Design

#### 4.4. Buffer Design

## 5. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 5.**NS-SAR ADC survey [20].

**Figure 10.**A 4th-order NS-SAR ADC with capacitor stacking and buffering [16].

**Figure 17.**Differential buffer $B{F}_{1}$ with the 2-phase settling for fast settling and low noise.

ISSCC 16 Shu [2] | ISSCC 17 Liu [10] | ISSCC 20 Liu [14] | ISSCC 20 Tang [3] | ISSCC 20 Jie [9] | ISSCC 22 Wang [19] | ISSCC 23 Wang [18] | ISSCC 24 Cheng [17] | ISSCC 21 Liu [16] | |
---|---|---|---|---|---|---|---|---|---|

Process | 55 nm | 28 nm | 40 nm | 40 nm | 28 nm | 65 nm | 28 nm | 28 nm | 40 nm |

NS Technique | Closed-loop OTA | Open-loop DA | CS ^{1} | Closed-loop DA | Open-loop amp. | Cap stack. ^{2} & DA& CS | Cap stack. & dynamic buffering & Passive gain | Cap stack. & DA & Passive gain | Cap stack. & dynamic buffering |

NS Order | 1 | 1 | 1 | 2 | 4 | 4 | 2 | 4 | 4 |

Sharp NTF Across PVT | Yes | No | No | Yes | No | Yes | Yes | Yes | Yes |

Supply (V) | 1.2 | 1 | 1.1 | 1.1 | 1 | 1.2/2 | 2 | 1 | 1.1 |

Area (mm^{2}) | 0.072 | 0.0049 | 0.061 | 0.037 | 0.02 | 0.075 | 0.026 | 0.09 | 0.094 |

${F}_{s}$ (MS/s) | 1 | 132 | 2 | 10 | 2 | 5 | 2.4 | 5 | 5 |

Power (μW) | 15.7 | 460 | 67.4 | 107 | 120 | 73.8/133.88 ^{3} | 160 | 107.38 | 340 |

OSR | 500 | 13.2 | 25 | 8 | 10 | 5 | 8 | 25 | 10 |

BW (kHz) | 1 | 5000 | 40 | 625 | 100 | 500 | 150 | 100 | 250 |

SNDR (dB) | 101 | 79.7 | 90.5 | 83.8 | 87.6 | 84.1 | 92.5 | 94.3 | 93.3 |

DR (dB) | 101.7 | 81.8 | 94.3 | 85.5 | 89 | 84.9 | 93.9 | 94.6 | 95 |

$Fo{M}_{s}$ ^{4} (dB) | 178.9 | 180.1 | 178.2 | 181.5 | 176.8 | 182.4/180 ^{3} | 182.2 | 184 | 182 |

^{1}CS = Charge sharing.

^{2}Cap stack = Cap stacking.

^{3}With Buffer Power Included.

^{4}$Fo{M}_{s}=\mathrm{SNDR}+10{log}_{10}(\mathrm{BW}/\mathrm{Power})$.

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**MDPI and ACS Style**

Shen, Z.; Yang, S.; Liu, J.
Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering. *Chips* **2024**, *3*, 296-310.
https://doi.org/10.3390/chips3040015

**AMA Style**

Shen Z, Yang S, Liu J.
Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering. *Chips*. 2024; 3(4):296-310.
https://doi.org/10.3390/chips3040015

**Chicago/Turabian Style**

Shen, Zhaoyang, Shiheng Yang, and Jiaxin Liu.
2024. "Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering" *Chips* 3, no. 4: 296-310.
https://doi.org/10.3390/chips3040015