Reliability Improvement of 28 nm Intel FPGA Ring Oscillator PUF for Chip Identification

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The authors present a method to improve the reliability of RO-PUFs on FPGA. While the paper is generally well-structured and presents a practical application, it requires major revision before it can be considered for publication:

1. The architecture shown in Figure 1 is overly abstract. Could the authors add internal signal labels, such as ring paths, counters, or multiplexers, to clarify the RO structure?
2. Temperature and voltage variability are important for PUF reliability, but no experiments are conducted under such conditions. The paper mentions that the measurements were repeated at low and high temperatures. But I couldn't find specific temperature data.
3. Could the authors discuss long-term reliability and aging of the RO-PUFs, since oscillator frequency can drift over time?
4. No discussion is given on the implementation overhead (LUTs, power, or area) of the added reliability mechanisms. Are they lightweight enough for scalable use in commercial FPGA security?
5. The figures, especially Figures 4, 5, and 6, lack proper labeling, and Figures 3, 7, and 8 also lack resolution. For example, Figure 4 should indicate the names of the bar colors. Figures 5 and 6 lack Y-axis labels. Could the authors revise these figures to improve clarity and standardize formatting and labeling across all plots?
6. Provide a discussion section reflecting on the reliability, generalizability to other FPGAs  and potential future work. Currently, the conclusion is very brief and lacks reflection.

 

 

 

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

This paper presents a method to improve the reliability of RO-PUFs (Ring Oscillator Physical Unclonable Functions) implemented on 28nm Intel Cyclone V FPGAs. The key novelty lies in utilizing the built-in ARM Cortex A9 hard processor for on-chip processing of RO frequencies and response generation using a frequency-mapped Q-factor-based approach. The authors propose a new frequency mapping method and quantization strategy to generate response bits with high reliability. The work improves the reliability to 95.8%, using a frequency equalization scheme and Q-value filtering, while minimizing area overhead by offloading processing to the hard processor subsystem (HPS). The paper proposes a solid and interesting method but needs stronger clarity, better comparative analysis, clearer algorithmic explanation, and improved English language structure to meet publication standards.

1. The paper heavily relies on Q-factor-based response generation but lacks a rigorous explanation or theoretical backing for the choice of specific Q combinations (Q2, Q3, etc.) or how filtering improves reliability.
2. The study is conducted only on 11 FPGA chips, which is quite limited for statistically validating PUF metrics like uniqueness, reliability, and bit aliasing.
3. The approach is tailored for Cyclone V with an ARM processor. How well this method scales to other FPGAs (e.g., Xilinx Zynq or Lattice FPGAs) is not discussed in depth.
4. To improve the discussion on recent techniques and broaden the context, the following papers should be cited:
   1. Kernel-based response extraction approach for efficient configurable ring oscillator PUF
   2. SQTRNG: Spintronic Quaternary True Random Number Generator
5. Only 25°C and 50°C are tested. Voltage variation or aging tests would add to the robustness of the results.

Author Response

Please see the attachment.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

The authors have satisfactorily addressed my comments. I have no further comments and the latest version of the paper is suitable for publication.

Reviewer 2 Report

Comments and Suggestions for Authors

The authors addressed all of my previous comments and concerns. Now the paper can be considered for publication.