200G VCSEL Development and Proposal of Using VCSELs for Near-Package-Optics Scale-Up Application ^†

Abstract

The connectivity demands of high-performance computing (HPC), artificial intelligence (AI) and data centers are driving the development of a new generation of multimode optical components. This paper discusses the vertical cavity surface emitting laser (VCSEL) bandwidth and noise performance needed to support 106 Gbd line rates with PAM4 modulation for 200 Gbps per lane multimode optical links. A −3 dB bandwidth greater than 35 GHz and a RIN of less than −152 dB/Hz are demonstrated. No uncorrectable errors were observed over 50 m of OM4 fiber, demonstrating good link stability. VCSEL device performance and the associated wear-out life are presented. Leveraging good device reliability and low power consumption of VCSEL-based links, a novel VCSEL near-packaged optics (NPO) concept is proposed for optical interconnects in AI scale-up network applications. Optical interconnects allow for longer reaches, compared to copper interconnects, which facilitate larger AI clusters with network disaggregation. The proposed VCSEL NPO can achieve an energy efficiency of ~1 pJ/bit, which is the highest among optical interconnects.

1. Introduction

VCSEL-based multimode links have supported many generations of HPC and datacenter connectivity needs by offering a value proposition of low power consumption and uncooled bandwidth performance, coupled with superior reliability and scalable manufacturing at a low cost [1,2,3,4]. For more than two decades, the performance of VCSELs (Figure 1) has enabled multimode active optical cables (AOC) and transceivers to dominate short-reach optical channels. Presently, VCSELs that are capable of four-level pulse amplitude modulation (PAM4) at 53–56 GBd (denoted as 100 Gbps PAM4) per channel are in volume production [5]. The development of 850 nm VCSELs that are capable of operation at 100 GBd (denoted as 200 Gbps PAM4) will enable another generation of enterprise and storage networks and switch-to-server and switch-to-switch connections in data centers. Recently, several research groups and commercial companies [6,7,8] have reported impressive results in excess of 100 Gbps PAM4, including using a lithographically defined aperture VCSEL [9]. In addition, a transverse coupled cavity 1060 nm VCSEL design [10,11], single-mode and Multi-Aperture VCSELs [12,13,14], and bidirectional multimode links [15] have been demonstrated. We note that among all the efforts, while 850 nm VCSELs have been widely used, along with standard based multimode fibers optimized for the 850 nm wavelength window, there has been interest in using 1060 nm VCSELs [7,10,11]. These results show that VCSELs have the promise to meet the demands for 200 Gbps per channel data communication.

The design, performance and reliability of our PAM4 at 53–56 GBd VCSEL have been discussed elsewhere [5]. Substantial improvements in both the bandwidth and noise performance of 850 nm VCSELs have been demonstrated to enable 200 Gbps per channel transmission. In March 2024, at OFC, we presented “Toward 200G per lane VCSEL-based multimode links” [16] and demonstrated 200 Gbps with uncorrected BER below 1 × 10⁻⁶. In September 2024, at ECOC, multimode links at 200 Gbps with uncorrected BER less than 1 × 10⁻⁷ were demonstrated. Further improvements were made and in March 2025 at OFC, an uncorrected BER ~ 1 × 10⁻⁸ was demonstrated. A maximum of five correctable frame errors over a 50 m OM4 link, over 9 h of traffic, was also demonstrated at OFC 2025 (Figure 2), showing good link stability.

In this paper, we present the progress on the development of a 200 Gbps PAM4 850 nm VCSEL, which meets the demands of next generation data transmission where the overall design approach focused not on the VCSEL with the fastest speed possible and the lowest noise possible, but rather on a reliable VCSEL with optimized performance. Our design is based on a well-established production epi and fab process flow used for 100 Gbps VCSEL products which have a proven track record of high-volume manufacturability, reliability and superior performance over temperature.

As AI scale-up networking expands wider connectivity scales to larger numbers of accelerators (GPUs or XPUs), optical interconnects will be needed to connect across longer distances. Power efficiency, reliability, escape bandwidth density and cost are important considerations to drive the wide adoption of optical interconnects. To support AI scale-up networking, a VCSEL-based near-package optics (NPO) concept, leveraging its good field reliability and low cost, is proposed in this paper, meeting the above criteria.

In Section 2, we present the device design and fabrication. Section 3 will cover device characterization for key parameters such as the S21 response and RIN. Large-signal responses that are representative of the drive conditions in field applications and device reliability are also presented. Section 4 discusses the application of VCSEL in scale-up applications in the form of a near-package-optics module, leveraging the good field reliability and low cost. Section 5 discusses the key design parameters and performance of the 200 Gbps VCSEL.

2. Device Design and Fabrication

To understand the bandwidth and noise requirements for a multimode link, we developed a model to simulate a VCSEL operating in a 200 Gbps link. The simulations indicate that open eyes at 106.25 Gbd are achievable when the VCSEL −3 dB bandwidth exceeds 35 GHz and the RIN is less than −152 dB/Hz.

As simulations have suggested appropriate targets for a 200 Gbps VCSEL’s minimum bandwidth and maximum noise, a VCSEL that is capable of 200 Gbps modulation has been designed. Leveraging the previous generation of 100 Gbps PAM4 VCSEL design, the 200 Gbps VCSEL has been designed to simultaneously deliver improvements in bandwidth, reduction in the relative intensity noise, and improved thermal resistance to minimize the junction temperature rise. The VCSEL design has an oxide layer for carrier and photon confinement that is created by using a wet-lateral oxidation process after a trench etch, which exposes the high aluminum content oxidation layer. A multi-energy implant process is used to reduce the bond pad capacitance. The structure is similar to one described in an earlier publication [5].

3. Results

The fabricated 200 Gbps devices were characterized. Figure 3a shows the optical power and Figure 3b shows the voltage versus current for a typical VCSEL. At 9 mA, the optical power exceeds 3 mW and the voltage is about 2.5 V.

The VCSEL has been designed to optimize dynamic performance by (1) improving the differential gain, which determines the maximum resonance frequency and bandwidth; (2) improving carrier transport in the p-n diode; (3) optimizing the cavity detuning between the Fabry–Perot cavity resonance wavelength and the material gain peak, which defines the threshold current over temperature behavior; and (4) improving the thermal resistance, which reduces the junction temperature at operation bias.

The small signal modulation response of the fabricated 200 Gbps VCSEL was characterized by using direct probing on the wafer with a FormFactor/Cascade air coplanar probe, an Agilent E8364B PNA and an external high-speed photodiode with greater than 35 GHz. The S21 modulation response is shown in Figure 4 and indicates a −3 dB bandwidth, which is more than 35 GHz at 9 mA with a flattened/damped response. One of the challenges of improving the bandwidth of a directly modulated laser is the impairment from electrical parasitics, including the capacitance and resistance of the forward-biased p-n junction. By reducing the electrical parasitics, the VCSEL’s optical modulation bandwidth has a potential to reach beyond 45 GHz [1].

As the VCSEL noise contributes significantly to the total noise of the link, we have improved our design to minimize any power fluctuations due to mode beating, etc., to decrease the VCSEL noise. The VCSEL design optimization has enabled us to improve the relative intensity noise of the 200 Gbps PAM4 VCSEL to under −152 dB/Hz (Figure 5).

3.1. 200 Gbps (106 GBaud) PAM4 VCSEL Large-Signal Response

The large-signal performance of the 200 Gbps VCSEL has been characterized. A Keysight M8199B arbitrary waveform generator is used to generate a 106.25 GBd PAM4 PRBS13Q pattern with an extinction ratio of 2.2 dB, and a 7-tap Tx FIR is applied. The DC bias and AC modulation signals were combined using a bias-T with 65 GHz bandwidth, and an RF probe was used to couple the signal to the VCSEL bond pads. Light from the VCSEL was directed to the multimode fiber in a microscope optics setup. The optical waveform after the fiber transmission was characterized using a 200G multimode DCA-M developed by Keysight, using an adaptive 25-tap DCA FFE and a 53.1 GHz SIRC filter. Figure 6 shows clear open eyes with three different fibers, indicating that the combined bandwidth of the VCSEL and fibers are sufficient to support 200 Gbps operations. In Figure 6a–c, the eyes were taken with different effective modal bandwidth (EMB) fibers: (a) 2 m of OM4, (b) 30 m of standard OM4 fiber with an EMB of 4700 MHz·km and (c) 50 m of custom Corning-supplied fiber with an EMB of 7500 MHz·km. The use of the 7500 MHz·km fiber helps to extend the reach of the 200G link to 50 m. The skew of the sub-eyes arises from the nonlinear response of the directly modulated laser and the equalization provides sufficient gain at high frequencies to reduce ISI, resulting in a clear open eye. At the point of this review, the link distance for multi-mode 200 Gbps has not been formalized by the IEEE standards body.

3.2. Reliability

One critical aspect of achieving superior wear-out lifetime is minimizing the junction temperature. The junction temperature is a function of the electrical power dissipated in the VCSEL and the VCSEL’s thermal resistance. The increased current densities needed to achieve faster lasers also contribute to more joule heating (higher currents and/or higher series resistance) and higher thermal resistivity for smaller devices. To combat the increase in thermal resistance, the design of the 200 Gbps VCSEL includes DBRs with lower thermal impedance. Preliminary reliability tests have been performed on 200 Gbps PAM4 VCSELs. The devices were packaged in TO headers and stress at a constant bias of 9 mA at 100C. The devices are removed periodically for room temperature optical and electrical performance measurements. Standard reliability models and methodologies are applied for measurements and analysis [17,18]. Figure 7 shows the normalized output power of the VCSELs over time, at a use condition of 60C, 9 mA. In practical applications, the VCSEL substrate temperatures can be stabilized at 60C or lower with thermo-electric coolers (TEC). The gradual degradation observed over its life is similar to what is observed with 100 Gbps VCSEL. More extensive reliability testing to confirm the acceleration model and provide more substantial wear-out-life statistics is ongoing.

4. VCSEL Applications for AI Scale-Up Networking

VCSEL-based optical interconnects have widely supported short reach front-end networks since the 1 Gbps generation. These interconnects generally connect between the servers to top-of-rack switches, which in turn connect to the Internet core via additional fabric layers of switches. The IEEE 802.3 db standard ushered in 100 Gbps per lane applications and VCSELs have been used extensively in artificial intelligence (AI) scale-out networks. In scale-out networks, the XPUs (XPU is a generic term for accelerators, e.g., graphic or tensor processing unit), are connected to each other via high-speed links, such as 800 Gbps. By connecting large clusters with high-speed links, these AI clusters can function as one massive AI supercomputer, thereby increasing their capability for training and inference.

As AI cluster sizes continue to grow to meet the increasing demand for more compute, copper links that are commonly used in scale-up networks will be limited due to a single rack, due to high electrical insertion losses. Optical interconnects that convert the electrical signal from the host ASIC to optical signals before transmitting over optical fibers allow for longer reaches beyond a single rack.

In AI scale-up networks, XPUs are interconnected to support massive memory transfers between their HBMs. This facilitates efficient parallel computation. However, this requires large bandwidth connectivity across these XPUs. The Blackwell GPU generation would require a bandwidth of up to 28.8 Gbps. Direct attached copper (DAC) cables supporting 100 Gbps per SerDes channel have a reach of 4 to 5 m, limited by signal impairments such as jitter and insertion losses. The next generation of SerDes of 200 Gbps per lane (with higher insertion losses at Nyquist) will limit the reach of DAC further, to around 1 to 2 m. The reach can be extended by adding retimers to 7 m, but at the expense of cost and power consumption. As such, copper interconnects limit XPU connectivity to within a rack, or, at most, across two racks, thereby limiting the number of XPUs that can be connected within a single hop. Optical interconnects, on the other hand, can support reaches of 50 m and beyond with high data rates per channel [19]. This enables the simplification of networks via disaggregation.

Figure 8 shows an example of disaggregation of scale-up switches and XPU servers. The scale-up switches can be together in a dedicated switch rack that can be optimized for power and efficiency. Similarly, the XPU server racks can be further optimized for liquid cooling, power delivery, etc. With optical interconnects supporting reaches of up to 50 m and an all-to-all connectivity of 8 to 10 server racks within a single hop, the number of XPUs that can be connected within a single hop is only then limited by the radix of the switch.

To support scale-up networks using optical interconnects, several key parameters need to be considered: energy efficiency, reliability, escape bandwidth density and cost. Passive copper interconnects used in scale-up networks today have no active power dissipation. Optical interconnects have active laser components and require electrical–optical conversion. For a reasonable trade-off between power and reach, optical interconnects should have as high an energy efficiency as possible. The importance of reliability is critical for scale-up networks to maximize the utilization of the XPUs [20]. Unlike scale-out networks, where re-transmission can be frequent, scale-up networks require the interconnects to be stable and reliable to minimize the frequency of checkpoint restoration. As XPU bandwidths increase to 50 Tbps and beyond, dense interconnects are needed to work in limited shoreline widths. A value of greater than 0.6 Tbps/mm escape bandwidth density is desired to support these connections. Lastly, the cost of the optical interconnects should be reasonably low and comparable to copper interconnects. In the next section, a VCSEL near-package optics (NPO) concept is proposed that meets the above criteria.

4.1. Near-Package Optics (NPO) Concept Proposal

A 3.2 Tbps VCSEL-based NPO engine concept is proposed (Figure 9). In this self-contained package, there are four 1 × 8 VCSEL arrays and corresponding VCSEL driver ICs, four 1 × 8 PD arrays and corresponding trans-impedance amplifier (TIA) ICs, and a microcontroller unit (MCU). Each channel supports a data rate of between 100 Gbps and 128 Gbps, resulting in 3.2 Tbps–4.1 Tbps total bandwidth. To support these high data rates, the Nyquist frequency of the optical components needs to be greater than 32 GHz. Figure 10 shows the 100G VCSEL meeting this requirement at a high substrate temperature of 75 deg C.

The transmit and receive parts can be packaged separately as individual engines. The VCSEL and PD arrays can be wirebonded to the engine substrate and light can be coupled vertically to multi-mode optical fibers via cost-effective plastic array lenses.

High power efficiencies can be achieved with CMOS-based VCSEL drivers and TIAs. The total power efficiency, including the VCSELs, is approximately 1 pJ/bit. This translates to less than 4 W per NPO device. This is far more efficient than silicon photonics optical interconnects which are in the range of 5 pJ/bit to 10 pJ/bit [21]. One of the contributions of the higher power consumption of these silicon photonics interconnects is the higher drive currents of single-mode DFB lasers, which are needed to have sufficient optical power launching into the silicon modulators.

Over one hundred million 50G/100G VCSEL channels have been shipped, translating to over 5 trillion device service hours in the field, with no field returns related to VCSEL reliability. This equates to a FIT rate of less than 0.1 for the VCSEL devices, thereby contributing to an insignificant reliability risk to the entire NPO device. Further analysis would be needed to assess the overall FIT rates at the NPO device level. However, it is expected that with CMOS processes and mature multi-mode manufacturing capabilities, the FIT rates would be comparable to active copper interconnects.

Figure 11 shows an example of the placement of 18 VCSEL NPO engines to support up to 73.7 Tbps of XPU escape bandwidth with a single beachfront. The engines are placed in a 3 × 6 configuration, with the width of each row being approximately 120 mm, resulting in an escape bandwidth density of >0.6 Tbps/mm. The optical fibers can be routed to the front panel or backplane of the XPU server. Additional swizzling of the fibers can be made in the server or a fiber shuffle box located at the top of the server rack, allowing for flexibility in optical connectivity, depending on the application needs.

A major cost contribution in PAM4-based optical interconnects is the digital signal processing (DSP) IC. With short links and thereby low electrical insertion losses, NPO devices do not need to have DSPs to correct for signal impairments. Compared to the standard optical pluggables, with the smaller form factor (19 mm × 19 mm) of an NPO for the same speed, material costs can be further reduced. Optical lens design is less complex with one-dimensional VCSEL or PD arrays compared to multi-dimensional arrays, thereby keeping manufacturing costs down. At high volumes, the cost ($/Gbps) can be comparable to active copper cables.

4.2. NPO Design Considerations

NPO links differ from optical links in standards-based links, e.g., IEEE 802.3 db, Infiniband XDR, whereby the electrical insertion loss budget depends on the capability of the XPU SerDes. These SerDes have different data rates and numbers of taps for pre-emphasis or equalization. However, the NPO has the advantage of being close to the SerDes, which limits the maximum insertion loss. As an example, with the placement of 18 engines, the longest electrical trace length is about 65 mm from the SerDes (Figure 12 and

Table 1. Electrical channel loss breakdown estimates at 106 Gbps and 128 Gbps from XPU to NPO. Total channel loss highlighted in bold.

Channel Loss Estimation at Nyquist Frequency	106G (Nyquist 26.6 GHz)	128G (Nyquist 32.0 GHz)
GPU Substrate Loss (5 mm)	0.65 dB	0.70 dB
Host PCB Loss (60 mm)	5.40 dB	6.00 dB
BGA	0.04 dB	0.04 dB
Connector	0.50 dB	0.50 dB
Cu Pillar (×2)	0.04 dB	0.04 dB
Total Channel Loss	6.6 dB	7.3 dB

). With low loss materials, an electrical channel insertion loss of about 7 dB (bump to bump) can be achieved at 106 Gbps. The closest engine has a short electrical trace length of about 15 mm from the SerDes, resulting in an insertion loss of about 2 dB. Compared to the IEEE standards of between 8 dB and 16 dB loss (BGA to Driver/TIA IC bump), a lower value and a smaller variation in the insertion loss between the XPU and NPO places less demand on the SerDes capabilities.

5. Discussion

The characterization results of the fabricated 200 Gbps PAM4 VCSELs demonstrate excellent performance, validating the key design optimizations that are implemented to meet the demands of high-speed data transmission. The successful dynamic performance is a direct result of several design improvements, specifically targeting enhanced differential gain, optimized carrier transport, precise cavity detuning, and reduced thermal resistance. The small signal modulation response confirms the device’s high-speed capability, exhibiting a −3 dB bandwidth that is greater than 35 GHz, along with a flattened and damped response that is characteristic of a well-optimized system. Furthermore, the mitigation of VCSEL noise was achieved, resulting in a relative intensity noise (RIN) of less than −152 dB/Hz at the operating bias, which is crucial for reducing the total noise in the communication link.

In large-signal operation, the VCSEL successfully demonstrates clear open-eye diagrams. This performance was maintained across various fiber lengths and types, notably extending the reach to 50 m with a custom Corning fiber (EMB 7500 MHz·km). Preliminary reliability testing has shown a gradual degradation trend that is similar to the previous generation of 100 Gbps VCSELs, suggesting a robust design. The focus on minimizing the junction temperature by using DBRs with lower thermal impedance is a critical factor for achieving a superior wear-out lifetime. More extensive reliability testing is currently underway to fully confirm the acceleration model and provide comprehensive wear-out-life statistics. These results collectively indicate that the optimized 200 Gbps PAM4 VCSEL is a highly promising component for next-generation, high-capacity optical interconnects.

A VCSEL-based near-package optics (NPO) solution is presented as a critical enabler for next-generation AI scale-up networks, effectively addressing the limitations faced by traditional copper interconnects. The proposed 3.2 Tbps VCSEL-based NPO engine supports significantly longer reaches (up to 50 m and beyond), facilitating network disaggregation and all-to-all connectivity across multiple server racks, ultimately enabling a larger number of XPUs to be connected within a single hop.

Crucially, the NPO solution meets the stringent demands of AI scale-up environments across key metrics: energy efficiency, reliability, escape bandwidth density and cost. A high-power efficiency of approximately 1 pJ/bit can be achieved with a CMOS laser driver and TIAs. Leveraging mature manufacturing, the VCSEL component exhibits an extremely low FIT rate (less than 0.1), suggesting an insignificant reliability risk to the overall NPO device. The proposed 3 × 6 placement of 18 engines supports a massive escape bandwidth of up to 73.7 Tbps, yielding a density of 0.6 Tbps/mm, which is essential for high-bandwidth XPU connectivity in limited shoreline widths. By eliminating the need for complex digital signal processing (DSP) ICs, due to short internal electrical links, and utilizing a small form factor (19 mm × 19 mm), the NPO’s cost ($/Gbps) is expected to be comparable to active copper cables at high volumes.

Furthermore, the proximity of the NPO to the SerDes greatly limits the maximum electrical insertion loss to a narrow range of 2 dB to 7 dB at 106 Gbps: a significant advantage over the 8 dB to 16 dB loss seen in standards-based optical pluggables. This lower and more stable insertion loss places considerably less demand on the XPU SerDes capabilities, simplifying the overall system design.

Future work should focus on further assessing the overall FIT rates at the NPO device level to fully validate the reliability model and establish the NPO as a robust and scalable alternative to copper for the increasing bandwidth demands of AI scale-up networks.

6. Conclusions

In this paper, we discussed the vertical cavity surface emitting laser (VCSEL) bandwidth and noise performance needed to support 106 Gbd line rates with PAM4 modulation for 200 Gbps per lane multimode optical links. A −3 dB bandwidth of greater than 35 GHz and a RIN of less than −152 dB/Hz were demonstrated. No uncorrectable errors were observed over 50 m of OM4 fiber, demonstrating good link stability. VCSEL device performance and the associated wear-out life are presented. This new VCSEL design will enable the next generation of 212.5 Gbps per channel commercial products. Leveraging good device reliability and low power consumption of VCSEL-based links, a novel VCSEL near-packaged optics (NPO) concept is proposed for optical interconnects in AI scale-up network applications. Optical interconnects allow for longer reaches compared to copper interconnects, which facilitate larger AI clusters with network disaggregation. A VCSEL NPO concept at ~1 pJ/bit energy efficiency is also proposed to meet AI scale-up networking requirements in terms of energy efficiency, escape bandwidth density, reliability and cost.