Current Source AC-Side Clamped Inverter for Leakage Current Reduction in Grid-Connected PV System

Abstract

For the grid-connected photovoltaic inverters, the switching-frequency common-mode voltage brings the leakage current, which should be eliminated. So far, many kinds of single-phase inverters have been published for this purpose, but most of them are the conventional voltage-type ones, which have the disadvantages of poor reliability due to the DC-link electrolytic capacitor and the risk of short-through of the bridge switches. To solve this technical issue, a novel current source inverter with AC-side clamping is proposed to mitigate the switching-frequency common-mode voltage. Meanwhile, a novel modulation method is proposed for the new single-phase inverter to achieve low-frequency operation of the main switches, which reduces the switching losses. Finally, the proposed method is implemented on the TMS320F28335DSP + XC6SLX9FPGA digital hardware platform. Also, the performance comparisons are done with the traditional solution. The results prove the proposed solution.

1. Introduction

Photovoltaic (PV) power generation is one of the ways to effectively use energy. Through photovoltaic panels to obtain energy, photovoltaic systems can provide green sustainable solutions [1,2]. In general, energy can be obtained from photovoltaic panels by grid connection of photovoltaic inverters or by connecting transformers. However, the transformer is relatively heavy, sizable, and costly, with undesirable power loss problems. Therefore, the transformerless PV inverters are promising and attractive in industrial and academic fields [3,4,5,6,7]. However, when the transformerless PV inverter is connected to the grid, there are still many technical challenges to be solved, such as the leakage current or ground current. Without the transformer isolation, the electrical connection exists between the photovoltaic panel and the grid, and a leakage current will be generated on the parasitic capacitance between the photovoltaic panel and the ground. Leakage currents can adversely affect grid current, personal safety and electro-magnetic interference issues. So, the German standard VDE 0126-1-1 defines that the PV system should be off from the grid when the leakage current exceeds 300 mA.

To solve the above problems, many kinds of topologies have been published, such as Heric, H6, oH5, H5 [8,9,10,11]. In theory, a constant common-mode voltage would be achieved with the above topologies. In fact, due to the influence of the switch junction capacitance, the switching common-mode voltage changes with high frequency. Consequently, the leakage current cannot be completely eliminated. Nevertheless, most topologies are proposed from the perspective of voltage-type inverters. In a voltage source inverter, the DC-side electrolytic capacitor reduces the reliability and life of the inverter system. Moreover, the voltage source inverter has a risk of short-through, which leads to the reliability issue. In addition, the current source inverter has a unique short-circuit operation capability, which improves the reliability of the system. Aside from that, the DC-link of the current source inverter uses an inductor instead of an electrolytic capacitor, which can be designed to work at high temperatures [12,13,14,15]. The current-type inverters, as a matter of fact, have been applied in photovoltaic systems over the past few decades [16,17,18,19,20,21,22].

However, due to the switching-frequency common-mode voltage, the leakage current of the conventional current-source four-switch inverter is large. This characteristic limits the application of conventional current source inverters in transformerless photovoltaic systems. Inspired by the bypass-type voltage source inverter topology [23], this paper proposes a novel AC-side clamped current-source inverter topology, which effectively suppresses the switching-frequency common-mode voltage, so as to reduce the leakage current. At the same time, for the new inverter, a new modulation for reducing the switching loss is proposed. In addition, the proposal is proven by the experiment results.

2. Traditional Current Source Inverter

Figure 1 is a schematic of the conventional current-source inverter circuit. Where, L_dc1 and L_dc2 are DC-side inductors, S₁–S₄ are IGBTs (Insulated Gate Bipolar Transistor), C_f is the AC-side filter capacitor, v_g is the AC-side voltage, and C_PV is the parasitic capacitance between the PV array and the ground. The voltage change across the parasitic capacitance C_PV will cause a leakage current, which will affect the grid current.

Figure 1. Conventional current-source inverter.

In order to understand the factors affecting the leakage current, a common-mode loop model, as shown in Figure 2, is established. Where, V_CM represents the common-mode voltage (CMV), and Z is the equivalent impedance of the common-mode loop.

$$V_{CM}=\frac{V_{PO}+V_{NO}}{2}$$

(1)

$$Z=\frac{s{L}_{dc1}{L}_{dc2}}{L_{dc1}+L_{dc2}}$$

(2)

$$i_{leakage}=2C_{PV}\frac{d{V}_{CPV}}{dt}$$

(3)

$$V_{CPV}=\frac{1}{2s{C}_{PV}Z+1}{V}_{CM}$$

(4)

where, V_CPV represents the voltage across the parasitic capacitance 2C_PV. According to Equations (3) and (4),

$$I_{leakage}(s)=\frac{2s{C}_{PV}}{2s{C}_{PV}Z+1}{V}_{CM}$$

(5)

Figure 2. Common-mode model.

According to Equation (2) and Equations (3)–(5), the leakage current I_leakage is dependent on the equivalent common-mode impedance and the rate of the common-mode voltage change. Therefore, reducing the leakage current can be considered from two points, one is to increase the common-mode loop impedance, and the other is to reduce the rate of the common-mode voltage change or to maintain the common-mode voltage constant.

Conventional current-source inverters have four switching states, as shown in Table 1. As shown in Figure 3, the driving signal waveforms of S₁ and S₃ are changed by low frequency, and the driving signals of S₂ and S₄ are changed at a high frequency.

Table 1. Current space vectors, switching states and common-mode voltage (CMV).

Current Vectors	Switching States				CMV
	S1	S2	S3	S4
I1	1	0	0	1	0.5vg
I2	1	1	0	0	vg
I3	0	1	1	0	0.5vg
I4	0	0	1	1	0

Figure 3. Gating signals of current-source inverter.

As switch S₁ and the switch S₄ are turned on, the common-mode voltage can be derived according to Equation (1):

$$V_{CM}=\frac{V_{PO}+V_{NO}}{2}=\frac{V_{AO}+V_{BO}}{2}=\frac{v_g}{2}$$

(6)

where, V_PO represents the potential of P with respect to O, and V_NO represents the potential of N with respect to O.

When the switch S₁ and the switch S₂ are turned on, the common-mode voltage is:

$$V_{CM}=\frac{V_{PO}+V_{NO}}{2}=V_{AO}=v_g$$

(7)

As the switch S₂ and the switch S₃ are turned on, the common-mode voltage is:

$$V_{CM}=\frac{V_{PO}+V_{NO}}{2}=\frac{V_{BO}+V_{AO}}{2}=\frac{v_g}{2}$$

(8)

When the switch S₃ and the switch S₄ are turned on, the common mode voltage is:

$$V_{CM}=\frac{V_{PO}+V_{NO}}{2}=V_{BO}=0$$

(9)

In summary, the switching-frequency common-mode voltage in the system leads to serious leakage current problems of the current-type inverter. In order to effectively suppress the leakage current, this paper will propose a new topology in the next section, which can eliminate the switching common-mode voltage variation for the leakage current attenuation.

3. New Current-Source Inverter

This section introduces a new current-source inverter topology that can eliminate high-frequency common-mode voltage variation from a topological perspective. As shown in Figure 4, a voltage source DC-bypass inverter is proposed in Reference [23]. It uses the diode to clamp the unchancommon-mode voltage unchanged at V_dc/2, and thus, the leakage current can be suppressed. The corresponding current-type topology is obtained, as illustrated in Figure 5.

Figure 4. Voltage source inverter with DC-side clamping.

Figure 5. New current-source inverter with AC-side clamping.

According to Table 1, the common-mode voltage depends on the grid voltage, and the common-mode voltage variation is from 0 to v_g. For eliminating the high-frequency common-mode voltage, the DC-side positive bus P and the negative bus N are clamped at the midpoint of the AC-side filter capacitors during the freewheeling period. According to Equation (1), the common-mode voltage is v_g/2 in the freewheeling cycle.

$$V_{CM}=\frac{V_{PO}+V_{NO}}{2}=\frac{v_g}{2}$$

(10)

During the freewheeling period, the switch S₅ and the switch S₆ are on to establish a freewheeling path for the DC-side current. The switching states in the active state are the same as that of the conventional current-source inverter. During the half-positive cycle, the switch S₁ and the switch S₄ are turned on. In the half-negative cycle, the switch S₂ and the switch S₃ are on. The new current-source inverter switching states and corresponding common-mode voltages are given in Table 2.

Table 2. Current space vectors, switch states and CMV.

Current Vectors	Switching States						CMV
	S1	S2	S3	S4	S5	S6
I1	1	0	0	1	0	0	0.5vg
I3	0	1	1	0	0	0	0.5vg
I0	0	0	0	0	1	1	0.5vg

It can be seen from Table 2 that the new current-source inverter has three switching states, and the common-mode voltages corresponding to each switching state are the same, which are 0.5v_g, and the common-mode voltage frequency is consistent with the fundamental frequency. Since the frequency of the grid voltage v_g is smaller than the high switching frequency, the influence of the fundamental-frequency voltage on the switching frequency common-mode characteristics can be ignored. According to Equations (3)–(5), the proposed method eliminates the switching frequency common-mode voltage variation, so that the leakage current is effectively suppressed.

The driving signal waveform of the proposed inverter is shown in Figure 6. The switches S₁–S₆ are high-frequency changes and the switching loss is increased. To solve this problem, a novel modulation method for reducing the switching loss based on the characteristics of the new topology is proposed. Taking the half-positive cycle operating state as an example, the active state I₁ and the zero state I₀ alternately operate. Figure 7 and Figure 8 are circuit diagrams of the system operating in the active state I₁ and the zero state I₀, respectively.

Figure 6. Gating signal of new current-source inverter.

Figure 7. Schematic of the active state I₁.

Figure 8. Schematic with the active state I₀.

According to Figure 8, when the system operates in the zero state, the potential at point A is v_g, the potential at point B is 0, the point P and the point N are clamped at point M, and the potential at point M is v_g/2. Therefore, in the zero state, if the switch S₁ and the switch S₄ are in the on state, the diodes D₁ and D₄ are reversely turned off, and the upper arm and the lower arm are still in the off state, and the circuit is as shown in Figure 9. The switch S₁ and the switch S₄ can always be in the on state during the half-positive cycle. In a similar manner, for the half-negative cycle, the switch S₂ and the switch S₃ can always be in the on state. The switching states of the new modulation method can be obtained, as shown in Table 3. Figure 10 shows the gating signals’ waveform when using the new modulation method. It can be seen that the switches S₁–S₄ vary by low frequency, and the switching loss is reduced.

Figure 9. Schematic under new modulation method.

Table 3. Current space vectors, switching states and CMV.

Current Vectors	Switching States						CMV
	S1	S2	S3	S4	S5	S6
I1	1	0	0	1	0	0	0.5vg
I01	1	0	0	1	1	1	0.5vg
I3	0	1	1	0	0	0	0.5vg
I03	0	1	1	0	1	1	0.5vg

Figure 10. Gating signals with the new modulation.

4. Results

In this section, a system experiment setup was built, and the proposal was compared against the traditional method. The algorithm is realized by the DSP (TMS320F28335) and FPGA (Xilinx XC6SLX9). The experimental parameters are shown in Table 4. Figure 11 shows the control diagram of the proposal. The phase angle θ is detected to generate the reference current. The output m of the PR (Proportional Resonant) regulator is used as the input of the new modulation method. The new modulation method judges the positive or negative of m and selects the corresponding switching sequence. The specific switching sequence selection is shown in Figure 12, where T_s represents the switching period.

Table 4. Experimental parameters.

Parameters	Values
Switching frequency	10 kHz
AC-side filter capacitors (Cf1 Cf2)	18.8 μF
DC-side inductances (Ldc1 Ldc2)	5 mH
Parasitic capacitance (Cpv)	75 nF
DC-side current	8 A
DC-side voltage	200 V
AC-side current	6 A
AC-side voltage	110 V (RMS)

Figure 11. System control block diagram.

Figure 12. Switching sequence selection for new modulation method.

The experimental results for the conventional current-type inverter are shown in Figure 13. The output current I_inv is unipolar, and the grid current I_g is sinusoidal. Figure 13b shows the voltages V_PO, V_NO and the common-mode voltage V_CM. The leakage current I_leakage waveform is shown in Figure 13c, and the maximum leakage current is 2 A. The switching-frequency variation of the common-mode voltage causes the leakage current to far exceed the 300 mA. As shown in Figure 13d, for the gating signal waveforms of the switches S₁–S₄, the switch S₁ and the switch S₃ operate at the power frequency, and the switch S₂ and the switch S₄ operate at a high frequency.

Figure 13. Results with conventional current-type inverter. (a) Output current I_inv, common-mode voltage V_CM, grid current I_g; (b) V_PO, V_NO, common-mode voltage V_CM; (c) Leakage current I_leakage, common-mode voltage V_CM; (d) Switches S₁–S₄ gating signal waveforms.

The output current I_inv and the grid current I_g are shown in Figure 14a. From Figure 14d, the switches S₁-S₄ operate in power frequency, which reduces the switching loss. Figure 14b is the experimental result of the voltages V_PO, V_NO and the common-mode voltage V_CM. The common-mode voltage is the half-grid voltage, ignoring the effect of the fundamental-frequency component of the common-mode voltage on the high-frequency common-mode behavior. According to Equation (5), the leakage current is able to be attenuated. The experimental waveform of the leakage current I_leakage is shown in Figure 14c. The maximum value of the leakage current is 144 mA, which meets the standard and is less than 300 mA, which is satisfactory in terms of the VDE-0126-1-1.

Figure 14. Results with new current-source inverter. (a) Output current I_inv, common-mode voltage V_CM, grid current I_g; (b) V_PO, V_NO, common-mode voltage V_CM; (c) Leakage current I_leakage, common-mode voltage V_CM; (d) Switches S₁–S₆ gating signal waveforms.

5. Conclusions

In this paper, a novel current-source inverter was proposed. Through the principle analysis and experimental research, the following conclusions were drawn. (1) The high-frequency variation of the common-mode voltage of the conventional current-source inverter cannot effectively suppress the leakage current. (2) The topology proposed in this paper can effectively eliminate the high-frequency common-mode voltage of the system, thus effectively suppressing the system leakage current and satisfying the VDE-0126-1-1 standard.