Next Article in Journal
Probabilistic Evaluation and Improvement Measures of Power Supply Capability Considering Massive EV Integration
Next Article in Special Issue
System Level Optimization for High-Speed SerDes: Background and the Road Towards Machine Learning Assisted Design Frameworks
Previous Article in Journal
Design of a Wide-Band Voltage-Controlled Ring Oscillator Implemented in 180 nm CMOS Technology
Previous Article in Special Issue
K-Band Low Phase Noise VCO Based on Q-Boosted Switched Inductor

Electronics 2019, 8(10), 1157; https://doi.org/10.3390/electronics8101157

Article
High-CMRR Low-Noise Fully Integrated Front-End for EEG Acquisition Systems
1
Polystim Neurotech. Lab., Department of Electrical Engineering, Polytechnique Montreal, Montreal, QC H3T 1J4, Canada
2
Department of Microelectronics, Electronics Research Institute, Cairo 12622, Egypt
3
School of Engineering, Westlake University, 18 Shilongshan Street, Hangzhou 310024, China
4
Westlake Institute of Advanced Study, Hangzhou 310024, China
*
Author to whom correspondence should be addressed.
Received: 22 September 2019 / Accepted: 7 October 2019 / Published: 12 October 2019

Abstract

:
We present in this paper a fully integrated low-noise high common-mode rejection ratio (CMRR) logarithmic programmable gain amplifier (LPGA) and chopped LPGA circuits for EEG acquisition systems. The proposed LPGA is based on a rail-to-rail true logarithmic amplifier (TLA) stage. The high CMRR achieved in this work is a result of cascading three amplification stages to construct the LPGA in addition to the lower common-mode gain of the proposed logarithmic amplification topology. In addition, the 1 / f noise and the inherent DC offset voltage of the input transistors are reduced using a chopper stabilization technique. The CMOS 180 nm standard technology is used to implement the circuits. Experimental results for the integrated LPGA show a CMRR of 140 dB, a differential gain of 37 dB, an input-referred noise of 0.754 μ Vrms, a 189 μ W power consumption from 1.8 V power supply and occupies an active area of 0.4 mm 2 .
Keywords:
EEG acquisition system; front-end amplifier; high CMRR; 1/f noise; logarithmic programmable gain amplifier; chopper stabilization technique

1. Introduction

The electroencephalogram (EEG) experimental and clinical monitoring technique is used for long-term monitoring of the brain’s electrical activity. EEG is a non-invasive and painless diagnostic test, which allows measuring the electrical activity of the brain by simply placing several electrodes on the head (scalp) around the brain. The potential differences measured from sets of two electrodes are converted into waveforms. These signals are used to evaluate the brain disorders in epileptic patients representing our interest. Recently, there was an increasing demand of miniaturized biopotential acquisition systems. These systems are lightweight, portable, do not hinder patient’s mobility, and are comfortable to the patient during the monitoring. The EEG signals are difficult to be measured due to their extremely weak amplitude, in the range of 1–160 μ VPP, and their limited band to a very low-frequency range from 0.1 to 100 Hz. Therefore, the EEG acquisition systems are susceptible to ambient noise (50/60 Hz common-mode interference signal coupled to human body from the mains), amplifier flicker noise ( 1 / f ), and DC offset, as well as to problems of electrode DC offset generated at the skin-electrode interface and between electrodes. This can lead to the saturation and reduction of the CMRR of the readout front-end that defines the quality of the extracted signal [1]. To extract a high-quality EEG signal under the above-mentioned conditions, low-power, low-noise, and high-CMRR and PSRR readout front-end are needed. In the remaining parts of the paper, we introduce the state-of-the-art on the front-ends dedicated to EEG signal acquisition. The proposed EEG acquisition channel is presented in Section 3, followed by a detailed explanation of the design and implementation of the LPGA. Section 4 shows the measurement results of the LPGA prototype integrated in 180 nm CMOS process. Conclusions and future work are given in Section 5.

2. Background and Previous Work

The amplifier in [2] consists of a low-noise closed loop amplifier (LNA) including a chopper stabilization module and a GM-C servo-loop to cancel offset current. Resistances and capacitances components are used off-chip. However, these off-chip components and the transconductor of the servo-loop increase the overall noise of the instrumentation amplifier. Furthermore, the amplifier provides low CMRR (60 dB) even at higher input-impedance and low-voltages operation. This is because of performing the input modulation at the op-amp virtual ground node. Additionally, mismatch in the input capacitors can convert common-mode input signals to differential-mode noise. Low-noise, low-offset, and large-output voltage swing amplifier design is introduced in [3]. It consists of AC coupled chopper folded-cascode amplifier combined with an input-impedance boosting loop and two offset trimming loops based on auxiliary current DACs for input offset and residual offset cancelation. A back-end common-mode feedback (CMFB) circuit is designed to improve the CMRR of the active electrode system. However, the CMRR of the CMFB circuit is limited by the electrode-tissue contact impedance mismatch. In addition, the use of these many active circuits (to solve offsets, ripple, input impedance problems and CMRR enhancement) reduces the SNR and increases the integration area. Recently, AC-coupled non-inverting chopped two-stage IA followed by a transconductance amplifier (TA) is reported [4]. The input pair of the IA consists of NMOS and PMOS differential pairs connected in parallel, which reduces the thermal noise of the input-referred voltage-density and doubles the input transconductance of the core amplifier without consuming extra bias current. Besides, the above design provides voltage gain, high input-impedance, low noise, and the ability to reject large electrode offset. However, the main drawback of the presented IA topology is the lack of CMFB circuit, which gives in the common-mode output variation of the TA. This results in a high-output distortion, low CMRR and PSRR, and high offset voltage. Moreover, the use of two amplifiers increases the IA noise. To adequately amplify the low EEG signals with a dynamic range of 80 dB and compress the largest ones created during the epileptic crises, we present in this paper a low-noise and high-CMRR rail-to-rail logarithmic programmable gain amplifier (LPGA) as well as a chopped LPGA (CLPGA) dedicated to EEG acquisition channels/systems.

3. The Proposed System

Figure 1 shows the architecture of EEG acquisition system, where the proposed fully integrated CLPGA is used as pre-amplification stage [5]. A high-pass filter is employed to cut off all received signals with frequencies lower than 0.1 Hz. In addition, a high resolution (up to 14 bits) delta-sigma modulator is used to digitize the amplified signal. This high-resolution modulator maximizes the number of available quantization steps, while reducing quantization noise error and increasing signal-to-noise ratio (SNR ≥ 100 dB). In addition, the proposed design involves a gain-programming logic to fit the EEG signal into ADC’s input dynamic range. The 1 / f noise is reduced in the proposed CLPGA by using large size PMOS and NMOS input pair transistors and applying a chopper stabilization (CS) technique [6,7]. Chopper 1, which is based on CMOS switches, is used to transpose the EEG signal to 1 kHz chopper frequency to up-modulate the 1 / f noise to a higher frequency further away from the signal band [8]. Chopper 2 acts as demodulator to place back the amplified EEG signal on its original band. Figure 2a shows the circuit implementation for Choppers 1 and 2, where dummy transistors have been added to reduce the generated spikes from the chopping process (due to charge injection from the used switches). In addition, a chopper spike filter shown in Figure 2b has been used to cancel these spike voltages. Our work in this paper focuses only on the design, implementation, and experimentally validation of the LPGA circuit.

3.1. LPGA

Figure 3 shows the block diagram of the proposed rail-to-rail LPGA. It is based on a differential topology of true logarithmic amplifier (TLA), where the phase shift or group delay does not vary with the input signal level. The LPGA consists of three cascading rail-to-rail dual-gain stages. To achieve high CMRR, low noise, and low offset in a wide-input common-mode range, each stage is composed of chopper-stabilized parallel N and P type modules, where their differential outputs are added together to perform logarithmic function. Depending on the input common-mode range, only one chopper-stabilized module is active at any time. The N type module is active when the input common-mode voltage is from 0 V to VDD. P type module is active when the input common-mode voltage is from VSS to 0 V. The gain of each stage consists of two parallel amplifications: limiting gain amplifier (LGA) and unity gain amplifier (UGA). LGA treats the signals that have the amplitude lower than a threshold input voltage (ViL) and limits the output voltage (VoL) when the amplitude of the input signal is higher than or equal to ViL by the following equations:
V out = AV in , V in < V iL
V out = V oL , V in V iL
where A, ViL, and VoL are the gain of the LGA, the input limiting voltage, and the output limiting voltage, respectively. Usually, for the UGA, V out = V in . Thus, the output voltage of one dual-gain stage is given by:
V out = ( A + 1 ) V in , V in < V iL
V out = V in + V oL , V in V iL
where A + 1 is the linear part of a dual-gain stage. Consequently, the linear gain of the cascaded three stages is equal to ( A + 1 ) 3 . The output voltage characteristic consists of a series of straight lines with breaking points indicating each limiting amplifier stage. Assuming n cascaded dual-gain stages are used and knowing that the limitation comes from the mth stage towards the ( m 1 ) th stage of the TLA, the output of the mth stage (Vom) of the TLA is given by:
V om = V oL 1 + 1 A
The expected signal passed through n−m limiting stages, Equation (5) applied for each stage, gives the following:
V out = ( n m ) V oL + 1 + 1 A V oL = V oL [ n + 1 / A ( m 1 ) ]
The input of the m-th stage (Vin,m) at the beginning of the limitation is amplified by m − 1 stages and given by:
V in , m = V oL A = V in [ ( A + 1 ) ] m 1
m 1 = log ( A + 1 ) V oL AV in
Substituting Equation (6) into Equation (4), we find
V out = V oL n + 1 / A + log ( A + 1 ) AV in V oL
Equation (9) demonstrates that the output signals follow the suited logarithmic variation. Given that the linear gain and the precision of the LGA are determined by all involved stages, 14.67 dB gain by one stage is required. Therefore, three stages are needed to obtain a 44 dB gain by the TLA. Each dual-gain stage is based on a differential circuit used to reject the input noise coming from the previous stages. Figure 4 shows the circuit implementation of the differential rail-to-rail topology for one dual-gain stage. Both LGA and UGA circuits share M3 and M4 transistors, which are used to produce the gain limitation or blockage of differential pairs composed of M1 and M2. The UGA stage, defined by M7 and M8 transistors, is working in the triode region as resistances. The ratio of bias currents In and Intotal, Ip, and Iptotal depends on the number of stages cascaded in order to get the desired dynamic range. The identical transistors M3 and M4 determine the limiting gain (2A), which dominates the total gain of one dual-gain stage 2(A + 1). The sizes of these transistors are chosen to be large to get the adequate gain for each stage. M1 and M2 constitute the input differential pair of the LGA, while M3 and M4 represent the active load, and M5 and M6 form the input differential pair of the low transconductance UGA. Output currents of both LGA and UGA are added together; Ik1 is the LGA bias current and Ik2 is the UGA bias current. The LGA and UGA gains are linear and the transistors of their input differential pairs work in the saturation region when the amplitude of input signal is very low. However, when the amplitude of the input signal is large, one transistor of the differential pair will be off and the bias current will be drained through the other transistor. The output of LGA will be limited by the drain-source saturation voltage of transistors M3 and M4. At breaking point:
V in + = 2 I k 1 K 1 + V t = 2 I k 3 K 9 + V t , V in = V t
V i n = V i n + V i n = 2 I k 1 K 1 = 2 I k 3 K 9
where K i corresponds to the transconductance’s constant of transistor M i and V t is the threshold voltage. Therefore, VIL can be set by designing Ik1 and Ik3 through the aspect ratio of M3, M4, M11, and M12.
Rail-to-rail output stage (Buffer B), which is realized by class-AB configuration, is connected at the output of the last stage of the LPGA to achieve low-output distortion and therefore getting the maximum SNR at the output [9].

3.1.1. CMRR

The CMRR is the important critical parameter of the amplifier to be enhanced to reject the mains interference. Usually, to improve the CMRR of the EEG channel, a driven right leg (RLD) circuit is used to feed a common-mode signal to the patient body to cancel the interference [10]. This method effectively reduces the common-mode gain and increases the CMRR. However, this kind of loop is difficult to stabilize due to the uncontrollable electrode-tissue impedance of the dry electrodes. To solve this problem, a digital RLD circuit has been presented in [11] to provide a high common-mode signal reduction at power line frequency. However, this circuit requires additional modules such as notch filter, digital signal processing and digital-to-analog converter, and hence greater power dissipation. Another technique to improve CMRR is the use of common-mode feedback [3], i.e., to feed the common-mode signal back to the input of each preamplifier. However, the feedback loop requires a summing amplifier and large compensation-capacitors for common-mode extraction and stability. This results in large silicon area. In this work, the presented LPGA is formed by cascading three amplification stages, where the CMRR (dB) of the overall LPGA can be expressed by [12]:
( CMRR LPGA ) dB = ( CMRR 1 st ) dB + ( CMRR 2 nd ) dB + ( CMRR 3 rd ) dB
Thus, a very-high CMRR can be achieved. In addition, the PSRR will be increased since it is directly related to the gain [12]. To further improve the CMRR, the common-mode gain ( A cm ) of the logarithmic amplification topology must perform very-high attenuation on all common-mode signals applied at the input of the LPGA module.
To calculate the Acm of the perfectly balanced differential amplifier shown in Figure 4, its small-signal equivalent half circuit is extracted, where we ignored the body-effect transconductance (gmb) [13]. However, as this perfectly balanced amplifier is symmetric, the calculation is greatly simplified by using the superposition theorem on the circuit shown in Figure 5. Firstly, we found the responses to the small signal currents in term of the pure common-mode input Vic of each branch, and adding all currents at summation node A to obtain the total common-mode gain AcmTotal, i.e., AcmTotal = Voc/Vic. For the four branches of the circuit of Figure 5 and considering our optimization of this circuit, the values of rds1, rds2, rds5, and rds6 are very small and for ideal case gm1 = gm5, gm2 = gm6, and gm4 = gm7. Thus, the drain currents of each branch can be expressed by:
I d 1 = V ic g m 1 1 + 2 R tail g m 1
I d 2 = V ic g m 2 1 + g m 2 r ds 4 2 R tail r ds 4 g m 2 g m 4
I d 5 = V ic g m 5 1 + 2 R tail g m 5
I d 6 = V ic g m 6 1 + g m 6 r ds 7 2 R tail r ds 7 g m 6 g m 7
where Ids1 = −Ids5 and Ids2 = −Ids6, thus Ids1 + Ids2 = −(Ids5 + Ids6). Consequently, the total common-mode gain at the summation node A can be expressed as
A cmTotal = A cm 1 + A cm 2 = 2 g m 3 ( g m 1 1 + 2 R tail g m 1 + g m 2 1 + g m 2 r ds 4 2 R tail r ds 4 g m 2 g m 4 g m 5 1 + 2 R tail g m 5 g m 6 1 + g m 6 r ds 7 2 R tail r ds 7 g m 6 g m 7 ) = 0
where gm3 is the transconductance of the active load of each stage and Acm1 and Acm2 are the common-mode gain of the N modules and P modules, respectively.

3.1.2. Programming Logic

To fit the EEG signal into ADC’s input dynamic range, a programming approach is proposed which is based on the variation of the tail current transistor width of each stage. To program the gain of the one dual low-gain stage, the tail currents of the N and P type LPGA stages must be reduced consecutively. By turning off the switches of In1 and Ip1 in the programming ladders, the node voltage (Vk1) increases, Vgs1/Vgs2 decreases, Vds1/Vds2 increases, Vgs3/Vgs4 decreases, and I1, I2, I5 and I6 decrease. Accordingly, the gain A and the dynamic range 2 3 ( A + 1 ) decrease. The logic diagram shown in Figure 6 is employed to program the gain of the LPGA. It has been implemented using a shift register, which receives a series input and produces n parallel outputs to tune the N modules. In addition, complementary n outputs have generated (through inverters) to tune the P modules.

3.1.3. Rail-to-Rail Output Stage

To get the maximum SNR at the output, the LPGA is required to achieve a rail-to-rail output swing, which is realized by class-AB architecture shown in Figure 7 and connected at the output of the last stage of the LPGA. This architecture consists of two transconductances ( G mn , G mp ) and a pair of complementary common-source amplifiers (M9 and M10). The output is connected to the inverting input terminal (Vout) and the input signal is applied to the non-inverting input terminal (Vin). It is noted that the small resistors of the demodulator’s switches, in which the LPGA needs to drive them, make the primary motivating factor to use class-AB buffer as output stages to achieve low-output distortion [14]. M2 and M8 are directly connected to VDD and GND, respectively, to have an active load of zero, thus not amplify the feedback signal. The balancing of the bias currents for the differential pairs is done by means of the feedback topology. When the non-inverting input voltage is decreased, the gate voltages of M9 and M10 are increased. As a result, M10 starts to discharge the output node. When the output voltage reaches the level that the voltage difference between the input and output is almost zero, M10 stops discharging the output node [14]. Similarly, when the input voltage (Vin) is increased, M9 charges the output load until the output voltage almost equals the input voltage. The single-ended amplifier incorporates a complementary differential pair as the input stage does, to obtain a full input voltage swing.

4. Measurement Results

A die photograph of the proposed LPGA and CLPGA circuits implemented in TSMC 180 nm CMOS process is shown in Figure 8, where they occupy an active area of 0.4 mm2 and 0.52 mm2, respectively. The post-layout simulations were done with Spectre under Cadence platform, and the fabricated chip was tested in our Polystim Neurotech Laboratory. The DC transfer function of the CLPGA is shown in Figure 9. For an input DC voltage of 15 mV, the simulated output DC voltage is approximated as 0.67 VPP. Figure 9a demonstrates the simulated transfer function of the CLPGA, while the bode transfer function of the simulated CMRR is shown in Figure 9b. The simulated values depict the high ability of the CLPGA to reject the common-mode interference (50/60 Hz) ambient signal coming from the main source coupled to the patient’s body as well as any signal noise and DC offset electrodes applied to CLPGA differential input. Simulation results of the CLPGA bode transfer for different gains at 1 dB step and for a maximum gain of 44 dB are presented in Figure 10a. The transient simulation results are given in Figure 10b, which shows the step-down output magnitude of the CLPGA controlled by the digital part at each rising edge of the clock signal right after the falling edge of the enable signal as well the spike voltage due to charge analog switches. The chopping frequency is 1 kHz, while 0.5 kHz clock is used for the chopper spike filter. The measurements have been performed in a closed-loop configuration shown in Figure 11 [15,16]. Based on this method, the LPGA is configured with a signal gain of −1 V/V using R1 = R2 = 10 k Ω and the LPGA has been supplied by ±0.9 V and it is acting as a preamplifier for its own error signal with R3 = 1 M Ω and a variable resistor (R4) of 2 k Ω used as a voltage divider at the inverting input. A 20 μ F ceramic capacitor, C1, is connected across R3 to filter the low amplitude error signals from noise. Furthermore, to reduce the effect of finite output impedance of the LPGA-under-test and the effect of feed-through due to the feedback path of the test set-up, a general purpose amplifier configured as a voltage buffer is used in the feedback loop [16]. Note that the passive elements and the buffer shown in Figure 11 are off-chip components. The open-loop gain obtained from the set-up is calculated as:
V out In_Test = Gain LPGA R 4 R 1 + R 3 V in
This open-loop gain was measured using a sine wave input of 5 VPP and a frequency of 100 Hz. Figure 12a shows approximately 500 mVPP output signal swing, for the differential input error voltage magnified by a factor of 100, with a maximum value less than or equal to 5 mVPP. The measured open-loop gain is at least 37 dB at 100 Hz. The CMRR is measured by connecting the differential input of the LPGA to a sine wave of 1 VPP at 100 Hz. Figure 12b shows the measured peak-to-peak value of the LPGA differential output, where a 1 VPP input signal has been applied and we obtained the mean values of Vout+ and Vout−, which are found to be 252 μ V and 258 μ V, respectively. Then, the differential signal (7.44 μ V) is obtained by subtracting Vout+ and Vout−. Therefore, the common mode gain is calculated as 20 Log (7.44 μ V/1 V), which results in 103 dB. The high CMRR value is the sum of the common-mode gain (≈103 dB) and the differential gain (≈37 dB), making the capacity of LPGA to reject any common noise signal applied to its differential input. The input-referred noise voltage is measured by connecting the LPGA inputs to ground and performing spectrum analysis of the output signal. Figure 13a shows the measured linear RMS value of the differential output under various input amplitudes and frequencies (75.39 μ Vrms@ 0.1 Hz, 3 mVrms@ 50/60 Hz, and 42.11 μ Vrms@ 100 Hz. Consequently, the measured input-referred noise voltage of the LPGA is determined by dividing the previous values by the linear gain (100 V/V). The input-referred offset voltage of the LPGA is measured by operating the LPGA as comparator and applying a ramp of 1 VPP at VIN+, and the ground at VIN−. The measured input-referred offset voltage that it must be put on the input VIN+ to set the DC differential output of the LPGA to zero is 78.13 μ V, as shown in Figure 13b. In addition, this figure depicts the measured maximum differential output swing of the LPGA, around 616 mVPP.
To amplify the signals, grouping offset, detected by the mismatched EEG electrodes and avoid severe distortion in the LPGA performance as well unity gain bandwidth (UGBW) variation, the measured input voltage range of the complementary LPGA can range from −200 to 200 mV, as presented in Figure 14, where a sine wave signal at 100 Hz is increased gradually at the differential input until the output signal begins to distort. Measurement results of the LPGA are summarized in Table 1 for a resistive and a capacitive load of 10 M Ω and 95 pF, respectively. Although the proposed design achieves high-CMRR, it consumes relatively large amount of power compared to similar designs, as a result of using three amplification stages to increase the CMRR. Therefore, and to provide a fair comparison, we considered a figure of merit (FOM), which is the noise efficiency factor (NEF) as shown in Equation (17) [17]. The NEF of the proposed design is 29.8.
NEF = V rms , in 2 · I t o t ß · U T · 4 K T · B W

5. Conclusions and Future Work

A fully integrated logarithmic programmable gain amplifier (LPGA) dedicated to EEG acquisition systems is introduced in this paper. It features low-noise and high common-mode rejection ratio performance. A proposed logarithmic amplification topology that exhibits low common-mode gain is presented. To further improve the CMRR, three amplification stages were cascaded. Moreover, a chopper stabilization technique was adopted to reduce the 1 / f noise and the inherent DC offset voltage of the input transistors. The generated spikes from the chopping process were canceled by employing a chopper spike filter. Furthermore, a rail-to-rail output stage realized by class-AB architecture was used to maximize the SNR at the output. The proposed circuit was designed and fabricated in 180 nm CMOS technology. Complete experimental characterization was performed to validate the functionality of the presented preamplifier circuit. The LPGA achieved 140 dB CMRR and an input-referred noise of 0.754 μ Vrms. It consumes 189 μ W from 1.8 V power supply and occupies an active area of 0.4 mm 2 .
To further improve the proposed LPGA, more optimizations will be performed to decrease its power consumption. Besides, a fully integrated EEG acquisition channel including the ADC implementation is our next step.

Author Contributions

Conceptualization, R.C. and M.S.; methodology, R.C. and M.S.; validation, R.C., M.A. and M.S.; resources, M.S.; writing—original draft preparation, R.C. and M.A.; writing—review and editing, M.A. and M.S.; and supervision, M.S.

Funding

This research was funded by Canadian Institutes of Health Research (MOP 133643), Heart and Stroke Foundation of Canada, and NSERC of Canada.

Acknowledgments

The authors would like to thank Frédéric Lesage and Dang Nguyen for their inputs to improve the presented design in this manuscript. Thanks are due to CMC Microsystems for the design tools and chip fabrication.

Conflicts of Interest

The authors declare no conflict of interest.

References

  1. Yazicioglu, R.F.; Merken, P.; Puers, R.; Van Hoof, C. A 200 μW Eight-Channel EEG Acquisition ASIC for Ambulatory EEG Systems. IEEE J. Solid-State Circuits 2008, 43, 3025–3038. [Google Scholar] [CrossRef]
  2. Verma, N.; Shoeb, A.; Bohorquez, J.; Dawson, J.; Guttag, J.; Chandrakasan, A.P. A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System. J. Solid-State Circuits 2010, 45, 804–816. [Google Scholar] [CrossRef]
  3. Xu, J.; Yazicioglu, R.F.; Grundlehner, B.; Harpe, P.; Makinwa, K.A.; Van Hoof, C. A 160 μW8-Channel Active Electrode System for EEG Monitoring. IEEE Trans. Biomed. Circuits Syst. 2011, 5, 555–567. [Google Scholar] [CrossRef] [PubMed]
  4. Xu, J.; Mitra, S.; Matsumoto, A.; Patki, S.; Van Hoof, C.; Makinwa, K.A.; Yazicioglu, R.F. A wearable 8-channel active-electrode EEG/ETI acquisition system for body area networks. IEEE J. Solid-State Circuits 2014, 49, 2005–2016. [Google Scholar] [CrossRef]
  5. Chebli, R.; Sawan, M. Chopped logarithmic programmable gain amplifier intended to EEG acquisition interface. In Proceedings of the 2013 25th International Conference on Microelectronics (ICM), Beirut, Lebanon, 15–18 December 2013; pp. 1–4. [Google Scholar]
  6. Pavan, S. Improved Chopping in Continuous-Time Delta–Sigma Converters Using FIR Feedback and N-Path Techniques. IEEE Trans. Circuits Syst. II Express Briefs 2018, 65, 552–556. [Google Scholar] [CrossRef]
  7. Shiah, J.; Mirabbasi, S. A 5-V 290-μW Low-Noise Chopper-Stabilized Capacitive-Sensor Readout Circuit in 0.8-μm CMOS Using a Correlated-Level-Shifting Technique. IEEE Trans. Circuits Syst. II Express Briefs 2014, 61, 254–258. [Google Scholar] [CrossRef]
  8. Bagheri, A.; Salam, M.T.; Velazquez, J.L.; Genov, R. Low-frequency noise and offset rejection in DC-coupled neural amplifiers: A review and digitally-assisted design tutorial. IEEE Trans. Biomed. Circuits Syst. 2017, 11, 161–176. [Google Scholar] [CrossRef] [PubMed]
  9. Lu, C.W. A rail-to-rail class-AB amplifier with an offset cancellation for LCD drivers. IEEE J. Solid-State Circuits 2009, 44, 525–537. [Google Scholar] [CrossRef]
  10. Prutchi, D.; Norris, M. Design and Development of Medical Electronic Instrumentation: A Practical Perspective of the Design, Construction, and Test of Medical Devices; John Wiley & Sons: Hoboken, NJ, USA, 2005. [Google Scholar]
  11. Haberman, M.A.; Spinelli, E.M. A multichannel EEG acquisition scheme based on single ended amplifiers and digital DRL. IEEE Trans. Biomed. Circuits Syst. 2012, 6, 614–618. [Google Scholar] [CrossRef] [PubMed]
  12. Baker, R.J. CMOS Circuit Design, Layout, and Simulation; John Wiley and Sons: Hoboken, NJ, USA, 2008. [Google Scholar]
  13. Gray, P.R. Analysis and Design of Analog Integrated Circuits; John Wiley & Sons: Hoboken, NJ, USA, 2009. [Google Scholar]
  14. Sawigun, C.; Demosthenous, A.; Liu, X.; Serdijn, W.A. A compact rail-to-rail class-AB CMOS buffer with slew-rate enhancement. IEEE Trans. Circuits Syst. II Express Briefs 2012, 59, 486–490. [Google Scholar] [CrossRef]
  15. Pease, R.A. Gain and Linearity Testing for Precision Operational Amplifiers; National Semiconductor Application Note 1671; Texas Instruments: Dallas, TX, USA, 2008. [Google Scholar]
  16. Sansen, W.M.; Steyaert, M.; Vandeloo, P.J. Measurement of operational amplifier characteristics in the frequency domain. IEEE Trans. Instrum. Meas. 1985, 59–64. [Google Scholar] [CrossRef]
  17. Steyaert, M.S.; Sansen, W.M. A micropower low-noise monolithic instrumentation amplifier for medical purposes. IEEE J. Solid-State Circuits 1987, 22, 1163–1168. [Google Scholar] [CrossRef]
  18. Zheng, J.; Ki, W.H.; Tsui, C.Y. A Fully Integrated Analog Front End for Biopotential Signal Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. 2018, 16, 1–10. [Google Scholar] [CrossRef]
  19. Kim, C.; Joshi, S.; Courellis, H.; Wang, J.; Miller, C.; Cauwenberghs, G. A 92 dB dynamic range sub-μVrms-noise 0.8 μW/ch neural-recording ADC array with predictive digital autoranging. In Proceedings of the 2018 IEEE International Solid-State Circuits Conference-(ISSCC), San Francisco, CA, USA, 11–15 February 2018; pp. 470–472. [Google Scholar]
  20. Greenwald, E.; So, E.; Wang, Q.; Mollazadeh, M.; Maier, C.; Etienne-Cummings, R.; Cauwenberghs, G.; Thakor, N. A bidirectional neural interface IC with chopper stabilized BioADC array and charge balanced stimulator. IEEE Trans. Biomed. Circuits Syst. 2016, 10, 990–1002. [Google Scholar] [CrossRef] [PubMed]
  21. Xu, J.; Büsze, B.; Van Hoof, C.; Makinwa, K.A.; Yazicioglu, R.F. A 15-channel digital active electrode system for multi-parameter biopotential measurement. IEEE J. Solid-State Circuits 2015, 50, 2090–2100. [Google Scholar] [CrossRef]
Figure 1. Block diagram of the EEG acquisition system with the proposed CLPGA.
Figure 1. Block diagram of the EEG acquisition system with the proposed CLPGA.
Electronics 08 01157 g001
Figure 2. Circuit implementation of: (a) Choppers 1 and 2; and (b) chopper spike filter.
Figure 2. Circuit implementation of: (a) Choppers 1 and 2; and (b) chopper spike filter.
Electronics 08 01157 g002
Figure 3. Block diagram of the proposed rail-to-rail LPGA.
Figure 3. Block diagram of the proposed rail-to-rail LPGA.
Electronics 08 01157 g003
Figure 4. Circuit schematic of one dual-gain stage.
Figure 4. Circuit schematic of one dual-gain stage.
Electronics 08 01157 g004
Figure 5. Small-signal equivalent half circuit of the LGA.
Figure 5. Small-signal equivalent half circuit of the LGA.
Electronics 08 01157 g005
Figure 6. Programming logic diagram of the LPGA.
Figure 6. Programming logic diagram of the LPGA.
Electronics 08 01157 g006
Figure 7. Circuit schematic of single-ended Class AB buffer.
Figure 7. Circuit schematic of single-ended Class AB buffer.
Electronics 08 01157 g007
Figure 8. Die micrograph.
Figure 8. Die micrograph.
Electronics 08 01157 g008
Figure 9. (a) Simulated Transfer Function of the CLPGA; and (b) bode transfer function of the simulated CMRR.
Figure 9. (a) Simulated Transfer Function of the CLPGA; and (b) bode transfer function of the simulated CMRR.
Electronics 08 01157 g009
Figure 10. CLPGA simulation results: (a) bode transfer function for different gains; and (b) control of the fClk = 0.5 kHz and input sine wave of 360 μ V and 100 Hz.
Figure 10. CLPGA simulation results: (a) bode transfer function for different gains; and (b) control of the fClk = 0.5 kHz and input sine wave of 360 μ V and 100 Hz.
Electronics 08 01157 g010
Figure 11. Experimental set-up for LPGA open-loop gain measurement.
Figure 11. Experimental set-up for LPGA open-loop gain measurement.
Electronics 08 01157 g011
Figure 12. Measured open loop ( R load = 10 M Ω and C load = 95 pF): (a) voltage gain of the LPGA at 100 Hz for Vin = 5 V PP ; and (b) CMRR ( 140 dB) of the LPGA at 100 Hz for Vin = 1 V PP .
Figure 12. Measured open loop ( R load = 10 M Ω and C load = 95 pF): (a) voltage gain of the LPGA at 100 Hz for Vin = 5 V PP ; and (b) CMRR ( 140 dB) of the LPGA at 100 Hz for Vin = 1 V PP .
Electronics 08 01157 g012
Figure 13. Measured open loop ( R load = 10 M Ω and C load = 95 pF): (a) output-referred noise of the LPGA at 0.1 Hz, 50/60 Hz, and 100 Hz; and (b) input-referred offset voltage and maximum differential output swing of the LPGA for an input ramp of 1 V PP at 100 Hz.
Figure 13. Measured open loop ( R load = 10 M Ω and C load = 95 pF): (a) output-referred noise of the LPGA at 0.1 Hz, 50/60 Hz, and 100 Hz; and (b) input-referred offset voltage and maximum differential output swing of the LPGA for an input ramp of 1 V PP at 100 Hz.
Electronics 08 01157 g013
Figure 14. Measured open loop ( R load = 10 M Ω and C load = 95 pF) input voltage range using an input sine wave at 100 Hz.
Figure 14. Measured open loop ( R load = 10 M Ω and C load = 95 pF) input voltage range using an input sine wave at 100 Hz.
Electronics 08 01157 g014
Table 1. LPGA Performance Summary and Comparison.
Table 1. LPGA Performance Summary and Comparison.
Reference[18][19][20][21][4]This Work
Technology (CMOS)180 nm65 nm180 nm180 nm180 nm180 nm
Supply Voltage (V)1.20.81.51.81.8 ± 0.9
Gain (dB)58150NA11–10137
CMRR (dB)>100NA9710284140
Noise1.3 μ Vrms0.99 μ Vrms1 μ Vrms0.65 μ Vrms1.75 μ Vrms0.754 μ Vrms
Bandwidth (Hz)0.5–5000.1–5000.25–2500.5–1000.5–1000.1–100
Power Consumption ( μ W)9.240.85.510482189
[email protected]/60Hz (dB)NANANANANA145
Area (mm 2 )1.2 a0.0242.25 a15.8 a17.55 b0.4
THD (%)0.082NANANANA0.045
NEF6.151.814.6719.145.629.8
a, chip area, including ADC; b, chip area.

© 2019 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).
Back to TopTop