Search Results (22)

This work presents a high-common-mode-rejection-ratio (CMRR) and high-gain FinFET-based bio-potential amplifier with a novel CMRR reduction technique. In this paper, a feedback buffer is used alongside a capacitively coupled chopper-stabilized circuit to reduce the common-mode signal gain, thus boosting the overall CMRR of the circuit. The conventional pseudoresistor in the feedback circuit is replaced with a tunable parallel-cell configuration of pseudoresistors to achieve high linearity. A chopper spike filter is used to mitigate spikes generated by switching activity. The mid-band gain of the chopper-stabilized amplifier is 42.6 dB, with a bandwidth in the range of 6.96 Hz to 621 Hz. The noise efficiency factor (NEF) of the chopper-stabilized amplifier is 6.1, and its power dissipation is 0.92 µW. The linearity of the parallel pseudoresistor cell is tested for different tuning voltages (V_tune) and various numbers of parallel pseudoresistor cells. The simulation results also demonstrate the pseudoresistor cell performance for different process corners and temperature changes. The low cut-off frequency is adjusted by varying the parameters of the parallel pseudoresistor cell. The CMRR of the chopper-stabilized amplifier, with and without the feedback buffer, is 106.9 dB and 100.3 dB, respectively. The feedback buffer also reduces the low cut-off frequency, demonstrating its multi-utility. The proposed circuit is compatible with bio-signal acquisition and processing. Additionally, a machine learning-based arrhythmia diagnosis model is presented using a convolutional neural network (CNN) + Long Short-Term Memory (LSTM) algorithm. For arrhythmia diagnosis using the CNN+LSTM algorithm, an accuracy of 99.12% and a mean square error (MSE) of 0.0273 were achieved. Full article

Over the past few decades, wind energy has expanded to become a widespread, clean, and sustainable energy source. However, integrating offshore wind energy with the onshore AC grids presents many stability and control challenges that hinder the reliability and resilience of AC grids, particularly during faults. To address this issue, current grid codes require offshore wind farms (OWFs) to remain connected during and after faults. This requirement is challenging because, depending on the fault location and power flow direction, DC link over- or under-voltage can occur, potentially leading to the shutdown of converter stations. Therefore, this necessitates the proper understanding of key technical concepts associated with the integration of OWFs. To help fill the gap, this article performs an in-depth investigation of existing alternating current fault ride through (ACFRT) techniques of modular multilevel converter-based high-voltage direct current (MMC-HVDC) for OWFs. These techniques include the use of AC/DC choppers, flywheel energy storage devices (FESDs), power reduction strategies for OWFs, and energy optimization of the MMC. This article covers both scenarios of onshore and offshore AC faults. Given the importance of wind turbines (WTs) in transforming wind energy into mechanical energy, this article also presents an overview of four WT topologies. In addition, this article explores the advanced converter topologies employed in HVDC systems to transform three-phase AC voltages to DC voltages and vice versa at each terminal of the DC link. Finally, this article explores the key stability and control concepts, such as small signal stability and large disturbance stability, followed by future research trends in the development of converter topologies for HVDC transmission such as hybrid HVDC systems, which combine current source converters (CSCs) and voltage source converters (VSCs) and diode rectifier-based HVDC (DR-HVDC) systems. Full article

This paper presents an amplifier with low noise, high gain, low power consumption, and high linearity for electrocardiogram (ECG) recording. The core of this design is a chopper-stabilized capacitive-feedback operational transconductance amplifier (OTA). The proposed OTA has a two-stage structure, with the first stage using a combination of current reuse and cascode techniques to obtain a large gain at low power and the second stage operating in Class A state for better linearity. The amplifier additionally uses a DC servo loop (DSL) to improve the rejection of DC offsets. The amplifier is implemented in a standard 0.13 μm CMOS process, consuming 1.647 μA current from the supply voltage of 1.5 V and occupying an area of 0.97 mm². The amplifier has a 0.5 Hz to 6.1 kHz bandwidth and 59.7 dB gain while having no less than a 65 dB common-mode rejection ratio (CMRR). The amplifier’s total harmonic distortion (THD) is less than 0.1% at 800 mV_pp output. The amplifier can provide a noise level of 1.18 μV_rms in the 0.5 Hz to 500 Hz bandwidth that the ECG signal is interested in and has 3.38 μV_rms input-referred noise (IRN) over the entire bandwidth, so its noise efficiency factor (NEF) is 2.13. Full article

The MEMS sensor converts the physical signal of nature into an electrical signal. The output signal of the MEMS sensor is so weak and basically in the low-frequency band that the MEMS sensor interface circuit has a rigorous requirement for the noise/offset and temperature coefficient, especially in the bandgap reference block. However, the traditional amplifier has low-frequency noise and offset voltage, which will decrease the precision of the bandgap reference. In order to satisfy the need of the MEMS sensor interface circuit, a high-precision and low-noise bandgap reference is proposed in this paper. A novel operational amplifier with a chopper-stabilization technique is adopted to reduce offset and low-frequency noise. At the same time, the V-curve compensation circuit is used to realize the second-order curvature compensation. The circuit is implemented under the 0.18 μm standard of the CMOS process. The test result shows that the temperature coefficient of the bandgap is 2.31 ppm/°C in the range of −40–140 °C, while the output voltage noise is only 616 nV/sqrt(Hz)@1 Hz and the power-supply rejection ratio is 73 dB@10 kHz. The linear adjustment rate is 0.33 mV/V for supply voltages of 1.2–1.8 V at room temperature, the power consumption is only 107 μW at 1.8 V power supply voltage, and the chip active area is 0.21 × 0.28 mm². Full article

Renewable energy sources play a pivotal role in the pursuit of sustainable and eco-friendly power solutions. While offering environmental benefits, they present inherent challenges. Photovoltaic systems rely on surrounding conditions, wind systems contend with variable wind speeds, and fuel cells are both costly and inefficient. Furthermore, the energy injected by renewable energy sources (RES) exhibits unpredictable behavior. To tackle these problems, researchers employ diverse power electronic devices and converters like inverters, power quality filters, and DC–DC choppers. Among these, DC–DC converters stand out for effectively regulating DC voltage and enhancing the efficiency of RESs. The meticulous selection of a suitable DC–DC converter, coupled with the integration of an efficient control technique, significantly influences overall power system performance. This paper introduces a novel approach to the design of switching controllers for DC–DC converters, specifically tailored for application in renewable energy systems. The proposed controller leverages the power of composite switched Lyapunov functions (CSLF) to enhance the efficiency and performance of DC–DC converters, addressing the unique challenges posed by renewable energy sources. Through comprehensive analysis and simulation, this study demonstrates the efficacy of the controller in optimizing power transfer, improving stability, and ensuring reliable operation in diverse renewable energy environments. Moreover, the small-scale DC–DC converter experiment’s findings are presented to confirm and validate the proposed scheme’s practical applicability. Full article

This paper presents a low-voltage low-power chopper-stabilized differential difference amplifier (DDA) realized using 40 nm CMOS technology. Operating with a supply voltage of 0.5 V, a three-stage DDA has been employed to achieve an open-loop gain of 89 dB, while consuming just 0.74 μW of power. The proposed DDA incorporates feed-forward frequency compensation and a Type II compensator to achieve pole-zero cancellation and damping factor control. The DDA has a unity-gain bandwidth (UGB) of 170 kHz, a phase margin (PM) of 63.98°, and a common-mode rejection ratio (CMRR) of up to 100 dB. This circuit can effectively drive a 50 pF capacitor in parallel with a 300 kΩ resistor. The use of the chopper stabilization technique effectively mitigates the offset and 1/f noise. The chopping frequency of the chopper modulator is 5 kHz. The input noise is 245 nV/sqrt (Hz) at 1 kHz, and the input-referred offset under Monte Carlo cases is only 0.26 mV. Such a low-voltage chopper-stabilized DDA will be very useful for analog signal processing applications. Compared to the reported chopper DDA counterparts, the proposed DDA is regarded as that with one of the lowest supply voltages. The proposed DDA has demonstrated its effectiveness in tradeoff design when dealing with multiple parameters pertaining to power consumption, noise, and bandwidth. Full article

This article deals with the calibration method of analog integrated circuits (ICs) designed in CMOS nanotechnology. A brief analysis of various methods and techniques (e.g., fuse trimming, chopper stabilization, auto-zero technique, etc.) for calibration of a specific IC’s parameter is given, leading to motivation for this research that is focused on the digital calibration. Then, the principle and overall design of the calibration subcircuit, which was generally used to calibrate the input offset voltage $V_{IN\_OFF}$ of the operational amplifier (OPAMP). The essence of this work is verification of the proposed digital calibration algorithm for minimization the $V_{IN\_OFF}$ of a bulk-driven fully differential difference amplifier (FDDA) with the power supply voltage $V_{DD}$ = 0.4 V. Evaluation of ASIC prototyped chip samples with silicon-proved results has been done. This evaluation contains comparison of selected parameters and characteristics obtained from both simulations and measurements of non-calibrated and calibrated FDDA configurations. Full article

A low-noise and -power readout integrated circuit (IC) for two-electrode electrocardiogram (ECG) recording is developed in this study using a common-mode charge pump (CMCP) for a robust 20-V_PP common-mode interference (CMI). Two-electrode ECG recording offers more comfort than three-electrode ECG recording. Contrasting to the three-electrode ECG recording, the two-electrode ECG recording is affected by CMI during measurements; the intervention of a large CMI will distort the ECG signal measurement. To achieve robustness for the CMI, the proposed ECG readout IC adopts CMCP—it uses switched capacitors that store and subtract CMI by control logic. In this paper, a window comparator structure is applied to CMCP to obtain a signal with less distortion. The window voltage ranges were set between the input common-mode ranges in which IA can operate. Therefore, a signal with less distortion was obtained by stopping the operation of CMCP between the window voltage ranges. It also reduced additional current consumption. To achieve this, the proposed circuit is implemented using a chopper stabilization technique. The chopper implemented in the amplifier can reduce low-frequency noise components, such as 1/f noise, and it comprises a CMCP, current feedback instrumentation amplifier, QRS peak detector, relaxation oscillator, voltage reference, timing generator, and serial peripheral interface on a single chip. The proposed circuit was designed using a standard 0.18 μm CMOS process with an active area of 0.54 mm². The proposed CMCP achieves a CMI robustness of 20 V_PP at 60 Hz. The measured input-referred noise level was 119 nV/√Hz at 1 Hz, and the power consumption was 23.83 μW with a 1.8 V power supply. Full article

Active thermography is an established technique for non-destructive testing and defect localisation. For external excitation, powerful light sources are commonly used. In addition to a high optical output, a good signal shape and response characteristic as well as control ports, which allow for multiple operation modes, are important for active thermography applications. In this work, the schematics for an excitation source based on infrared LEDs is presented. It features multiple control modes for easy integration into existing measurement setups as well as sophisticated control electronics to realize a wide range of excitation patterns. The phase and amplitude stability of this prototype is investigated and compared to the performance of a modulated halogen lamp as well as a halogen lamp and mechanical chopper combination. Full article

This paper presents a potentiostat readout circuit with low-noise and mismatch-tolerant current mirror using chopper stabilization and dynamic element matching (DEM) for electrochemical sensors. Current-mode electrochemical sensors are widely used to detect the blood glucose and viruses in the diagnosis of various diseases such as diabetes, hyperlipidemia, and the H5N1 avian influenza virus (AIV). Low-noise and mismatch-tolerant characteristics are essential for sensing applications that require high reliability and high sensitivity. To achieve these characteristics, a proposed potentiostat readout circuit is implemented using the chopper stabilization scheme and the DEM technique. The proposed potentiostat readout circuit consists of a chopper-stabilized programmable gain transimpedance amplifier (TIA), gain-boosted cascode current mirror, and a control amplifier (CA). The chopper scheme, which is implemented in the TIA and CA, can reduce low frequency noise components, such as 1/f noise, and can obtain low-noise levels. The mismatch offsets of the cascode current mirror can be reduced by the DEM operation. The proposed current-mirror-based potentiostat readout circuit is designed using a standard 0.18 μm CMOS process and can measure the sensor current from 350 nA to 2.8 μA. The input-referred noise integrated from 0.1 Hz to 1 kHz is 21.7 pA_RMS, and the power consumption was 287.9 μW with a 1.8 V power supply. Full article

This paper presents a low-noise and low-power audio preamplifier. The proposed low-noise preamplifier employs a delay-time chopper stabilization (CHS) technique and a negative-R circuit, both in the auxiliary amplifier to cancel the non-idealities of the main amplifier. The proposed technique makes it possible to mitigate the preamplifier 1/f noise and thermal noise and improve its linearity. The low-noise preamplifier is implemented in 65 nm complementary metal-oxide semiconductor (CMOS) technology. The supply voltage is 1.2 V, while the power consumption is 159 µW, and the core area is 192 µm². The proposed circuit of the preamplifier was fabricated and measured. From the measurement results over a signal bandwidth of 20 kHz, it achieves a signal-to-noise ratio (SNR) of 80 dB, an equivalent-input referred noise of 5 nV/√Hz and a noise efficiency factor (NEF) of 1.9 within the frequency range from 1 Hz to 20 kHz. Full article

A low-noise instrumentation amplifier dedicated to a nano- and micro-electro-mechanical system (M&NEMS) microphone for the use in Internet of Things (IoT) applications is presented. The piezoresistive sensor and the electronic interface are respectively, silicon nanowires and an instrumentation amplifier. To design an instrumentation amplifier for IoT applications, different trade-offs are discussed like power consumption, gain, noise and sensitivity. Because the most critical noisy block is the amplifier, a delay-time chopper stabilization (CHS) technique is implemented around it to eliminate its offset and 1/f noise. The low-noise instrumentation amplifier is implemented in a 65-nm CMOS (Complementary metal–oxide–semiconductor) technology. The supply voltage is 2.5 V while the power consumption is 0.4 mW and the core area is 1 mm². The circuit of the M&NEMS microphone and the amplifier was fabricated and measured. From measurement results over a signal bandwidth of 20 kHz, it achieves a signal-to-noise ratio (SNR) of 77 dB. Full article

The recently growing progress in neuroscience research and relevant achievements, as well as advancements in the fabrication process, have increased the demand for neural interfacing systems. Brain–machine interfaces (BMIs) have been revealed to be a promising method for the diagnosis and treatment of neurological disorders and the restoration of sensory and motor function. Neural recording implants, as a part of BMI, are capable of capturing brain signals, and amplifying, digitizing, and transferring them outside of the body with a transmitter. The main challenges of designing such implants are minimizing power consumption and the silicon area. In this paper, multi-channel neural recording implants are surveyed. After presenting various neural-signal features, we investigate main available neural recording circuit and system architectures. The fundamental blocks of available architectures, such as neural amplifiers, analog to digital converters (ADCs) and compression blocks, are explored. We cover the various topologies of neural amplifiers, provide a comparison, and probe their design challenges. To achieve a relatively high SNR at the output of the neural amplifier, noise reduction techniques are discussed. Also, to transfer neural signals outside of the body, they are digitized using data converters, then in most cases, the data compression is applied to mitigate power consumption. We present the various dedicated ADC structures, as well as an overview of main data compression methods. Full article

This paper proposes a low noise readout integrated circuit (IC) with a chopper-stabilized multipath operational amplifier suitable for a Wheatstone bridge sensor. The input voltage of the readout IC changes due to a change in input resistance, and is efficiently amplified using a three-operational amplifier instrumentation amplifier (IA) structure with high input impedance and adjustable gain. Furthermore, a chopper-stabilized multipath structure is applied to the operational amplifier, and a ripple reduction loop (RRL) in the low frequency path (LFP) is employed to attenuate the ripple generated by the chopper stabilization technique. A 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) is employed to convert the output voltage of the three-operational amplifier IA into digital code. The Wheatstone bridge readout IC is manufactured using a standard 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology, drawing 833 µA current from a 1.8 V supply. The input range and the input referred noise are ±20 mV and 24.88 nV/√Hz, respectively. Full article

This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can be reconfigured for a specific sensor application. The multimodal sensor readout circuit consists of a reconfigurable amplifier, programmable gain amplifier (PGA), low-pass filter (LPF), and analog-to-digital converter (ADC). A chopper stabilization technique was implemented in a multi-path operational amplifier to mitigate 1/f noise and offsets. The 1/f noise and offsets were up-converted by a chopper circuit and caused an output ripple. An AC-coupled ripple rejection loop (RRL) was implemented to reduce the output ripple caused by the chopper. When the amplifier was operated in the discrete-time mode, for example, the capacitive-sensing mode, a correlated double sampling (CDS) scheme reduced the low-frequency noise. The readout circuit was designed to use the 0.18-µm complementary metal-oxide-semiconductor (CMOS) process with an active area of 9.61 mm². The total power consumption was 2.552 mW with a 1.8-V supply voltage. The measured input referred noise in the voltage-sensing mode was 5.25 µV_rms from 1 Hz to 200 Hz. Full article