An Active Common-Mode Voltage Compensation Method for Three-Phase Induction Motor Drives ^†

Abstract

Pulse Width Modulated (PWM) voltage source inverters are widely used to power induction motors in industrial applications. However, they generate common-mode voltage (CMV), which induces high shaft voltages and bearing currents, leading to premature motor failures. This paper proposes a novel active cancellation method to compensate for the CMV in high-voltage induction motor drives. The method utilizes Y-configured resistors for CMV detection and a push–pull amplifier with MOSFETs to generate reproduced CMV (RCMV). The RCMV is applied to the motor frame via an isolation transformer, effectively reducing the CMV-induced common-mode current (CMC). The proposed method achieves a significant reduction in the CMC, from 1.5 A to 4 mA peak-to-peak in a simulation and from 2.7 A to 57 mA peak in experiments with a 1.1 kW, 415 V/60 Hz motor. This cost-effective approach enhances motor drive reliability and mitigates electromagnetic interference (EMI), making it suitable for high-voltage applications.

1. Introduction

Nowadays, the use of induction motors fed by three-phase inverters is growing rapidly in industrial applications due to their low cost, high reliability, and maintenance-free operation [1,2]. The high-speed pulse width modulation (PWM) switching process, responsible for rapid voltage and current transitions, generates a voltage with large step sizes, known as common-mode voltage (CMV). This phenomenon leads to several serious issues, including common-mode current (CMC), conducted electromagnetic interference (EMI), shaft voltage, bearing failures in motor drive systems, and leakage currents that flow to the earth through the motor internal parasitic capacitors [3]. The significant issue of reduced motor bearing lifespan has been thoroughly examined in [4,5,6]. Specifically, shaft voltage is induced in the stator windings due to the CMV via parasitic capacitance through the motor air gap, creating electrostatic discharge in the lubricating film of motor bearings and ultimately reducing their lifespan [7,8,9,10].

In typical three-phase induction motor drive systems, the parasitic capacitance between the stator windings and the motor frame (ground) ranges from approximately 1 nF to 10 nF, depending on the motor rating, insulation class, and winding geometry. For the 1.1 kW, 415 V motor used in this work, a measured parasitic capacitance of 2.4 nF was identified between the motor neutral point and the frame. This parasitic capacitance, in combination with the leakage inductance of the isolation transformer (ITR) secondary winding, forms an LC resonant circuit that introduces additional harmonic spikes into the motor-frame voltage waveform. This resonance effect creates a discrepancy between the CMV and the RCMV applied via the ITR, and must be actively compensated through a series inductor connected between the ITR secondary winding and the motor frame, as detailed in Section 3.

Over the last two decades, several studies have proposed numerous methods to mitigate the CMV and CMC generated by PWM-driven inverters in induction motor drives. These methods can be categorized into three types: (1) modulation techniques, (2) passive filters, and (3) active filters. Various PWM techniques, such as AZPWM, NSPWM, DPWM, and RSPWM, have been developed to reduce the CMV and CMC [11,12,13], as reviewed in [14,15,16,17,18]. These methods adjust inverter output by limiting PWM switching possibilities, reducing the dv/dt of the CMV and consequently the CMC. However, they often trade off waveform quality, introduce harmonic distortions, and, in some cases, increase switching loss functions (SLFs), reducing overall efficiency.

Another approach employs passive filtering techniques such as LC, LCL, LR, and LRC filters as well as common-mode transformers (CMTR) to mitigate the CMC and CMV [19,20,21,22,23]. These filters are effective at targeting specific frequency ranges. However, their practical application faces challenges related to resonance, power loss, size, cost, and complexity in high-performance grid-connected systems [24,25,26]. A combined RLC filter and CMTR method, proposed in [27,28], uses a Y-configured RC network to detect CMV and series-connected inductors to magnetize the CMTR. However, this method requires high magnetizing currents and involves a trade-off in selecting capacitor and resistor values, leading to higher costs, line current distortion, power loss and larger components.

In 1998, an active common-noise cancellation or active common-mode cancellation (ACC) circuit was proposed to eliminate the CMV generated by PWM inverters [29]. This ACC consists of Y-configured capacitors, a push–pull emitter follower using complementary transistors, a CMTR, and two DC-side capacitors. However, this method has the limitation of current for CMTR, therefore it can be used for lower power applications only. To address current limitations, an improved method based on an active noise cancellation circuit was proposed in [30], employing a Darlington pair transistor to achieve higher magnetizing currents. For higher-voltage-rated systems, these methods require a separate power supply [31,32,33,34,35], which is challenging to integrate into a single drive system. Since the CMTR secondary windings are connected directly to the inverter output terminals in the aforementioned ACC circuits, a higher magnetizing current is required to magnetize the transformer, resulting in a larger, costlier core and high losses.

A new ACC circuit for reducing CM noise in vehicular three-phase AC motor drives was proposed in [36]. This circuit features a feed-forward voltage-detecting, voltage-compensating structure and avoids CM transformers on thick phase wires by driving the chassis and motor frame relative to the inverter ground, thereby aligning the motor neutral potential with the motor frame to block the CMC from flowing through the motor windings. Building on this concept, the authors of [37] proposed an improved active cancellation method that also employs a feed-forward voltage-detecting, voltage-compensating structure. In this method, Y-configured capacitors are used to detect the CMV, which is then amplified through a Darlington pair transistor push–pull amplifier and applied directly to the motor frame relative to the inverter ground. This approach eliminates the potential difference between the motor neutral point and the motor frame, effectively cancelling the CMC. Additionally, this method incorporates an isolation transformer (ITR) to isolate the ACC circuit from the motor frame and chassis, enhancing safety through electrical isolation.

Despite these advancements, existing methods face limitations, such as the need for separate power supplies or issues with capacitive CMV detection, which can introduce line current spikes. To address these challenges, this paper presents a detailed design and experimental setup of a new CMC cancellation method optimized for higher DC-link voltages. Building on the improved ACC concept, this method achieves CMC cancellation by applying the RCMV to the motor frame via an ITR, minimizing the voltage difference between the motor neutral point and the frame. This approach eliminates CMC effectively for higher DC-link voltage drives without the need for a separate power supply.

The proposed circuit employs Y-connected sensing resistors to detect CMV and MOSFET-based push–pull amplifiers for high-voltage applications. Additionally, low-frequency blocking capacitors (LFBC) and compensating inductors are included to filter low-frequency RCMV components, further reducing transformer size and harmonics in CMV, thereby enhancing CMV compensation and reducing CM EMI. The inclusion of the LFBC also increases the flexibility of the circuit, enabling its use with various PWM techniques that involve low-frequency CMV components, such as SVPWM [33]. This allows the proposed method to adapt to different PWM schemes, ensuring improved performance across a wide range of motor drive systems.

Compared to modulation-based CMV reduction strategies (e.g., AZPWM, NSPWM, and DPWM), the proposed hardware-based active cancellation method offers several distinct advantages. Modulation-based methods reduce the CMV by restricting inverter switching states, which inevitably trades off output voltage quality; they increase harmonic distortion, reduce the achievable modulation index, and may increase switching losses [11,12,13,38,39]. In contrast, the proposed method imposes no constraints on the PWM scheme, preserving full modulation quality and remaining compatible with any PWM technique, as demonstrated with both SVPWM and SPWM in this work. Furthermore, modulation-based approaches reduce the CMV at the source but do not fully eliminate the residual CMC flowing through motor parasitic capacitances, whereas the proposed method directly applies an anti-phase RCMV to the motor frame, actively cancelling the CMC at its point of entry into the motor. The primary limitation of the hardware approach is the addition of physical components, including resistors, MOSFETs, an isolation transformer, a blocking capacitor, and a compensating inductor, which increases system complexity and cost compared to a purely software-based PWM modification. Nonetheless, for high-voltage motor drives where EMI compliance and bearing lifetime are critical, the superior CMC suppression offered by the active hardware approach (97.89% reduction demonstrated experimentally) justifies the added complexity.

The main contributions of this paper are as follows: (1) A novel active CMC cancellation method optimized for high DC-link voltage (400 V) motor drives is proposed, eliminating the need for a separate power supply. (2) Y-configured sensing resistors, instead of conventional capacitors, are employed for CMV detection, eliminating line current spikes associated with capacitive detection. (3) A MOSFET-based push–pull amplifier with wide bandwidth enables faithful CMV reproduction across different PWM schemes (SVPWM and SPWM). (4) A low-frequency blocking capacitor (LFBC) filters the third-harmonic component in the isolation transformer primary current, reducing core size and enabling SVPWM compatibility. (5) A compensating inductor addresses parasitic resonance at the motor frame, further improving CMC suppression. Experimental results demonstrate a 97.89% reduction in CMC (from 2.7 A to 57 mA peak), validating the proposed approach.

The proposed method demonstrates significant improvements over previous approaches, achieving better CMV and CMC compensation in higher voltage drives. This paper outlines the design, implementation, and experimental validation of the proposed method using a 400 V DC-link voltage and a three-phase induction motor (1.1 kW, 415 V/60 Hz).

This paper is organized as follows: Section 2 discusses the operating principle of the cancellation circuit. Section 3 details the design of the active cancellation circuit. The simulation and experimental results are presented in Section 4 and Section 5, respectively. Section 6 concludes the paper.

This article is a revised and expanded version of a paper entitled “An Active Common-Mode Current Suppression Method for Three-Phase Motor Drive Systems”, which was presented at the Proceedings of the Korean Institute of Power Electronics (KEPCO), Pyeongchang, South Korea [40].

2. Operating Principle of the Proposed Active CMC Cancellation Method

Figure 1 presents the block diagram of the proposed CMC compensation method. This method introduces an enhanced active cancellation circuit to effectively mitigate CMC in three-phase motor drives. The circuit diagram of the proposed active compensation method, incorporating a three-phase two-level inverter and a three-phase induction motor, is shown in Figure 2, while Figure 3 illustrates the simplified schematic of the active compensation circuit.

This method is based on the feed-forward voltage-detecting voltage-compensating concept. In this method a Y-connected resistor bank is used after the inverter output to form a neutral point for CMV detection, in addition to a unity gains push–pull amplifier, which consists of N-channel and P-channel MOSFETs connected in complementary positions. The output of the push–pull amplifier is then applied to the motor frame via the isolation transformer (ITR). Additionally, a low-frequency blocking capacitor is added in series with the primary winding of the ITR to filter out low-frequency components in the magnetizing current, helping to reduce the core size further. The secondary voltage of the ITR, or RCMV, is applied to the motor frame through a compensating inductor to offset the parasitic capacitance between the motor neutral point and frame.

From a theoretical perspective, as there is no voltage difference between the motor neutral point and the motor frame after imposing the RCMV, ideally no CMC will flow through the motor parasitic capacitors. Consequently, the current flow through the ITR will be minimal, allowing for a smaller core size. A smaller core size results in a lower-cost solution for the compensation circuit. Hence, the proposed method is more effective in compensating for the CMV and CMC in high voltage motor drives compared to previous solutions. The advantage of connecting the transformer output to the motor frame instead of the inverter output line leads to a lower-cost compensation circuit with a significant increase in drive system reliability.

Mathematical Analysis of the Proposed Method

The inverter phase voltages relative to the compensation circuit midpoint ‘O’ can be expressed as follows, (1)–(3), based on Figure 3.

$${\mathrm{V}}_{\mathrm{A}\mathrm{Ó}}=\left({\mathrm{i}}_{\mathrm{x}}\right)\mathrm{R}+{\mathrm{V}}_{\mathrm{g}\mathrm{s}}+\mathrm{V}{\mathrm{c}}_2+{\mathrm{V}}_{\mathrm{T}\mathrm{R}-\mathrm{P}}$$

(1)

$${\mathrm{V}}_{\mathrm{B}\mathrm{Ó}}=\left({\mathrm{i}}_{\mathrm{y}}\right)\mathrm{R}+{\mathrm{V}}_{\mathrm{g}\mathrm{s}}+\mathrm{V}{\mathrm{c}}_2+{\mathrm{V}}_{\mathrm{T}\mathrm{R}-\mathrm{P}}$$

(2)

$${\mathrm{V}}_{\mathrm{C}\mathrm{Ó}}=\left({\mathrm{i}}_{\mathrm{z}}\right)\mathrm{R}+{\mathrm{V}}_{\mathrm{g}\mathrm{s}}+\mathrm{V}{\mathrm{c}}_2+{\mathrm{V}}_{\mathrm{T}\mathrm{R}-\mathrm{P}}$$

(3)

Here, $V_{gs}$ represents the voltage drop across the MOSFET gate-to-source terminals; $i_x$, $i_y$, $i_z$ are common-mode currents; $V{c}_2$ is LFBC ($C_2$) voltage; and $V_{TR-P}$ is the reproduced voltage at the primary winding of the ITR which is connected to the push–pull output.

For the balanced three-phase system, the CMV (VCM) can be expressed as:

$$3{\mathrm{V}}_{\mathrm{C}\mathrm{M}}={\mathrm{V}}_{\mathrm{A}\mathrm{O}}+{\mathrm{V}}_{\mathrm{B}\mathrm{O}}+{\mathrm{V}}_{\mathrm{C}\mathrm{O}}.$$

(4)

And the ITR primary voltage can be derived as

$${\mathrm{V}}_{\mathrm{T}\mathrm{R}-\mathrm{P}}={\mathrm{V}}_{\mathrm{C}\mathrm{M}}-{\mathrm{V}}_{\mathrm{g}\mathrm{s}}-\mathrm{V}{\mathrm{c}}_2-{\mathrm{i}}_{\mathrm{g}}\mathrm{R},$$

(5)

where $i_g$ is the gate current of complementary MOSFETs, which is very low and occurs over a very short period of switching time. Due to the high impedance at the gate of the MOSFET, the value of $i_g$ is very low, just small spikes of charging and discharging currents of the MOSFET input capacitance ($C_{iss}$); as shown in Figure 4, that is why the $i_{g}R$ is very low and can be ignored. The value of the $i_g$ can be measured using the following Equation (6) [41],

$${\mathrm{i}}_{\mathrm{g}}={\displaystyle \frac{{\mathrm{Q}}_{\mathrm{g}}}{{\mathrm{t}}_{\mathrm{r}}}},$$

(6)

where $Q_g$ is the total gate charge, consisting of two components, $Q_{gs}$ due to $C_{iss}$, and $Q_{gd}$ due to Crss (gate to drain capacitance). $t_r$ is the rise time of voltage during IGBTs commutation (100 ns) as can be seen in Figure 4.

The $V{c}_2$ is LFBC drop, which is very low for high frequency. By ignoring $i_{g}R$ and $V{c}_2$, the voltage difference ($V_{error}$) between the detected CMV and RCMV at the ITR primary winding is approximately equal to $V_{gs}$, which corresponds to the threshold voltages of the MOSFET.

$${\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}\mathrm{o}\mathrm{r}}\approx {\mathrm{V}}_{\mathrm{g}\mathrm{s}}$$

(7)

Figure 4 shows the gate current waveform of the MOSFET push–pull amplifier during a switching transition. The narrow current spikes at the rising and falling edges correspond to the charging and discharging of the MOSFET input capacitance ($C_{iss}$). These spikes are brief, occurring within the 100 ns rise time of the inverter switches, and their peak magnitude is determined by $i_g$ and the sensing resistor value, as given in Equation (6). After this transient interval, the gate current returns to near zero, confirming that the circuit draws negligible steady-state current from the CMV-sensing network. This validates the assumption that the gate current can be neglected in the steady-state analysis of Equation (5).

Figure 5 shows the CMV measured at the inverter output neutral point under SVPWM operation. The waveform exhibits the characteristic three-level switching pattern with voltage steps of +200 V and −200 V, where +400 V is the DC-link voltage. The high-frequency content corresponds to the 10 kHz switching frequency and its harmonics. The low-frequency third-harmonic envelope visible in the waveform is a known characteristic of SVPWM and is the primary motivation for including the low-frequency blocking capacitor (LFBC); without it, this component would cause core saturation in the isolation transformer at low frequencies.

3. Active Cancellation Circuit Design Procedure

The proposed CMC cancellation method with improved ACC consists of several components, such as:

• Sensing resistors;
• A MOSFET-based push–pull amplifier;
• DC-side capacitors;
• An ITR with LFBC;
• An inductor for the compensation of parasitic capacitor.

3.1. Sensing Resistor

A Y-configured set of three resistors is used at the inverter output terminal to sense the CMV with respect to the midpoint ‘O’, as shown in Figure 3. The selection of sensing resistors primarily depends on the rise time ($t_r$) and fall time ($t_f$) of CMV. For efficient results, the $t_r$ and $t_f$ of the push–pull MOSFETs should be much lower than the rise time of inverter switches. To achieve this, the input capacitance ($C_{iss}$) and sensing resistors should be appropriately selected. The approximate relation between the $C_{iss}$ and input resistance is as follows:

$${\mathrm{t}}_{\mathrm{r}}\approx 2.2\mathrm{R}\times {\mathrm{C}}_{\mathrm{i}\mathrm{s}\mathrm{s}}$$

(8)

$${\mathrm{t}}_{\mathrm{f}}\approx \mathrm{R}\times {\mathrm{C}}_{\mathrm{i}\mathrm{s}\mathrm{s}}\mathrm{l}\mathrm{n}(1+{\displaystyle \frac{{\mathrm{V}}_{\mathrm{d}\mathrm{s}}}{{\mathrm{V}}_{\mathrm{g}\mathrm{s}\left(\mathrm{t}\mathrm{h}\right)}}}).$$

(9)

The selection of the resistor value involves a trade-off between losses and efficiency. A lower resistor value will increase $I^{2}R$ losses due to the high current. Conversely, using a very high resistor value would result in a significant voltage difference during switching between the CMV at the RCMV. For this paper, a resistor value of 10 kΩ was selected to minimize $I^{2}R$ losses and ensure a lower voltage difference during switching.

3.2. Push–Pull MOSFETs

A pair of complementary MOSFETs in a push–pull configuration is used in the proposed CMV compensation method. This configuration can be referred to as an amplification circuit as it amplifies the current output. The push–pull circuit with MOSFETs offers several advantages in this compensation method, including the ability to reproduce the CMV, wide frequency bandwidth, high impedance at the MOSFET gate to reduce input current drawn directly from the inverter, and low impedance at the output to magnetize the ITR.

Most of the time, the MOSFETs operate in saturation mode, because $V_{ds}$ > $V_{gs}$ − $V_{th}$ and the drain current depends on the output load (magnetizing current of the ITR).

It should be noted that in standard industrial motor installations, the motor frame is required to be solidly connected to protective earth ground in accordance with IEC standards [42] and equivalent national standards such as NEC requirements [43], to prevent electric shock hazards in the event of insulation failure. The proposed ACC method requires the motor frame to be driven at the RCMV rather than being grounded, which constitutes a deviation from this standard installation practice. Appropriate safety measures including physical enclosure barriers, insulating motor mounts, and surge protection devices between the motor frame and ground must therefore be incorporated into any practical deployment of this circuit, as further discussed in Section 3.6 and Section 6.

It is important to clarify that in this application the complementary MOSFETs do not operate as conventional hard-switching power devices. Unlike switching power converters where MOSFETs are driven fully ON or fully OFF by a gate driver, the MOSFETs in the proposed push–pull stage operate in the saturation (active) region, functioning as source-follower voltage buffers. The gate is driven directly by the detected CMV, and the source output follows the gate potential with a small offset equal to the threshold voltage $V_{th}$. The drain current adjusts continuously to supply the low magnetizing current required by the ITR primary winding. Regarding the Safe Operating Area (SOA): the maximum voltage stress on each MOSFET is limited to approximately half the DC-link voltage (for the 400 V DC-link), while the drain current is limited to the low ITR magnetizing current (target 10 mA), which is well within the SOA of the selected high-voltage MOSFETs (see

Table 1. Absolute maximum ratings of the MOSFETs.

Model No	[V]	[V]	[V]	[mA]	[pF]
TC1550TG-G	±500	±20	±3.5	±20	45

). As a more robust alternative for future industrial implementations, the MOSFET push–pull stage could be replaced by a dedicated high-voltage linear amplifier IC (e.g., a bootstrapped op-amp topology using high-voltage rail-to-rail devices), which offers better-defined SOA guarantees and tighter bandwidth control.

The selection of suitable MOSFETs depends on various factors, such as $V_{dss}$ drain-to-source breakdown voltage; the input capacitance of the MOSFETs ($C_{iss}$), which effects the rise and fall time of the signal as well as the short through current in complementary switches; the threshold voltage $V_{th}$, which is the difference between the original CMV and the RCMV, as in (7); and $V_{gs}$, which should be sufficiently high to protect the MOSFET from breakdown. Table 1 presents the maximum ratings of the selected MOSFETs for this paper.

The steady-state drain current is $I_D={\displaystyle \frac{V_{RCMV}}{X_{Lm}}}\approx {\displaystyle \frac{200 \mathrm{V}}{22 \mathrm{k}\mathsf{\Omega } }}\approx 9.1 \mathrm{m}\mathrm{A}$, with $V_{DS}\approx 200 \mathrm{V}$ (half DC-link), giving a conduction loss of approximately 1.82 W per MOSFET. Switching losses are negligible (~2.8 mW). The worst-case operating point of 200 V/9.1 mA lies comfortably within the TC1550TG-G continuous DC SOA, which is rated up to 500 V with drain currents well above 9.1 mA, confirming sufficient SOA margin under all foreseeable operating conditions.

3.3. DC-Side Capacitor

Excessive current can flow to the isolation transformer due to the presence of DC components in the output voltage of the push–pull amplifier circuit, potentially causing MOSFET breakdown, and can cause core saturation of the ITR. In the proposed compensation circuit, two DC-side capacitors are connected, as shown in Figure 3. These capacitors help remove the DC components and create a neutral or ground point for RCMV at the primary winding of the ITR.

To further enhance DC component removal, a low-frequency blocking capacitor is employed at the output of the push–pull amplifier. This inclusion reduces the required capacitance for the DC-side capacitors while effectively mitigating the DC components. By optimizing the DC-side capacitor values, the circuit achieves a balanced voltage variation at the neutral point, minimizing error voltages in the isolation transformer primary winding. For simulation and experimentation, two 4.7 µF electrolytic capacitors were selected to ensure the effective restriction of voltage variation and enhance the overall stability of the proposed cancellation circuit.

The LFBC and ITR magnetizing inductance form a high-pass network with a series resonant frequency of approximately 60 Hz, resulting in a negligible phase delay of ~0.34° at 10 kHz. At motor start-up, the LFBC charges with a time constant of approximately 117 ms, after which the ACC circuit reaches full steady-state performance with no practical impact since CMC suppression is not critical during the start-up transient. Under load variation, the CMV is governed by the inverter PWM pattern and DC-link voltage rather than the mechanical load, so ACC performance is inherently robust to load transients [44,45].

3.4. ITR with Low-Frequency Blocking Capacitor

The ITR isolates the ACC circuit from the motor and inverter while acting as a damping resistor to compensate for the CMC. Its design involves selecting the core type, magnetizing inductance, and the number of turns. Ferrite cores were chosen for their high magnetic permeability and low core losses, essential for the 10 kHz operating frequency. The core size was determined using the Area Product (AP), with the ETD29/16/10 core selected for its robust performance.

The ITR has two windings on the ETD-type ferrite core. The primary winding, with $n_1$ turns, is connected to the push–pull amplifier output via the LFBC, and the secondary winding is connected to the motor frame through a compensating inductor to mitigate the CMV and eliminate the CMC. The minimum number of turns required to prevent core saturation is calculated using (10),

$${\mathrm{N}}_{\mathrm{m}\mathrm{i}\mathrm{n}}={\displaystyle \frac{{\mathrm{V}}_{\mathrm{r}\mathrm{m}\mathrm{s}}}{4\times \mathrm{f}\times {\mathrm{B}}_{\mathrm{m}\mathrm{a}\mathrm{x}}\times {\mathrm{A}}_{\mathrm{e}}}},$$

(10)

where $N_{min}$ is the minimum number of turns, $V_{rms}$ is the RMS voltage at the primary of the transformer, $f$ is the switching frequency, $B_{max}$ is the maximum flux density of the core, and $A_e$ is the effective area of the core.

For this experiment, 10 mA magnetizing current was chosen, to reduce the losses of both MOSFTs and transformers. The magnetizing inductance is calculated using (11),

$${\mathrm{L}}_{\mathrm{m}}={\displaystyle \frac{{\mathrm{V}}_{\mathrm{r}\mathrm{m}\mathrm{s}}}{\mathsf{\omega }{\mathrm{I}}_{\mathrm{m}}}},$$

(11)

where L_m (350 mH calculated) is the magnetizing inductance and $I_m$ is magnetizing current. For a 350 mH magnetizing inductance, the number of turns required for both primary and secondary windings is calculated using (12):

$$\mathrm{N}=\sqrt{{\displaystyle \frac{{\mathrm{L}}_{\mathrm{m}}{\mathrm{l}}_{\mathrm{m}}}{{\mathsf{\mu }}_0{\mathsf{\mu }}_{\mathrm{r}}{\mathrm{A}}_{\mathrm{e}}}} }.$$

(12)

This results in approximately 305 turns for each winding.

Table 2. Main parameters of ferrite ETD-type core.

Le [mm]	Ae [mm2]	AL [nH]	Bmax [mT]
72.00	76.00	2860	330
The effective magnetic length of core	The effective cross-sectional area	Magnetic permeability	The saturation flux density

summarizes the main parameters of the Ferrite ETD-Type Core.

The LFBC before the primary winding is used to eliminate the low-frequency components in the input current of ITR, particularly the third harmonic component in CMV caused by SVPWM. Figure 6a illustrates the existence of low and high-frequency components in the ITR input current. This can cause core saturation and high current at low frequencies, increasing the operating flux density ($B_{opt}$) beyond $B_{max}.$ The operating flux density is calculated using (13):

$$B_{opt}= {\displaystyle \frac{Vrms}{4\times f\times N\times A_e}} .$$

(13)

At low frequencies, the current can peak at more than saturation limit, as shown in Figure 6a the low frequency current peaks are around 100 mA. Thus, eliminating the low-frequency components is crucial, which can be achieved using LFBC.

In this setup, a 0.03 µF capacitor is placed in series with the primary winding of the ITR. Figure 6a,b shows the simulation results of the ITR primary current before and after adding the LFBC, respectively, effectively demonstrating the elimination of the low-frequency component from the ITR primary current.

3.5. Inductor for Compensation Parasitic Capacitor

Parasitic capacitance between the motor neutral and frame creates a resonance effect with the motor windings, introducing harmonics in the CMV waveform. This leads to discrepancies between the CMV at the motor neutral and the RCMV from the isolation transformer secondary winding. To mitigate these effects, a compensation inductor is connected between the motor frame and the ITR secondary winding. Figure 7a shows the extra spikes in the waveform caused by this resonance, while Figure 7b illustrates the improved waveform after adding the inductor

The inductor value is calculated using the resonance Formula (14),

$$L={\displaystyle \frac{{\left(\raisebox{1ex}{$1$}\!\left/ \!\raisebox{-1ex}{$2\pi f$}\right.\right)}^2}{C}} ,$$

(14)

where f is the switching frequency (10 kHz) and C is the parasitic capacitance (2.4 nF). The calculated inductance is 105 mH. A toroidal core is selected for its magnetic confinement and low EMI characteristics, suitable for the 10 kHz operating frequency.

The chosen core, nanocrystalline CMC025016010H, features high permeability (${\mu }_r$ = 80,000). Using Equation (12), approximately 43 turns are required. This configuration ensures optimal magnetic flux linkage and minimal leakage inductance, effectively compensating for parasitic capacitance in the CMV waveform.

The measured parasitic capacitance of 2.4 nF was obtained at room temperature under no-load conditions with a 1 metre motor cable. In practice, $C_p$ varies with motor temperature (10–20% increase at rated operating temperature, giving a worst-case 2.9 nF), bearing wear (less than 5% variation), and cable length (a 5 m shielded cable adds approximately 0.5–1.5 nF, potentially raising $C_p$ to 3–4 nF). Using the resonance Formula (14), these variations shift the compensating inductor resonant frequency from 10 kHz (at 2.4 nF) to approximately 8.7–9.3 kHz, within the ACC operating bandwidth and without significant performance degradation, since the compensating inductor attenuates over a broad frequency range. For long-cable or high-temperature installations, the inductor value should be recalculated using the measured effective $C_p$.

The proposed ACC circuit connects only to the motor frame and does not modify the inverter phase output voltages, leaving the motor’s electromagnetic characteristics including torque production, flux linkage, efficiency, and thermal performance unaffected. The isolation transformer (ITR) provides galvanic separation between the ACC circuit and the inverter/motor power circuit. The only current drawn from the motor frame is the small ITR secondary winding magnetizing current (approximately 10 mA), which is negligible compared to the rated motor current. The Y-connected sensing resistors (10 kΩ each) draw a small current from the inverter output lines, resulting in a resistive power loss of approximately less than 0.12% of the 1.1 kW motor rating, which is negligible. Therefore, the proposed hardware does not adversely affect the normal operating characteristics of the induction motor.

3.6. Safety Considerations and Practical Deployment

The proposed ACC method requires the motor frame to be connected to the reproduced CMV (RCMV) output of the isolation transformer secondary winding, rather than to protective earth ground. While this is a necessary condition for CMC cancellation, it represents a departure from the grounded-frame requirement of IEC 60034-1 for standard motor installations.

In practical deployment, this conflict can be partially resolved by connecting a high-frequency bypass capacitor ($C_{HF}$) and a low-frequency grounding resistor ($R_{LF})$ in parallel between the motor frame and earth ground. The component values are selected such that:

• At the ACC operating frequency (10 kHz switching frequency and harmonics), $C_{HF}$ presents a sufficiently high impedance; for example,$C_{HF}= 1 \mathrm{n}\mathrm{F}$ gives $Z_C\approx 16 \mathrm{k}\mathsf{\Omega }$ at 10 kHz, so that the high-frequency RCMV applied to the motor frame is not significantly shunted to ground and the CMC cancellation performance is preserved.
• At power frequency (50/60 Hz), $R_{LF}$ (e.g., 10 kΩ to 100 kΩ) provides a high-resistance path from the motor frame to ground. This limits the touch voltage to a safe level in the event of an insulation failure, partially satisfying the intent of IEC 60034-1, while the high impedance at switching frequency maintains the ACC performance.

This soft-grounding approach represents a practical compromise for the industrial deployment of the proposed ACC circuit. The precise values of $C_{HF}$ and $R_{LF}$ should be selected based on the specific motor drive rating and the applicable safety standard requirements of the installation. For full compliance with IEC 60034-1, physical enclosure of the motor in an electrically isolated cabinet inaccessible to personnel during operation is additionally required. These safety measures should be assessed as part of the overall system design and represent an important area for future experimental investigation.

4. Simulation Results

A simulation using PSIM (2024.1) software was conducted to assess the effectiveness of the proposed CMC cancellation method with a 400 V DC-link voltage. As discussed in Section 3.4 (ITR with low-frequency blocking capacitor), the necessity of a LFBC was identified. Figure 6a,b illustrate the input current measurements of the isolation transformer before and after the connection of the LFBC with FFTs, demonstrating its effectiveness with SVPWM. It is evident that the addition of the LFBC to the transformer primary winding eliminates low-frequency components due to the third harmonic component of fundamental frequency in SVPWM, from the current waveform, reducing peaks from 120 mA to 8 mA and preventing core saturation at low frequencies.

Figure 8 shows the RCMV and CMV together, with a zoomed-in section highlighting waveform differences attributable to the rise and fall times at the MOSFET high input capacitance (10 nF), as discussed in Section 2. This discrepancy can be minimized by carefully selecting the sensing resistor and MOSFETs for the push–pull amplifier. As discussed in Section 3.1 (Sensing Resistor), we cannot decrease the size of the sensing resistance due to $I^{2}R$ losses, but we can choose the lower $C_{iss}$ MOSFET. After decreasing the size of $C_{iss}$ to 40 pF, the RCMV waveform chases the CMV almost perfectly, as shown in Figure 9.

Figure 10 illustrates the CMV or motor neutral voltage with SVPWM and SPWM, while Figure 11 depicts the CMC with SVPWM and SPWM before connecting the ACC circuit. Upon connecting the cancellation circuit in the simulation, Figure 12 shows the motor neutral-to-frame voltage waveforms and corresponding FFTs after connecting ACC; the high-frequency component effectively decreases from 400 V p-to-p to 6 V p-to-p, and the low-frequency component remains at 40 v peak with SVPWM, as shown in Figure 13 of the figure. Figure 12b shows the motor neutral-to-frame voltage with SPWM after connecting the ACC. Furthermore, the CMC is reduced to 4 mA peak-to-peak from 1.5 A peak-to-peak for both modulations, SVPWM and SPWM, as shown in Figure 13. By looking at the results in Figure 12 and Figure 13, we can determine that the proposed ACC technique is effective for various PWM techniques to reduce the CMC.

5. Experimental Results

For the experimental setup, an induction motor rated at 1.1 kW and 415 V/60 Hz was driven by a three-phase inverter with a 400 V DC-link to evaluate the effectiveness of the proposed compensation method. Figure 14 illustrates the experimental configuration, comprising a three-phase two-level voltage source inverter, three-phase induction motor, a prototype of the proposed common-mode cancellation circuit, a DC power supply and a Teledyne-LeCroy HD4096 oscilloscope for measurement.

The EMI spectral measurements were obtained using the built-in FFT of a Teledyne-LeCroy HD4096 oscilloscope in a standard laboratory environment. The measurements were conducted in a laboratory environment without a Line Impedance Stabilization Network (LISN) or an electromagnetic shielding chamber. The measurement focus was restricted to the inverter switching frequency of 10 kHz and its lower-order harmonics, which constitute the dominant contribution to conducted common-mode EMI in the system and represent the primary target frequency range of the proposed ACC circuit. These measurements are intended to characterize the time-domain and spectral performance of the ACC circuit at its designed operating frequencies and are not intended as formal EMC compliance measurements per CISPR 11 or IEC 61800-3 [42,46]. Standardized conducted emissions testing with an LISN and the characterization of high-frequency EMI performance above 1 MHz remain directions for future work.

Figure 15a displays the primary current of the ITR and a zoomed waveform without the LFBC installed on the primary winding. Clearly, the current exhibits higher amplitudes at low frequency. The FFT of the TR primary current without the low-frequency blocking capacitor is shown in Figure 15b, where prominent peaks are observed at the low frequency component. To mitigate these low-frequency components, an LFBC was introduced at the input of the primary winding of the isolation transformer. Figure 15c illustrates the primary winding current and its zoomed waveform after the inclusion of the LFBC, revealing that only high-frequency components remain, which are 12 mA peak-to-peak.

Experimental results for the CMV, representing motor neutral-to-frame voltage without ACC and with ACC circuit connecting, are presented in Figure 16 and Figure 17, respectively. It is evident that the high frequency component of motor neutral-to-frame voltage reduces to 30 V peak-to-peak when the cancellation circuit is active, down from 500 V peak-to-peak observed without the cancellation circuit. Results for the CMC before and after adding the ACC circuit are shown in Figure 18 and Figure 19, respectively. It is observed that the proposed method reduces the CMC to 57 mA peak using the cancellation circuit in Figure 19, compared to 2.7 A peak without the cancellation circuit in Figure 18. Figure 20a presents the measured spectrum for the CMC and CMV without the compensation circuit. The frequency range analyzed is 0 kHz to 100 MHz for CMC and 0 kHz to 1 MHz for CMV, using a Teledyne-LeCroy HD4096 oscilloscope. In contrast, Figure 20b illustrates the spectrum when the ACC circuit is connected to the motor frame, demonstrating a significant reduction in both CMC and CMV noise. Specifically, the CMC spectrum at low frequencies is reduced to below −50 dB, while at higher frequencies, it decreases from above −100 dB to nearly −150 dB. Similarly, the CMV spectrum decreases from 165 dBµV to 136 dBµV at low frequencies, with most components reducing from 100 dBµV to below 50 dBµV. These results confirm that the proposed ACC method effectively mitigates high-frequency conducted CM EMI noise.

Table 3. Comparison of the proposed active CMC cancellation method with existing approaches.

Method	CMC Reduction	Extra Power Supply	PWM Compatibility	High Voltage (>200 V DC)	Core Advantage
Ogasawara et al. [29] (1998, active)	High	No	Limited	No (low power only)	First active canceller; limited to low voltage
Di Piazza et al. [30] (2008, improved active)	High	Yes (dedicated)	Limited	Yes (380 V)	Handles higher voltage but requires separate supply
Kim et al. [37] (2024, improved ACC)	>90%	No	Yes	Yes (415 V)	No CM transformer needed; predecessor method
Proposed Method (this work)	97.89%	No	Yes (SVPWM & SPWM)	Yes (400 V DC-link)	LFBC for 3rd harmonic; resistive sensing; no separate supply

compares the proposed method with key existing active CMC cancellation approaches. The proposed method achieves the highest measured CMC reduction (97.89%) among hardware-based methods, while also offering the broadest PWM compatibility and avoiding the need for a separate power supply or a common-mode transformer on the main power lines.

6. Conclusions

In this paper, the design procedure and experimental evaluation of an active CMC cancellation method for induction motor (1.1 kW, 415 V/60 Hz) drive system have been discussed. The proposed method uses a feed-forward system with Y-configured resistors for CMV detection and an active push–pull amplifier with MOSFETs to reproduce and apply the CMV to the motor frame via an isolation transformer. This effectively reduces the potential difference between the motor neutral and frame, significantly mitigating the CMC. By addressing the limitations of conventional ACC methods, the proposed approach meets the requirements of induction motor drives with higher DC-link voltages without any extra power supply. The method performance, validated through PSIM simulations and experimental analysis with a three-phase two-level voltage source inverter, demonstrates its effectiveness in achieving a 97.89% reduction in CMC and substantial EMI mitigation, offering a reliable and scalable solution for high-voltage motor drives.

It should be acknowledged that the proposed ACC method causes the motor frame potential to float at the RCMV level rather than being connected to a fixed ground reference. While this is necessary for CMC cancellation, it represents a practical limitation from the perspective of electrical safety. In standard industrial installations, the motor frame is solidly grounded per IEC 60034 [42] and similar standards to prevent electric shock hazards. In the practical deployment of the proposed method, this limitation must be mitigated through: (1) the physical enclosure of the motor in an electrically isolated cabinet inaccessible to personnel during operation; (2) insulating mounts for the motor frame; and (3) the installation of appropriate overvoltage protection between the floating frame and ground. These safety measures should be implemented as part of the system design and represent an important area for further investigation in future work.