A 39 GHz Phase Shifter in 28 nm FD-SOI CMOS Technology for mm-Wave Wireless Communications

Abstract

This paper presents a 0–360° phase shifter in 28 nm FD-SOI CMOS technology, suitable for radar applications and mm-wave wireless communication systems, which adopt high-efficiency transmitter architectures. It exploits a novel switching vector modulator based on a double-balanced Gilbert cell, which guarantees high-resolution phase control while exhibiting inherently high robustness against process and temperature variations. The phase control is performed by merely changing the currents in the Gilbert cells using digitally controlled current generators. The proposed phase shifter operates at 39 GHz and provides RMS phase and gain errors of 2.7–4.7° and 0.3–0.5 dB, respectively, while drawing 13 mA from a 1 V supply voltage.

1. Introduction

The continuous evolution of wireless communication and sensing systems has driven the need for increasingly stringent performance requirements, particularly in modern radar and communication standards. In communication systems, the adoption of advanced modulation schemes, such as high-order QAM, introduces a high peak-to-average power ratio (PAPR), which directly impacts the transmitter architectures since the requirement of high linearity contrasts with efficiency performance. Consequently, many CMOS transmitters use a high-efficiency non-linear power amplification combined with a technique of amplitude modulation recovery. Typical approaches are the polar modulation [1,2,3] and outphasing [4,5,6], which allow the power amplifier to operate at maximum efficiency.

High power efficiency is crucial in phased array systems. These systems consist of a collection of antenna elements that are properly driven to perform beam forming and beam steering. Specifically, the radiation pattern of each individual element constructively combines with neighboring elements to provide an effective radiation pattern, namely the main lobe, whose direction is controlled by changing the phase of the signal being fed into each antenna element. This allows the signal beam to be electronically steered, improving connection quality and reducing interference [7].

Phase shifters are key circuits for phased array systems since they set the space resolution. In recent years, several monolithic phase shifters have been proposed in the literature, which can be classified into active and passive.

Passive phase shifters exploit passive tunable networks, which guarantee low power consumption and a wide operating band while providing good linearity performance. However, they require power-hungry pre-amplifying drivers to compensate for their high insertion loss. Furthermore, they usually entail a large silicon area occupation due to the use of many passive components, namely inductors and transmission lines [8,9,10,11,12,13]. Conversely, active phase shifters, despite lower linearity and higher power consumption, rely on properly controlled gain stages, which allow output phase adjustment as well as signal amplification with a reduced silicon area occupation. Moreover, an active non-linear phase shifter can be well embedded with a high-efficiency power amplifier to maintain a stable gain and enhance the overall transmitter power efficiency, while reducing phase distortion.

Active phase shifters exploit a vector modulator (VM), which sums two properly weighted quadrature signals to perform the output phase variation [14,15,16], as shown in Figure 1. By adjusting the relative amplitudes of the in-phase and quadrature paths, the VM continuously steers the output phase.

A VM is usually implemented by means of a couple of variable-gain amplifiers driven by two orthogonal (I/Q) input signals. The phase variation is performed by changing the gain of the I/Q paths and summing the two signals at the output. Unfortunately, the accuracy in terms of amplitude and phase of the output signal is greatly affected by process, voltage, and temperature (PVT) variations, since they impact gain and phase difference in the I/Q paths. To overcome this limitation, trimming techniques are proposed at the cost of an increased system complexity [17,18,19], and a switching approach is used to implement the VM [20,21,22]. Specifically, the VGAs in the latter are replaced by a couple of Gilbert cells driven by the I/Q signals and whose bias currents are properly tuned to vary their amplitude and, hence, the resulting output phase. This approach guarantees high robustness against PVT variations since the Gilbert cell is not affected by small changes in the amplitude of the driving I/Q signals.

However, the solution proposed in [20,21,22] relies on a single-balanced Gilbert cell. This cell offers limited isolation between input and output terminals and poor rejection of unwanted signals, making it more susceptible to spurious components and distortions. Consequently, phase accuracy is reduced. To overcome these limitations, a double-balanced fully differential solution is proposed. This solution, thanks to its symmetry, improves isolation, reduces sensitivity to disturbances, and enhances overall linearity. The circuit is designed in a 28 nm FD-SOI CMOS technology and operates over the 37.5–40.5 GHz range, which is a band of interest in modern communication systems. This frequency range is also widely used in automotive radar, where frequency doublers are employed to decouple the local oscillator from the power amplifier, reducing crosstalk and enhancing performance [23]. The circuit provides an output signal whose phase spans from 0° to 360° and is controlled by a 7-bit digital word, resulting in a nominal phase resolution of about 2.8°. Moreover, the proposed phase shifter does not require external calibration, which simplifies the hardware implementation and reduces system-level complexity while maintaining good phase accuracy.

The paper is structured as follows. Section 2 describes the system architecture, Section 3 delves into the circuit design, Section 4 presents the measurement results, and Section 5 draws conclusions.

2. System Architecture

The phase shifter architecture is depicted in Figure 2. The signal flows from the quadrature generator through to the vector modulator, which is controlled by the control current generator, and finally reaches the I-V converter, performed by a resonant load. The quadrature generator provides the two differential quadrature signals, V_I and V_Q, that drive the switching vector modulator. The latter delivers a differential output current, $I_O^{+}-I_O^{-}$, whose phase can be varied while keeping its amplitude constant by changing the values of the control currents, I_I1,_I2 and I_Q1,_Q2, according to a quadrature sinusoidal shape, as described below. These control currents are generated by a mixed analog/digital control current generator driven by the digital word that sets the output signal phase. Finally, a resonant load performs I-V conversion and provides the phase-controlled output voltage.

3. Circuit Design

The design was carried out using a 1 V power supply and a 28 nm FD-SOI CMOS technology with a transition frequency of approximately 300 GHz. This technology adopts a general-purpose back-end-of-line (BEOL), consisting of eight thin copper metal layers and an aluminum top layer. The absence of thick metals poses significant challenges in designing passive components, particularly inductors and transformers. Indeed, larger metals are necessary to reduce series losses, which in turn lead to higher parasitic capacitances and reduced coupling between spirals. This results in a decrease in the resonant frequency, making the design more critical as these factors directly impact gain, area, and power consumption.

3.1. Quadrature Generator

The first building block of the phase shifter is the quadrature generator shown in Figure 3. It provides two differential signals with a 90° phase difference and high enough amplitude to guarantee the switching operation required by the vector modulator. A passive first-order polyphase filter has been adopted as the quadrature generator, since it provides a compact, reliable, and low-loss solution. As is well-known, the passive polyphase filter is implemented by properly combining RC low- and high-pass filters, whose pole frequencies are set equal to the operating frequency to ensure equal attenuation and a 90° phase shift.

The quadrature signals generated by the polyphase filter are fed into the VM input via the integrated transformers, T₁ and T₂. These transformers provide a resonant load for the polyphase filter, achieving high impedance in the operating band. They also provide AC coupling with the VM, avoiding coupling capacitances that are affected by parasitic capacitances. Additionally, the center terminals of the transformers are used for VM input biasing (V_B). The transformers have primary and secondary winding inductances and quality factors equal to 168/155 pH and 14/24, respectively. They have a coupling coefficient of 0.7 and a self-resonant frequency higher than 50 GHz.

3.2. Switching Vector Modulator

The switching vector modulator, shown in Figure 4a, is the core of the phase shifter. It is made up of a couple of double-balanced mixers, which are driven by the differential I/Q signals produced by the quadrature generator. The mixers provide, at their output, four properly weighted currents that are summed to produce the differential output current, $I_O^{+}- I_O^{-}$, which is converted into the output voltage, V_OUT, by the resonant load based on the transformer T₃. V_OUT can be written as follows [24]:

$$V_{OUT}={\displaystyle \frac{2}{\pi }}{R}_P\left(I_{I1}-I_{I2}\right)·\cos \left(2\pi f_{0}t\right)-{\displaystyle \frac{2}{\pi }}{R}_P\left(I_{Q1}-I_{Q2}\right)·\sin \left(2\pi f_{0}t\right)$$

(1)

where R_P is the equivalent parallel loss resistance of the output transformer. Equation (1) can also be expressed as follows:

$$V_{OUT}=A·\mathrm{c}\mathrm{o}\mathrm{s}(2\pi f_{0}t + \phi )$$

(2)

where the amplitude, A, and the phase, φ, are given by (3) and (4), respectively, as follows:

$$A={\displaystyle \frac{2}{\pi }}{R}_P\sqrt{{\left(I_{I1}-I_{I2}\right)}^2+{\left(I_{Q1}-I_{Q2}\right)}^2}$$

(3)

$$\phi =arctan\left({\displaystyle \frac{I_{Q1}-I_{Q2}}{I_{I1}-I_{I2}}}\right)$$

(4)

As apparent from (4), the phase of the output signal can be varied by changing the ratio of the control current differences, $I_{Q1}-I_{Q2}$ and $I_{I1}-I_{I2}$. These currents are generated with a bang-gap current reference and, hence, the phase that depends on current ratio is not affected by absolute process tolerances and temperature variations but only on process mismatches. Moreover, φ does not depend on the amplitude mismatches of the I/Q signals, provided that these signals are high enough to fully switch the Gilbert cells of the vector modulator. To perform the phase variation, control currents I_I1,I2 and I_Q1,Q2 are set as follows:

$$I_{I1}=I_{AV}+I_{MAX}\mathrm{c}\mathrm{o}\mathrm{s}(N·∆\phi )$$

(5)

$$I_{I2}=I_{AV}-I_{MAX}\mathrm{c}\mathrm{o}\mathrm{s}(N·∆\phi )$$

(6)

$$I_{Q1}=I_{AV}+I_{MAX}\mathrm{s}\mathrm{i}\mathrm{n}(N·∆\phi )$$

(7)

$$I_{Q2}=I_{AV}-I_{MAX}\mathrm{s}\mathrm{i}\mathrm{n}(N·∆\phi )$$

(8)

where N is the decoded digital word, ∆φ is the phase resolution, and I_AV and I_MAX are the average value and maximum variation in the VM control currents, respectively. For this design, I_AV and I_MAX were set to 0.6 mA and 1.2 mA, respectively, as a trade-off between power consumption and control current accuracy. Transistors M_1–8, which operate as switches, were implemented as two parallel devices, each with W = 12.6 µm and L = 28 nm to minimize the R_ON resistance and guarantee fast switching.

Substituting (5)–(8) in (3) and (4), A and φ become the following:

$$A={\displaystyle \frac{2}{\pi }}{R}_P·I_{MAX}$$

(9)

$$\phi =N·∆\phi$$

(10)

Therefore, the amplitude of the output signal remains constant, while the phase can be varied linearly with N within the range of 360° with a resolution of ∆φ.

The proposed approach of double-balanced configuration maintains the benefits of isolation and robustness against disturbances over a single-balanced solution, while using the same number of transistors. Finally, Figure 4b shows the layout of the switching VM and the transformer, T₃, including its parameters.

Since the control currents are sinusoidal functions, they can be synthesized by properly using the same four sets of reference current samples, I_CS1–4, for the four quadrants of the entire phase range. For instance, the sets of current samples required for the first, second, and third phase quadrant of I_I1 are the same as those required for the second, third, and fourth phase quadrant of I_Q1, respectively. This property is exploited to reduce the complexity of the control current generator.

3.3. Control Current Generator

The control current generator is shown in Figure 5a. It is composed of four feedback current generator (FCG) units and a control switch array (CSA). The FCGs generate the four sets of reference current samples, I_CS1–4, by multiplying the band-gap current, I_BG, with a transfer factor determined by the ratio of resistances. These resistances are selected in the two resistor strings, R_RS1 and R_RS2, of the FCG. Control currents I_I1,I2 and I_Q1,Q2 of the VM are derived from the reference sample sets, I_CS1–4, using current mirrors that are properly selected with the CSA. The CSA associates each quadrant of a control current to the relative set of reference current samples using a 2-bit control word. To meet the phase resolution target of approximately 2.8°, each 90° phase quadrant requires a set of 32 current samples selected in the resistor strings with a 5-bit word. Consequently, the entire 360° output phase variation can be achieved with a 7-bit digital control, i.e., 2 bits to drive the CSA and, hence, select one of the four sample sets, and 5 bits to select the current sample in the set, both operations for each control current.

To improve the accuracy of the current mirrors, a replica, M_C2,3, of the VM input pair, M_1,2, was used to equalize the drain-source voltages of the mirror transistors, M_C1 and M_I1 in Figure 5a, which were sized with W = 240 µm and L = 500 nm. The resistor string with the selection switches is depicted in Figure 5b. The switches select two resistances, R₁ and R₂, from the two strings composed of a series of unity resistances, r_i. Since R₁ and R₂ are connected between V_DD and the inverting and non-inverting OTA inputs, their voltage drops are equal. Therefore, considering the generation of a generic control current, I_i, we obtain the following results:

$$I_i=I_{BG}·{\displaystyle \frac{R_1}{R_2}}·k$$

(11)

where k is the mirror ratio, which was set to 1. Control currents I_I1,I2 and I_Q1,Q2 are, hence, determined with the accuracy of a band-gap current that can be well stabilized with respect to temperature and power supply variations.

Figure 5c shows the schematic of the transconductance operational amplifier (OTA). It is made of two stages: a differential stage with a resistive load and a stacked mirror transconductance stage. The first stage minimizes offset voltage, while the second stage provides a full single-stage gain, resulting in an overall 56 dB open-loop gain. A replica, M_3,4 and M_7,8, of the two input pairs, M_1,2 and M_5,6, was incorporated in the bias branches to guarantee equal drain-source voltages for the current mirrors, M_11,12 and M_14,15, thereby enhancing their accuracy. This arrangement is required since the low power supply (as low as 1 V) entails a low drain-source voltage for the tail transistors, M₁₂ and M₁₅. The OTA is stabilized with a dominant pole compensation, thanks to the inherent gate-source capacitances provided by M_C1 and M_I1 in Figure 5a. A gain–bandwidth product and a phase margin of 85 MHz and 66° are achieved, respectively.

Finally, the control currents are plotted in Figure 5d. For simplicity, a continuous sinusoidal representation is used instead of the real sequence of discrete values. The colors show how the four sets of reference current samples, I_CS1–4, perform the control currents, I_I1,2, I_Q1,2, in each quadrant of the 360° phase range. As can be seen, currents I_I1,2, I_Q1,2 in the first quadrant correspond to the sets of current samples, I_CS1, I_CS2, I_CS3, I_CS4, respectively. Their correspondence in the second quadrant is instead with I_CS3, I_CS4, I_CS1, I_CS2, and so on. A proper digital decoder operating on the CSA enables the association of control currents with reference current samples to achieve a full-phase variation with a compact solution. This strategy reduces the complexity of resistance and switch arrays, leading to increased phase accuracy and reduced silicon area.

4. Experimental Results

The proposed phase shifter was implemented in a 28 nm FD-SOI CMOS technology by STMicroelectronics (Catania, Italy). A chip microphotograph is shown in Figure 6.

For measurement purposes, input and output terminals of the phase shifter core (PS core) are connected to RF buffers, which are matched to 50 Ω. The phase shifter core area is approximately 0.3 × 0.3 mm², which excludes RF buffers and input and output GSG pads that are used for test purposes. The area occupied by the control current generator is instead 0.3 × 0.8 mm². The chip was assembled on a FR4 printed circuit board (PCB) using the chip-on-board approach, to allow wire bonding for dc and low-frequency pads (i.e., bias terminals and control bits). In contrast, the mm-wave signals are directly fed into the RF pads through a probe station, as shown in Figure 7.

The performance of the phase shifter was comprehensively evaluated by sweeping the 128 phase steps in the 360° phase range and the frequency in the 37.5–40.5 GHz band. Given the massive measurement campaign, a LabView program was arranged to automate the measurement process.

Figure 8a,b shows the measured |S₁₁| and |S₂₂| for all phase states, corresponding to input and output return losses higher than 10 dB in the whole band.

The control currents, I_I1,2, I_Q1,2, evaluated from the measured current samples, I_CS1–4, and the related measured output phase, φ, are shown in Figure 9a and 9b, respectively, as a function of the 7-bit control code. The measured control currents in Figure 9a closely follow the ideal sinusoidal shapes, and the phase shift in Figure 9b varies monotonically with the control code, which is desirable for a predictable phase tuning. The gain under 50 Ω input/output matching conditions is shown in Figure 9c for all phase states. It exhibits minor variation with both the control code and frequency.

The main performance of the phase shifter is assessed with the RMS phase [25] and gain [26] errors, which are plotted in Figure 10a and 10b, respectively, as a function of frequency.

The measured errors in the band of interest lay in the ranges 2.7–4.7° and 0.3–0.5 dB, respectively. The measurements are consistent with simulations. Indeed, measured and simulated RMS phase errors differ by less than 1° and have the same trend with frequency. Measured and simulated RMS gain errors have a discrepancy of about 0.3 dB. The results in Figure 10 also show the impact of a typical power supply variation of ±10% on the RMS phase and gain errors, increasing them by only 5% and 16%, respectively. The small deviations between simulated and measured values, and the small impact of power supply variations on gain and phase accuracy, demonstrate the robustness and accuracy of the proposed phase shifter. Moreover, the adopted architecture is inherently scalable to higher operating frequencies by properly tuning the resonators at the output of the quadrature generator and vector modulator. This makes the approach suitable for future mm-wave applications.

Table 1. Performance summary and comparison with the state-of-the-art phase shifters.

	[17]	[27]	[28]	[29]	[30]	[31]	This work
CMOS technology	28 nm	65 nm	90 nm	65 nm	28 nm	90 nm	28 nm
Frequency band (GHz)	80–100	32–40	26–30	57–67	22–44	25–43	37.5–40.5
Topology	VMPS	VMPS	VMPS	VMPS	VMPS	VMPS	VMPS
Phase control bits	6	7	7	7	7	5	7
Calibration	Yes	Yes	Yes	No	Yes	No	No
Max RMS phase error (°)	2.2	1.6	0.23	2.36	8.5/1 (a)	4.8	4.7
Max RMS gain error (dB)	0.24	0.36	0.14	0.55	0.59	1.4	0.51
Max insertion loss (dB)	9	18	5.1	14	5.8	6.4	3.7
Power consumption (mW)	7.7	Passive	32	Passive	35	43.2	13
Area (mm2)	0.11	0.14	0.73 (b)	0.24	0.19	1.1	0.33 (c)

^(a) Value with phase calibration. ^(b) It also includes PAD area. ^(c) It includes area of PS core and current generator in Figure 6.

compares recent state-of-the-art phase shifters operating in the millimeter-wave frequency range.

The proposed work achieves lower insertion loss, avoiding the need for an additional amplification stage that affects phase accuracy, and consumes less power than most reported implementations. The RMS phase error is higher compared to some previous works, although some of them, such as [30], benefit from calibration that reduces the RMS phase error, but at the cost of increased hardware complexity.

5. Conclusions

A 7-bit phase shifter in the 39 GHz band was presented, which was implemented in a 28 nm FD-SOI CMOS technology. The phase shifter core is made up of a quadrature generator based on a polyphase filter and a switching vector modulator adopting a double-balanced Gilbert cell to enhance input/output isolation, thereby improving accuracy. The output phase is determined by adjusting the values of four control currents, which are generated by a control current generator that is digitally controlled by a 7-bit word. The phase shifter dissipates 13 mW from a 1 V power supply. The circuit silicon area is 0.33 mm².

Without calibration, the phase shifter exhibits RMS phase and gain errors in the range of 2.7–4.7° and 0.3–0.5 dB, respectively, within the 3 GHz frequency band from 37.5 GHz to 40.5 GHz. This result demonstrates the accuracy of the proposed solution.