Impact of Electromagnetic Pulses on N-Type MOSFET Reliability: Experimental Insights

Abstract

In power systems, MOSFET devices used in industrial chips exhibit more pronounced degradation when subjected to intense electromagnetic pulses than in conventional environments. Conventional reliability testing methods, which fail to simulate dynamic electromagnetic environments, are unable to accurately assess the changes in device performance under electromagnetic interference. In this study, we employed a transmission line pulse generator to apply pulse stress to N-type MOSFET devices, systematically investigating the degradation mechanisms by varying pulse features such as pulse cycle, amplitude, rise/fall times, and intervals. The results indicate that changes in the electrical properties of the devices are primarily influenced by two types of charged traps. Under the conditions of low pulse cycles, the current response of the devices may even exceed that prior to stress application. The study further analyzed the competitive mechanisms of these different traps during the device degradation process. Additionally, by varying the test temperature to mimic industrial application scenarios, we analyzed the degradation behavior of the devices under multi-physics conditions.

1. Introduction

The advancements of smart grid systems have driven the demand for efficient multimodal data processing and conversion at intelligent fusion terminals [1,2]. These terminals are often deployed near primary power equipment, where the electromagnetic environment is complex and harsh [3,4,5]. Terminal failures caused by electromagnetic disturbance (EMD) are frequent, with chip failures being an important concern [6]. Generally, EMD propagates through the chip pins, leading to degradation of electronic components, and hence, significantly affecting the safe and stable operation of power equipment.

Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) are of importance, as they constitute the functional units in the CPU and memory chips. In most cases, chip failures can be attributed to transistor degradation [7]. Prior to integration, reliability tests must be conducted to effectively evaluate the lifetime of MOSFETs. A conventional reliability test involves constant voltage stress or gradient stress for accelerated experiments, where voltage stress is systematically applied to the electrodes of MOSFETs to investigate changes in their electrical performance over varied stress durations [8,9]. Under severe EMD, the terminals of MOSFETs are subjected to electromagnetic stress from the environment, accelerating the degradation process and complicating the evaluation of device degradation [10,11,12]. In addition, EMD casts a more significant impact on emerging semiconductor devices, such as ferroelectric MOSFETs. Ferroelectric materials in these devices are particularly susceptible to hysteresis under high electric fields, which introduces unstable nonlinearities between the device gate voltage and internal potential, ultimately compromising the long-term reliability of the device [13].

In power systems, EMD mainly originates from transient electromagnetic pulses generated by equipment like high-voltage switchgear [14,15]. The pulses typically consist of pulse groups resulting from multiple discharge events or breakdowns, with frequencies ranging from 100 kHz to 100 MHz and pulse widths from 10 ns to 10 μs. Such pulses can pass through electrostatic discharge circuits and propagate to the MOSFET terminals [16]. In this study, we revealed the destructive impact of EMD pulses on switching MOSFETs, which are fabricated via typical BCD process. A transmission line pulse (TLP) generator was used to apply square pulses to the gate of the device, for the purpose of EMD simulation. The testing process innovatively incorporated engineering characteristic data to experimentally define the multi-physics environment of the device, enabling the design of a series of reliability tests that replicate real industrial conditions. The degradation of the device was then investigated, by examining the deviation of transfer characteristics. Changes in threshold voltage and mobility were analyzed to reveal the competitive mechanisms of Si–H and Si–O bond breakage in modulating device behavior. A distinct threshold voltage reduction had been observed under a small number of pulse impacts. The degradation of MOSFETs under multi-physics conditions was also elucidated, covering extreme temperatures ranging from −50 °C to 125 °C.

2. Materials and Methods

Standard 5 V N-type MOSFETs (NMOSs), fabricated via a traditional BCD process, were prepared for the experiments. The device structure is illustrated in Figure 1a. The substrate thickness is 775 μm. The channel length and width of the device are 1.2 μm and 10.0 μm, respectively. A reverse-doped well structure is adopted, with Boron implantation concentrations of 10¹³ cm⁻³, 1.5 × 10¹³ cm⁻³, and 2.4 × 10¹² cm⁻³, separately. To mitigate the electric field distribution, the lightly doped drain (LDD) structure is carefully designed, with a Phosphorus concentration of 2.3 × 10¹³ cm⁻³. The source and drain of the device are doped with Phosphorus at 1.5 × 10¹⁴ cm⁻³ and Arsenic at 4.5 × 10¹⁵ cm⁻³. The depths of the drain/source, LDD, and well are measured as 32.6 nm, 69.0 nm, and 261.8 nm, respectively, while the thickness of the gate oxide and poly-silicon layer are 14.5 nm and 200.0 nm, respectively.

After tape-out, the fabricated devices were placed in a cryostat to ensure precise and stable temperature control for the reliability tests. Multiphysics experiments were then conducted. Periodic square pulses were applied to the gate of the devices using a TLP system (ES622, ESDEMC Technology, Rolla, MO, USA), with the pulse waveform shown in Figure 1b. A schematic diagram of the experimental setup is illustrated in Figure 2, where the function of each component can be found in

Table 1. Function of the experimental setup.

No.	Experimental Equipment	Function Description
1	Transmission Line Pulse Generator: ES622, ESDEMC Technology, Rolla, MO, USA	Generation of stress pulses for the whole experiment.
2	Mixed Signal Oscilloscope: MSO-X 3104, Keysight Technologies, Santa Rosa, CA, USA	Characterization of TLP waveform during the experiment.
3	Probe Station: TS3000-SE, MPI Corporation, Mercer, NJ, USA	Providing a stable thermal environment for temperature-controlled device testing.
4	Semiconductor Device Analyzer: B1500A, Keysight Technologies, Santa Rosa, CA, USA	Characterization of devices’ pre- and post-stress electrical performance.

. Given that the gate breakdown voltage of MOSFETs was measured to be 12 V, pulses with an amplitude (V_stress) ranging from 5 V to 11 V were specified during the experiments. To explore the impact of waveforms on device degradation, the duration and duty cycle of the periodic pulses were varied. Experimental details are listed in

Table 2. Reliability tests: multi-physics experiment details.

Experiment No.	Vstress/V	Trise/ns	Tpeak/ns	Tfall/ns	Tinterval/ns	Pulse Cycles	Temperature/°C
1	8	20	150	20	160	105~109	25
2	5~9	20	150	20	160	107	25
3	7	20	150	20	160	103~5 × 108	25
	8	20	150	20	160	103~5 × 108	25
	9	20	150	20	160	103~5 × 108	25
	11	20	150	20	160	103~105	25
4	9	20	150	20	160	104	25
	9	20	150	20	160	107	25
	9	80	150	80	160	104	25
	9	80	150	80	160	107	25
5	9	20	150	20	40~160	105	25
6	7	20	150	20	160	106	−50~125

. Reliability tests were performed on devices under off-state condition, followed by an evaluation of the resulting variations in their DC output characteristics.

3. Results

The reliability of NMOS devices was first evaluated at room temperature, with varied pulse amplitudes and cycles (Experiment No. 1). The rise and fall times (T_rise and T_fall) were fixed at 20 ns, the pulse stress time (T_peak) was set to 150 ns, and the pulse period (T_period) was maintained at 350 ns. Figure 3a shows the degradation of the device’s transfer characteristics (I_d–V_g) at V_stress = 8 V. As the pulse cycles increase from 10⁵ to 10⁹, the drain current gradually decreases, accompanied by an increase in the threshold voltage. This output performance degradation is primarily attributed to carrier injection across the Si–O interface. When electrical pulses reach the gate terminal, electrons in the p-well are attracted by the perpendicular electrical field under the oxide. The electrons gain kinetic energy and penetrate into the oxide layer through field-driven processes such as Poole–Frenkel emission. This energetic injection leads to the breakage of Si–O bonds in the oxide matrix. The resulting broken bonds create charged trap states that subsequently influence carrier transport when the device works, either enhancing carrier scattering in the channel or inducing severe recombination at the interface. Consequently, the drain current is diminished and threshold voltage can be elevated [17,18]. Note that there is a slight current improvement when only 10⁵ pulses are applied to the device, indicating a decrease in threshold voltage.

In Figure 3b, the effect of pulse voltage was analyzed across multiple samples (Experiment No. 2). Due to process variations, NMOS samples exhibit slight differences in performance [19,20]; only samples showing a threshold voltage fluctuation within 50 mV during the wafer acceptance test were selected for the experiment to avoid inconsistency of the results. The relative difference in drain current (ΔI_d) with respect to gate voltage (V_g) was used to evaluate the degradation, representing the drain current deviation between the post-stressed and pristine devices. At fixed 10⁷ pulse cycles, an increase in V_stress from 5 V to 9 V leads to more severe degradation, demonstrating the positive correlation between stress intensity and device degradation. The stress amplitude of 5 V has been proven to cause no observable degradation in device performance, as it falls within the device’s normal operating range.

The current degradation trend in Figure 3a has been extendedly studied. Saturation currents are extracted from each curve at V_g = 5 V. The absolute change in drain current with respect to pulse cycles are shown in Figure 4. From the semi-logarithmic coordinate plot, it is evident that the current degrades logarithmically as pulse cycle increases. In general, degradation processes such as bias temperature instability and time-dependent dielectric breakdown follow power-law regarding time-dependent parameter evolution [7]. These mechanisms are typically associated with Si–H and Si–O bond breakage in the device, respectively. The observed logarithmic current change in the case suggests a more complex degradation mechanism within the device. The results presented in the logarithmic coordinate confirm this phenomenon. Two distinct regions following power-law dependencies are indicated by the dashed lines. Such findings suggest a change in the governing mechanism as the number of pulse cycles increases.

Table 3. Reliability tests: degradation mechanism comparison.

No.	Degradation Topics	Causes	Theoretical Models	Electrical Parameter Deviation with Respect to Time
1	Hot Carrier Injection	Si–O bond breakage caused by the redirection of high-energy carriers from the channel to the oxide.	Hot Carrier Injection Model [21]	Changes follow a power-law relation.
2	Bias Temperature Instability	Si–H bond breakage caused by a hole collection at the heterointerface under a perpendicular gate electric field.	Reaction-Diffusion Model [22]	Changes follow a power-law relation.
3	Time-Dependent Dielectric Breakdown	Si–O bond breakage caused by electron tunneling in the oxide.	Poole–Frenkel Model [23]	Changes follow a power-law relation.
4	This Work	Multi-physical contributions are considered, including both S–H bond and Si–O bond breakages under electrical pulse conditions.	Under Discussion	Changes follow a logarithmic relation.

presents a theoretical comparison between commonly studied degradation topics and this work.

The effect of pulse cycles on the device output characteristics at different V_stress was further explicitly investigated (Experiment No. 3). To quantify the degradation, the shift in threshold voltage (ΔV_th) was examined. The threshold voltage (Vth) was extracted from the transfer characteristics curve at the maximum transconductance and was measured as 0.67 V for 5 V NMOSs [24]. The results are shown in Figure 5a. It is evident that ΔV_th is strongly correlated with both pulse cycles and V_stress, where a higher V_stress and an increased number of pulse cycles lead to more severe degradation. Notably, an inflection point in ΔV_th is observed in the initial stress stage, where Vth first decreases at a few pulse cycles and then increases. The minima of ΔV_th decreases with increasing V_stress and occurs at the lowest pulse cycle count when V_stress = 11 V. Reduced V_stress extends the negative shift in ΔV_th over an increasing number of pulse cycles; however, the minima are barely detected under a V_stress of 7 V.

The increase in Vth is generally attributed to high-energy carrier injection into the gate oxide, as they can stay trapped in the oxide and break Si–O bonds at the Si/SiO₂ interface, generating interface traps that capture electrons and introduce fixed negative charges. In contrast, the breaking of Si–H bonds should be responsible for the reduction in Vth [25]. In a typical BCD process, MOSFETs are usually treated with an annealing process to minimize surface dangling bonds through the formation of Si–H bonds [26,27]. These dangling bonds act as defects that can become positively charged. When carriers are injected into the oxide, relatively weak Si–H bonds can be broken, regenerating the dangling bonds and inducing positive fixed oxide charges. The observed inflection point arises from the trade-off between two competitive mechanisms.

Although the reduction in Vth enhances current outputs, traps accumulate in the device. For MOSFETs operating in the saturation region, the ideal current–voltage relationship can be derived as follows [24]:

$$I_d={\displaystyle \frac{W{\mu }_n{C}_{OX}}{2L}}{\left(V_g-V_{th}\right)}^2,$$

(1)

where W and L denote the device width and channel length, ${\mu }_n$ is the carrier mobility, C_OX is the gate dielectric capacitance, and V_g represents the imposed gate voltage. The transconductance can be conducted as [24]:

$$g_m={\displaystyle \frac{W{\mu }_n{C}_{OX}}{L}}\left(V_g-V_{th}\right)$$

(2)

Given that the gate oxide thickness of fabricated device is 14.5 nm, C_OX is calculated using parallel-plate capacitor formula, yielding approximately 2.38 × 10⁻³ F/m². In essence, since both interface traps and traps within the gate oxide layer are caused by impact carriers, the change trend of the dielectric constant of SiO₂ is consistent with that of carrier mobility. To qualitatively analyze the mobility variation, it is assumed that the gate oxide capacitance of SiO₂ remains unchanged. The carrier mobility is then determined by fitting the change of g_m along with V_g [24]. The degradation of mobility is visualized in Figure 5b. It is clear that the mobility decreases monotonically with the increase in pulse cycles. In addition, the stronger the pulse voltage, the faster the mobility declines. The decrease in mobility originates from trap accumulation, where the monotonic tendency indicates the increasing trap concentration. The presence of the minima in Figure 5a can thus be further explained. The minimum Vth is found when 11 V pulses are imposed on the device, which results from the lower bond dissociation energy of Si–H bonds than that of Si-O bonds, leading to different accumulation rates of various types of traps [28]. Stronger pulse stress promotes the breaking of Si–H bonds, accelerating the accumulation of positive traps around the channel, which triggers Vth minima appearing at a lower pulse count. On the other hand, under 7 V stress, the Vth reduction benefiting from Si–H bond breaking is effectively balanced out, making it difficult to observe.

Considering the various pulse waveforms present in the EMD environment, the effect of T_rise and T_fall of the pulses was explored (Experiment No. 4). Figure 6a,b illustrate the device’s output changes under pulses with different rise/fall edges for pulse cycles of 10⁴ and 10⁷, respectively, with a fixed pulse voltage of 9 V. After exposure to 10⁴ pulses, an increase in device current due to Vth decrease is observed under both 20 ns and 80 ns pulse edge conditions. Compared to the experiment applying 20 ns edge pulses, the current increase is weaker when T_rise = T_fall = 80 ns. This is due to the higher average electric stress of the latter case, giving rise to more Si–O bond breakage and additional negatively charged traps [7]. The overlap of curves near the saturation region suggests that the transfer curve obtained from the 20 ns-edge-pulse experiment is smoother under the influence of high perpendicular electric field around surface and, as discussed above, the device mobility decreases more significantly in this scenario. The reduction in device mobility is mainly attributed to the breaking of Si–H and Si–O bonds. Given that electron trapping and detrapping processes are more pronounced when positively charged traps are present, the device mobility is more significantly affected by Si–H bond breakage than by scattering caused by negatively charged traps originating from Si–O bonds. In this regard, a shorter pulse edge time appears more favorable for Si–H bond breakage. In light of the curve from the 80 ns-edge-pulse experiment, the formation of negatively charged traps due to Si–O bond breakage alters the electric field in the channel and seems to suppress Si–H bond breakage. For devices subjected to 10⁷ pulses on the gate terminal, current degradation occurs under both conditions, with more severe degradation observed under 80 ns edge pulses due to the increased average electric stress level. Moreover, since Si–H bonds are limited at the device interface, the overall degradation can be mostly governed by the concentration of Si–O bond defects in this case [29,30].

Figure 7 reveals the effect of the pulse interval (T_interval) on device degradation, with V_stress set to 9 V and pulse cycles set to 10⁵ (Experiment No. 5). As T_interval extends from 40 ns to 160 ns, the device degradation is notably mitigated. The device recovery effect is generally recognized as a crucial factor in modulating this performance [31]. When the gate stress transitions from high to low, the electric field within the gate oxide weakens. The alternation in the electric field facilitates the release of trapped charges from the gate oxide by lowering the energy required for the charge escape; then the device recovers. A longer pulse interval endows the device with more adequate recovery time, thereby diminishing the extent of device degradation. To this concern, with an interval of 160 ns, the smallest current deviation could be obtained.

Experimental studies related with MOSFET reliability under EMD are typically based on single-pulse stress, focusing on the maximum instantaneous electric field that the device can withstand. Such a method is specifically used to test the electrostatic discharge robustness when a protection semiconductor is fabricated to demonstrate the device’s superior performance [32,33]. In contrast, the experiment here explores the device’s endurance against EMD signals, focusing not only on the waveform characteristics of electromagnetic signals but also on the frequencies and the times. The results reveal that the device’s electrical performance can be complicatedly changed by these signals.

There are reports evidencing that MOSFETs tend to degrade more rapidly under high-temperature conditions [34,35]. To investigate the device reliability in real industrial scenarios, multi-physics experiments were further conducted, with temperatures varying from −50 °C to 125 °C (Experiment No. 6). The results, shown in Figure 8a, present the device transfer characteristics before-stress experiment (BE) and post-stress experiment (PE). The pulse voltage was set to 7 V, and the pulse cycle was set to 10⁶. As the temperature decreases, the current increases. This is because, when the temperature drops, the lattice vibrations in semiconductors are reduced, which in turn lowers the scattering probability of charge carriers and increases carrier mobility. The enhanced mobility facilitates current flow, thus improving device performance. Meanwhile, at lower temperatures, the concentration of intrinsic carriers in semiconductor materials decreases, leading to an increase in the Fermi potential. As the temperature decreases, the Fermi potential increases remarkably. The promoted Fermi potential elevates the threshold voltage [24]. As a result, high threshold voltages can be found in the curves at low temperature test conditions.

Figure 8b shows relative difference in drain current as a function of gate voltage measured at different temperatures. Minimal performance variation is detected when the experiment temperature was set around 25 °C. Similar to the characteristics observed in Figure 6, the device exhibits a moderate current enhancement under low-temperature conditions after limited pulse stress. The overall current variation remains within approximately 1 μA. With temperature rising, device degradation gradually becomes pronounced. The underlying mechanism for the performance shift should be the constant accumulation of negatively charged traps. At low temperatures, the degradation caused by Si–O bond breakage is suppressed owing to the strong bond energy. The device’s electrical shift is predominately governed by the positively charged traps originating from Si–H bond breakage. Specifically, the rapid decrease in current change curve at −50 °C suggests that the degraded device performance can be more influenced by vertical electric fields. The intersection of curves between −50 °C and −25 °C, coupled with the stronger impact of positively charged traps on carrier mobility compared to negative ones, demonstrates relatively higher Si–H bond breakage trap concentration of post-stress device at −50 °C. By contrast, the degradation intensifies at temperatures above 25 °C. The bond energy of Si–O bonds diminishes due to enhanced thermal motion, rendering high-temperature environment more prone to triggering device degradation. This temperature-dependent current variation confirms our above analysis that device degradation is co-modulated by dual defect mechanisms. The disappearance of current enhancement at elevated temperatures suggests that the influence of positively charged traps at the oxide semiconductor interface is limited. For devices in long-term operation, the degradation process dominated by Si–O bond breakage usually continuously worsens as a result of the increased internal thermal stress [36,37].

4. Conclusions

In summary, we systematically investigated the degradation process of 5 V NMOS devices under gate stress induced by transmission line pulses. By varying the pulse cycle, amplitude, rise/fall times, and intervals, the results demonstrate that device degradation can be influenced by charged traps resulting from the bond breakage of Si–H and Si–O at the interface. Under limited pulse cycles, positively charged traps generated by Si–H bond breakage exhibit a modulatory effect on device performance. However, in most cases, negatively charged traps from Si–O bond breakage and electrons trapped in the gate oxide lead to significant degradation. The degradation process is not only recoverable but also temperature sensitive. Shorter pulse intervals and higher experimental temperatures exacerbate the degradation. While this study provides valuable insights into the degradation mechanisms under ideal pulse conditions, real-world EMD often features complex pulse waveforms, like oscillating pulses and multi-peak pulses. The impact of such waveforms on device electrical properties remains a critical area for future research. In addition, EMD pulses superimposed on operational electrode voltages usually act as a catalyst to accelerate the device degradation. Yet, relevant research has not been explored. Our findings lay the groundwork for developing strategies to evaluate the reliability of MOSFETs used in EMD environments and underscore the need for further investigation into the effects of complex pulse profiles on device behavior.