A Review on Direct Digital Conversion Techniques for Biomedical Signal Acquisition

Round 1

Reviewer 1 Report

I have thoroughly reviewed the review article entitled 'A Review on Direct Digital Conversion Techniques for Biomedical Signal Acquisition' and have some suggestions/comments to improve the article as follows:

1) Write the full form of abbriviation such as OSR, ADC, etc. when appearing in the text for the first time.

2) What does it mean, # of channel? If this is a number of channel, you can write 'no. of channel'.

3) I noticed that critical analysis, such as research evaluation, limitations, and the author's own ideas regarding the reviewed articles, is missing. It would greatly enhance the article if you include a paragraph dedicated to these aspects just before the conclusions.

4) It would better if you include common significant parameters of the direct digital conversion techniques in the conclusion.

 

Author Response

Response to Reviewer 1 Comments

 

Point 1: Write the full form of abbriviation such as OSR, ADC, etc. when appearing in the text for the first time.

 

Response 1: We appreciate your suggestion to write the full form of abbreviations such as OSR, ADC, etc. when appearing in the text for the first time. We have incorporated this into the manuscript as follow:

” There are mainly two categories of biomedical signals: bio-potential signals like Electrocardiogram (ECG), Electroencephalogram (EEG) and bio-optical signals like photoplethysmography (PPG), near infrared spectroscopy (NIRS) ”

 “Traditional biopotential signal readouts consist of an AC-coupled preamplifier fol-lowed by an analog to digital converter (ADC) ”

“Figure 3(a) shows a conventional first-order ∆∑ ADC, this circuit has a tradeoff between integrated noise, oversampling rate (OSR), power consumption.”

“A second order hybrid continuous time to discrete time (CT-DT)CT-DT ∆∑-∑modulator [7] was presented as shown in Figure 5.”

 

Point 2: What does it mean, # of channel? If this is a number of channel, you can write 'no. of channel'

 

Response 2: Thank you for pointing out the confusion regarding the # of channel. In this revision, we  used the phrase 'no. of channels' to avoid any confusion. For example:

” NO. of channel”(table 1)

 

Point 3: I noticed that critical analysis, such as research evaluation, limitations, and the author's own ideas regarding the reviewed articles, is missing. It would greatly enhance the article if you include a paragraph dedicated to these aspects just before the conclusions.

 

Response 3: Thank you for your feedback regarding the critical analysis, limitations, and the author's own ideas regarding the reviewed articles. We appreciate your constructive criticism, and we agree that these aspects are crucial for a comprehensive review article. In this revision, we included a dedicated paragraph for critical analysis, limitations, and our own ideas at the comparsion table of each section to provide a more thorough and well-rounded review of the research. In this revision, the description of the table has been improved as follow:

” [6] implements DT ∆-∆∑ structure to eliminate the input DC offset, which achieving rail-to-rail offset tolerance. A high OSR (1000) is needed to reduce kT/C noise. Such high switch frequency with capacitor leads to a limited input impedance(<100MΩ). [7] uses a hybrid CT-DT ∆∑-∑ modulator achieving three stage noise shaping. The low gain (gain=8) stage needs large power consumption (15μW) to reduce input referred noise. The system linearity is limited by 5-bits quantizer and 5-bits CDAC. [8] pro-posed another second-order hybrid DDC architecture which connect the input signal to the second integrator avoiding kT/C noise. This work implements a PDA for high input range and avoiding the requirements of gain. Therefore, the system offers a good tradeoff between noise (<1µVrms) and input range (90dB). However, the input impedance is still relatively low (26MΩ). [9] proposed a op-amp-less ∆-modulator which achieves spectra shaping of low frequency signals to relax the DR requirement. This work has an above GΩ (2.94 GΩ) input impedance because there are no input ca-pacitors. Without an op-amp, system only occupies 0.044mm2. However, without noise shaping, SNDR (60dB) is limited. [11] proposed a current feedback gm stage as the CT-integrator within a ∆^2∑ architecture. A second order noise shaping (OSR=512) is used to achieve low quantization noise. However, flicker noise of current mirror is not chopped so that the noise (2.88µVrms) of system is not low enough. In order to boost input impedance, this work implements bootstrapping first gm stage which lim-ited EDO tolerance (70mV). [12] also uses a gm-c based second stage ∆∑ modulator with bulk driven DSL. It achieves 238 MΩ input impedance with low OSR (136) and small input capacitor (60fF). [13] uses a similar structure achieving low noise (3.9µVrms) with 0.0046 mm2 area.”

“[17] proposed VCO-based neural recording system which works at 1.2V supply. This work achieves good performance on SNDR (76dB) comparing with conventional delta sigma modulator. However, the linearity of system depends on PVT variations of cal-ibration module. [18] presents a closed loop VCO-based system using PFD array as quantizer. With PFD array the system avoid high speed VCO to save power (4.5μW) and area (0.025 mm2). Therefore, the FoM of system is higher than [17]. But the input impedance is not considered. [19] proposed Gm-C-based CT-DSM without chopping. This work has good performance on SNDR (80.4), area (0.078mm2) and input imped-ance (13.3 MΩ@10kHz). However, without chopping the CMRR (76dB) and noise (95nV/√hz) is poor. [20] proposed VCO-based quantizer using DPCM to avoid nonlin-earity. With low OSR (OSR=32), system achieves an SNDR of 89dB consuming 3.2μW. Although other performance is excellent, the input impedance (4 MΩ) is limited by chopper and input capacitor. [21] proposed 3rd-order VCO-based DSM using a pseudo virtual ground to eliminate the large swing at integrator output. This work also achieves good tradeoff between SNDR (92dB) and power(4.4μW), but input imped-ance is poor.”

“[30] proposed a LDC with 8-bits IDAC consisting of pDACs and nDACs. With 10.24% LED duty cycle, the system achieves 92.7dB consuming 8.1uW. Based on [30], [31] proposed second-order LDC. This work gets benefit of lower noise (DR=108.2dB), but consumes higher power(15.1μW). However, both [30] and [31] consume large LED power (1950μW and 264μW). [32] proposed reconfigurable LDC which uses a current integrator and a DAC. This work achieves 119dB DR with 196μW power consumption. Although the power of AFE is high, with lower LED Duty cycle (1%) LED power is lower than [30] and [31]. [33] proposed a hybrid architecture slope LDC to reduce AFE power. This work achieves 134dB DR with only 28μW AFE power.”

 

 

Point 4: It would better if you include common significant parameters of the direct digital conversion techniques in the conclusion.

 

Response 4: We agree with your suggestion to include common significant parameters of the direct digital conversion techniques in the conclusion. To make it more informative, we added this information at the comparsion table of each section as follow:

” [6] implements DT ∆-∆∑ structure to eliminate the input DC offset, which achieving rail-to-rail offset tolerance. A high OSR (1000) is needed to reduce kT/C noise. Such high switch frequency with capacitor leads to a limited input impedance(<100MΩ). [7] uses a hybrid CT-DT ∆∑-∑ modulator achieving three stage noise shaping. The low gain (gain=8) stage needs large power consumption (15μW) to reduce input referred noise. The system linearity is limited by 5-bits quantizer and 5-bits CDAC. [8] pro-posed another second-order hybrid DDC architecture which connect the input signal to the second integrator avoiding kT/C noise. This work implements a PDA for high input range and avoiding the requirements of gain. Therefore, the system offers a good tradeoff between noise (<1µVrms) and input range (90dB). However, the input impedance is still relatively low (26MΩ). [9] proposed a op-amp-less ∆-modulator which achieves spectra shaping of low frequency signals to relax the DR requirement. This work has an above GΩ (2.94 GΩ) input impedance because there are no input ca-pacitors. Without an op-amp, system only occupies 0.044mm2. However, without noise shaping, SNDR (60dB) is limited. [11] proposed a current feedback gm stage as the CT-integrator within a ∆^2∑ architecture. A second order noise shaping (OSR=512) is used to achieve low quantization noise. However, flicker noise of current mirror is not chopped so that the noise (2.88µVrms) of system is not low enough. In order to boost input impedance, this work implements bootstrapping first gm stage which lim-ited EDO tolerance (70mV). [12] also uses a gm-c based second stage ∆∑ modulator with bulk driven DSL. It achieves 238 MΩ input impedance with low OSR (136) and small input capacitor (60fF). [13] uses a similar structure achieving low noise (3.9µVrms) with 0.0046 mm2 area.”

“[17] proposed VCO-based neural recording system which works at 1.2V supply. This work achieves good performance on SNDR (76dB) comparing with conventional delta sigma modulator. However, the linearity of system depends on PVT variations of cal-ibration module. [18] presents a closed loop VCO-based system using PFD array as quantizer. With PFD array the system avoid high speed VCO to save power (4.5μW) and area (0.025 mm2). Therefore, the FoM of system is higher than [17]. But the input impedance is not considered. [19] proposed Gm-C-based CT-DSM without chopping. This work has good performance on SNDR (80.4), area (0.078mm2) and input imped-ance (13.3 MΩ@10kHz). However, without chopping the CMRR (76dB) and noise (95nV/√hz) is poor. [20] proposed VCO-based quantizer using DPCM to avoid nonlin-earity. With low OSR (OSR=32), system achieves an SNDR of 89dB consuming 3.2μW. Although other performance is excellent, the input impedance (4 MΩ) is limited by chopper and input capacitor. [21] proposed 3rd-order VCO-based DSM using a pseudo virtual ground to eliminate the large swing at integrator output. This work also achieves good tradeoff between SNDR (92dB) and power(4.4μW), but input imped-ance is poor.”

“[30] proposed a LDC with 8-bits IDAC consisting of pDACs and nDACs. With 10.24% LED duty cycle, the system achieves 92.7dB consuming 8.1uW. Based on [30], [31] proposed second-order LDC. This work gets benefit of lower noise (DR=108.2dB), but consumes higher power(15.1μW). However, both [30] and [31] consume large LED power (1950μW and 264μW). [32] proposed reconfigurable LDC which uses a current integrator and a DAC. This work achieves 119dB DR with 196μW power consumption. Although the power of AFE is high, with lower LED Duty cycle (1%) LED power is lower than [30] and [31]. [33] proposed a hybrid architecture slope LDC to reduce AFE power. This work achieves 134dB DR with only 28μW AFE power.”

 

Thank you for your suggestion, and we hope that our modified version can meet your expectations.

Author Response File: Author Response.pdf

Reviewer 2 Report

This work shows a review on direct digital conversion techniques for biomedical signal acquisition. The manuscript is interesting and I recommend the following improvements:

• Paragraph 1 of the introduction requires supporting references.
  
  
• Add a brief description of the sections to be found later at the end of the introduction section.
  
  
• Please add references to justify those described in lines 32 to 40.
  
  
• The authors are asked to review and improve the placement of the references in the paper since several paragraphs or sections need to include them. For example, from line 57 to line 70, no reference justifies what is described.
  
  
• In section 2, the taking of EEG signals is briefly mentioned as an example, but it is not specified for which types of biopotentials the developed technologies are. It is essential to highlight and analyze this point since different maximum and minimum electrical parameters must be reached depending on the biopotential in question to ensure signal integrity and patient safety. Therefore, the authors are requested to make this distinction and analyze the works separately, avoiding comparing circuits with different purposes. Suppose all the technologies are focused on the acquisition of EEG signals. In that case, it is suggested to change the title since it currently alludes to a general aspect that does not reflect the specificity of the content. The authors are asked to differentiate between the works analyzed based on the biopotentials for sections 2 and 3.
  
  
• Please verify that all abbreviations are defined.
  
  
• It is necessary to improve the conclusions. Here a detailed analysis of all the information presented should be presented.
  
  
• The sentence “...Multi-electrode neural recordings are becoming standard practice in neuroscience research to gain knowledge on how the brain works and enable neuro-prosthetic applications…” can be exemplified with the following references: Hyperconnected Openings codified in a max tree structure: an application for skull-stripping in brain mri t1; Impact of eeg parameters detecting dementia diseases: a systematic review.

• EMG and sEMG signals are not threatened in the manuscript, please give a brief introduction of them.

• Authors are asked to add a section where they specify their article selection method, what bibliographic bases they used, the exclusion and inclusion criteria, etc.
  
  
• It is necessary to do a deeper search of the literature.

Author Response

Response to Reviewer 2 Comments

 

Point : Paragraph 1 of the introduction requires supporting references.

 

Add a brief description of the sections to be found later at the end of the introduction section.

 

Please add references to justify those described in lines 32 to 40.

 

The authors are asked to review and improve the placement of the references in the paper since several paragraphs or sections need to include them. For example, from line 57 to line 70, no reference justifies what is described.

 

In section 2, the taking of EEG signals is briefly mentioned as an example, but it is not specified for which types of biopotentials the developed technologies are. It is essential to highlight and analyze this point since different maximum and minimum electrical parameters must be reached depending on the biopotential in question to ensure signal integrity and patient safety. Therefore, the authors are requested to make this distinction and analyze the works separately, avoiding comparing circuits with different purposes. Suppose all the technologies are focused on the acquisition of EEG signals. In that case, it is suggested to change the title since it currently alludes to a general aspect that does not reflect the specificity of the content. The authors are asked to differentiate between the works analyzed based on the biopotentials for sections 2 and 3.

 

Please verify that all abbreviations are defined.

 

It is necessary to improve the conclusions. Here a detailed analysis of all the information presented should be presented.

 

The sentence “...Multi-electrode neural recordings are becoming standard practice in neuroscience research to gain knowledge on how the brain works and enable neuro-prosthetic applications…” can be exemplified with the following references: Hyperconnected Openings codified in a max tree structure: an application for skull-stripping in brain mri t1; Impact of eeg parameters detecting dementia diseases: a systematic review.

EMG and sEMG signals are not threatened in the manuscript, please give a brief introduction of them.

Authors are asked to add a section where they specify their article selection method, what bibliographic bases they used, the exclusion and inclusion criteria, etc.

 

It is necessary to do a deeper search of the literature.

 

Response :

 We appreciate your comment on the manuscription.

 

We have added references as follows:

” 39. Chandrakumar, H.; Markovi´c , D. A 2 μW 40 mVpp linear input-range chopper-stabilized bio-signal ampli-fier with boosted input impedance of 300 MΩ and electrode-offset filtering. in IEEE Int.Solid-State Circuits Conf. (ISSCC), Jan./Feb. 2016,pp. 96–97. ”  (See Line74)

 

A brief description of the sections has been added at the end of the introduction section as follows:

” In section 2, we will describe the techniques for implantable signal recording. In section 3, the techniques for voltage-controlled oscillator based signal recording is presented. In section 4, we will discuss techniques for PPG/NIRS signal recording. In section 5, we will conclude the focus of neural signal recording and PPG/NIRS signal recording.”

 

In section 2, we have clarified the biopotentials for which the developed technologies are suitable and differentiate the works analyzed based on the biopotential to avoid comparing circuits with different purposes. We have also reviewed the title to ensure that it reflects the specificity of the content as follows:”Techniques for Implantable Neural Signal Recording ”.

 

Moreover, we have verified that all abbreviations are defined as follows:

” There are mainly two categories of biomedical signals: bio-potential signals like Electrocardiogram (ECG), Electroencephalogram (EEG) and bio-optical signals like photoplethysmography (PPG), near infrared spectroscopy (NIRS) ”

 “Traditional biopotential signal readouts consist of an AC-coupled preamplifier fol-lowed by an analog to digital converter (ADC) ”

“Figure 3(a) shows a conventional first-order ∆∑ ADC, this circuit has a tradeoff between integrated noise, oversampling rate (OSR), power consumption.”

“A second order hybrid continuous time to discrete time (CT-DT)CT-DT ∆∑-∑modulator [7] was presented as shown in Figure 5.”

 

More comprehensive analysis has been added at comparsion table of each section as follows:

” [6] implements DT ∆-∆∑ structure to eliminate the input DC offset, which achieving rail-to-rail offset tolerance. A high OSR (1000) is needed to reduce kT/C noise. Such high switch frequency with capacitor leads to a limited input impedance(<100MΩ). [7] uses a hybrid CT-DT ∆∑-∑ modulator achieving three stage noise shaping. The low gain (gain=8) stage needs large power consumption (15μW) to reduce input referred noise. The system linearity is limited by 5-bits quantizer and 5-bits CDAC. [8] pro-posed another second-order hybrid DDC architecture which connect the input signal to the second integrator avoiding kT/C noise. This work implements a PDA for high input range and avoiding the requirements of gain. Therefore, the system offers a good tradeoff between noise (<1µVrms) and input range (90dB). However, the input impedance is still relatively low (26MΩ). [9] proposed a op-amp-less ∆-modulator which achieves spectra shaping of low frequency signals to relax the DR requirement. This work has an above GΩ (2.94 GΩ) input impedance because there are no input ca-pacitors. Without an op-amp, system only occupies 0.044mm2. However, without noise shaping, SNDR (60dB) is limited. [11] proposed a current feedback gm stage as the CT-integrator within a ∆^2∑ architecture. A second order noise shaping (OSR=512) is used to achieve low quantization noise. However, flicker noise of current mirror is not chopped so that the noise (2.88µVrms) of system is not low enough. In order to boost input impedance, this work implements bootstrapping first gm stage which lim-ited EDO tolerance (70mV). [12] also uses a gm-c based second stage ∆∑ modulator with bulk driven DSL. It achieves 238 MΩ input impedance with low OSR (136) and small input capacitor (60fF). [13] uses a similar structure achieving low noise (3.9µVrms) with 0.0046 mm2 area.”

“[17] proposed VCO-based neural recording system which works at 1.2V supply. This work achieves good performance on SNDR (76dB) comparing with conventional delta sigma modulator. However, the linearity of system depends on PVT variations of cal-ibration module. [18] presents a closed loop VCO-based system using PFD array as quantizer. With PFD array the system avoid high speed VCO to save power (4.5μW) and area (0.025 mm2). Therefore, the FoM of system is higher than [17]. But the input impedance is not considered. [19] proposed Gm-C-based CT-DSM without chopping. This work has good performance on SNDR (80.4), area (0.078mm2) and input imped-ance (13.3 MΩ@10kHz). However, without chopping the CMRR (76dB) and noise (95nV/√hz) is poor. [20] proposed VCO-based quantizer using DPCM to avoid nonlin-earity. With low OSR (OSR=32), system achieves an SNDR of 89dB consuming 3.2μW. Although other performance is excellent, the input impedance (4 MΩ) is limited by chopper and input capacitor. [21] proposed 3rd-order VCO-based DSM using a pseudo virtual ground to eliminate the large swing at integrator output. This work also achieves good tradeoff between SNDR (92dB) and power(4.4μW), but input imped-ance is poor.”

“[30] proposed a LDC with 8-bits IDAC consisting of pDACs and nDACs. With 10.24% LED duty cycle, the system achieves 92.7dB consuming 8.1uW. Based on [30], [31] proposed second-order LDC. This work gets benefit of lower noise (DR=108.2dB), but consumes higher power(15.1μW). However, both [30] and [31] consume large LED power (1950μW and 264μW). [32] proposed reconfigurable LDC which uses a current integrator and a DAC. This work achieves 119dB DR with 196μW power consumption. Although the power of AFE is high, with lower LED Duty cycle (1%) LED power is lower than [30] and [31]. [33] proposed a hybrid architecture slope LDC to reduce AFE power. This work achieves 134dB DR with only 28μW AFE power.”

The selection criteria for our articles are the top issue or top conference articles with high performance in recent years

 

Thank you for your suggestion, and we hope that our modified version can meet your expectations.

 

Author Response File: Author Response.pdf

Reviewer 3 Report

1) The abstract of this manuscript is too general and does not reveal the essence of the work done. The abstract should briefly describe the work performed, giving specific values for the main parameters or indicators of the study;

2) The electronic circuits in Fig. 1 have positive feedback. In classic circuit configurations of active filters and amplifiers of this type, the feedback is negative, and in very rare cases, positive feedback is added;

3) To the captions in Fig. 3, 4, 5, etc. relevant literature sources must be cited. These circuit configurations are well known to a wide range of engineers working in the field;

4) What is the purpose of the comparative analysis given in Table 1 as well as in Table 2. The authors have to analyze in detail the advantages and disadvantages of the circuit configurations under study. Based on the comparative analysis, the authors should define, for example, evaluations and recommendations. In this form, the manuscript lacks scientific innovation.

 

As I have pointed out above in the review - Minor editing of English language required.

Author Response

Response to Reviewer 3 Comments

 

Point 1: The abstract of this manuscript is too general and does not reveal the essence of the work done. The abstract should briefly describe the work performed, giving specific values for the main parameters or indicators of the study;

 

Response 1: We appreciate your comment on the manuscription. To provide a more thorough and well-rounded review of the research, we included a dedicated paragraph for critical analysis, limitations, and our own ideas at the comparsion table of each section. In this revision, the description has been improved as follows:

” [6] implements DT ∆-∆∑ structure to eliminate the input DC offset, which achieving rail-to-rail offset tolerance. A high OSR (1000) is needed to reduce kT/C noise. Such high switch frequency with capacitor leads to a limited input impedance(<100MΩ). [7] uses a hybrid CT-DT ∆∑-∑ modulator achieving three stage noise shaping. The low gain (gain=8) stage needs large power consumption (15μW) to reduce input referred noise. The system linearity is limited by 5-bits quantizer and 5-bits CDAC. [8] pro-posed another second-order hybrid DDC architecture which connect the input signal to the second integrator avoiding kT/C noise. This work implements a PDA for high input range and avoiding the requirements of gain. Therefore, the system offers a good tradeoff between noise (<1µVrms) and input range (90dB). However, the input impedance is still relatively low (26MΩ). [9] proposed a op-amp-less ∆-modulator which achieves spectra shaping of low frequency signals to relax the DR requirement. This work has an above GΩ (2.94 GΩ) input impedance because there are no input ca-pacitors. Without an op-amp, system only occupies 0.044mm2. However, without noise shaping, SNDR (60dB) is limited. [11] proposed a current feedback gm stage as the CT-integrator within a ∆^2∑ architecture. A second order noise shaping (OSR=512) is used to achieve low quantization noise. However, flicker noise of current mirror is not chopped so that the noise (2.88µVrms) of system is not low enough. In order to boost input impedance, this work implements bootstrapping first gm stage which lim-ited EDO tolerance (70mV). [12] also uses a gm-c based second stage ∆∑ modulator with bulk driven DSL. It achieves 238 MΩ input impedance with low OSR (136) and small input capacitor (60fF). [13] uses a similar structure achieving low noise (3.9µVrms) with 0.0046 mm2 area.”

“[17] proposed VCO-based neural recording system which works at 1.2V supply. This work achieves good performance on SNDR (76dB) comparing with conventional delta sigma modulator. However, the linearity of system depends on PVT variations of cal-ibration module. [18] presents a closed loop VCO-based system using PFD array as quantizer. With PFD array the system avoid high speed VCO to save power (4.5μW) and area (0.025 mm2). Therefore, the FoM of system is higher than [17]. But the input impedance is not considered. [19] proposed Gm-C-based CT-DSM without chopping. This work has good performance on SNDR (80.4), area (0.078mm2) and input imped-ance (13.3 MΩ@10kHz). However, without chopping the CMRR (76dB) and noise (95nV/√hz) is poor. [20] proposed VCO-based quantizer using DPCM to avoid nonlin-earity. With low OSR (OSR=32), system achieves an SNDR of 89dB consuming 3.2μW. Although other performance is excellent, the input impedance (4 MΩ) is limited by chopper and input capacitor. [21] proposed 3rd-order VCO-based DSM using a pseudo virtual ground to eliminate the large swing at integrator output. This work also achieves good tradeoff between SNDR (92dB) and power(4.4μW), but input imped-ance is poor.”

“[30] proposed a LDC with 8-bits IDAC consisting of pDACs and nDACs. With 10.24% LED duty cycle, the system achieves 92.7dB consuming 8.1uW. Based on [30], [31] proposed second-order LDC. This work gets benefit of lower noise (DR=108.2dB), but consumes higher power(15.1μW). However, both [30] and [31] consume large LED power (1950μW and 264μW). [32] proposed reconfigurable LDC which uses a current integrator and a DAC. This work achieves 119dB DR with 196μW power consumption. Although the power of AFE is high, with lower LED Duty cycle (1%) LED power is lower than [30] and [31]. [33] proposed a hybrid architecture slope LDC to reduce AFE power. This work achieves 134dB DR with only 28μW AFE power.”

 

Point 2: The electronic circuits in Fig. 1 have positive feedback. In classic circuit configurations of active filters and amplifiers of this type, the feedback is negative, and in very rare cases, positive feedback is added;

 

Response 2: Thank you for bringing this to our attention. We apologize for any confusion or inaccuracies in the manuscript. We have reviewed the electronic circuits in Fig. 1 and make sure that the feedback is appropriately noted as positive or negative based on the circuit configuration. The figure has been revised as follows:

(a)

(b)

Figure 1 (a) Conventional AC-coupled neural amplifiers; (b) Digitally assisted DC-coupled neural amplifiers.

Point 3: To the captions in Fig. 3, 4, 5, etc. relevant literature sources must be cited. These circuit configurations are well known to a wide range of engineers working in the field;

 

Response 3: Thank you for your suggestion. In this revision, we have cited references in the corresponding description paragraphs of Fig. 3, 4, 5, etc, for exmple:

” To the best of the authors knowledge, the first DDC for bio-potential signal readout is proposed by H. Kassiri etc. [6]. Figure 3(a) shows a conventional first-order ∆∑ ADC, this circuit has a tradeoff between integrated noise, oversampling rate (OSR), power consumption. As a result, with an anticipatory design it can satisfy a neural recording front end requirement of bandwidth, noise, power. However, any DC offset from elec-trode can make amplifier saturated.

In order to improve the suppression of electrode DC offset (EDO) while keep a high chain gain, the so-called ∆2∑structure added an additional ∆ stage to the ∆∑modulator as shown in Figure 3(b). As a result, the difference of two consequent input signals is fed into the DDC, which removes the DC component, avoiding inte-grator saturation. The output of the quantizer is thus the derivative of the input signal, and it can be integrated in digital domain to reconstruct the AC component of the original signal. In the feedback path, the DAC and integrator is implemented by a dig-ital controlled charge pump. Although this structure enables EDO rejection in rail-to-rail range, integration using IDAC results in an insufficient ability to track fast transi-ents due to the large time constant of the integrator. Moreover, a DT ∆2∑ADC need a high-oversampling-ratios (OSR) to avoid KT/C noise aliasing at cost of limited input impedance. As a result, the differential-mode signal caused by different high imped-ance of microelectrode will attenuate the ability of immunizing large artifacts.

Figure 4 shows an oOp-amp-less ∆-modulator diagram using a continuous-time ∆-ADC [9] to achieve shaping the spectra of neural signals as LFPs and ECoG, which can decrease the DR requirement of recording front end by more than 30 dB. Mean-while, this structure achieves above GΩ input impedance because it using DC-coupled front end without input capacitors. However, without noise shaping low frequency noise of the system is high so that SNDR is limited.”

 

Point 4: What is the purpose of the comparative analysis given in Table 1 as well as in Table 2. The authors have to analyze in detail the advantages and disadvantages of the circuit configurations under study. Based on the comparative analysis, the authors should define, for example, evaluations and recommendations. In this form, the manuscript lacks scientific innovation.

 

Response 4: We agree with your suggestion on the article. In this revision, to make it more informative, we have added this information at the comparsion table of each section as follows:

” [6] implements DT ∆-∆∑ structure to eliminate the input DC offset, which achieving rail-to-rail offset tolerance. A high OSR (1000) is needed to reduce kT/C noise. Such high switch frequency with capacitor leads to a limited input impedance(<100MΩ). [7] uses a hybrid CT-DT ∆∑-∑ modulator achieving three stage noise shaping. The low gain (gain=8) stage needs large power consumption (15μW) to reduce input referred noise. The system linearity is limited by 5-bits quantizer and 5-bits CDAC. [8] pro-posed another second-order hybrid DDC architecture which connect the input signal to the second integrator avoiding kT/C noise. This work implements a PDA for high input range and avoiding the requirements of gain. Therefore, the system offers a good tradeoff between noise (<1µVrms) and input range (90dB). However, the input impedance is still relatively low (26MΩ). [9] proposed a op-amp-less ∆-modulator which achieves spectra shaping of low frequency signals to relax the DR requirement. This work has an above GΩ (2.94 GΩ) input impedance because there are no input ca-pacitors. Without an op-amp, system only occupies 0.044mm2. However, without noise shaping, SNDR (60dB) is limited. [11] proposed a current feedback gm stage as the CT-integrator within a ∆^2∑ architecture. A second order noise shaping (OSR=512) is used to achieve low quantization noise. However, flicker noise of current mirror is not chopped so that the noise (2.88µVrms) of system is not low enough. In order to boost input impedance, this work implements bootstrapping first gm stage which lim-ited EDO tolerance (70mV). [12] also uses a gm-c based second stage ∆∑ modulator with bulk driven DSL. It achieves 238 MΩ input impedance with low OSR (136) and small input capacitor (60fF). [13] uses a similar structure achieving low noise (3.9µVrms) with 0.0046 mm2 area.”

“[17] proposed VCO-based neural recording system which works at 1.2V supply. This work achieves good performance on SNDR (76dB) comparing with conventional delta sigma modulator. However, the linearity of system depends on PVT variations of cal-ibration module. [18] presents a closed loop VCO-based system using PFD array as quantizer. With PFD array the system avoid high speed VCO to save power (4.5μW) and area (0.025 mm2). Therefore, the FoM of system is higher than [17]. But the input impedance is not considered. [19] proposed Gm-C-based CT-DSM without chopping. This work has good performance on SNDR (80.4), area (0.078mm2) and input imped-ance (13.3 MΩ@10kHz). However, without chopping the CMRR (76dB) and noise (95nV/√hz) is poor. [20] proposed VCO-based quantizer using DPCM to avoid nonlin-earity. With low OSR (OSR=32), system achieves an SNDR of 89dB consuming 3.2μW. Although other performance is excellent, the input impedance (4 MΩ) is limited by chopper and input capacitor. [21] proposed 3rd-order VCO-based DSM using a pseudo virtual ground to eliminate the large swing at integrator output. This work also achieves good tradeoff between SNDR (92dB) and power(4.4μW), but input imped-ance is poor.”

“[30] proposed a LDC with 8-bits IDAC consisting of pDACs and nDACs. With 10.24% LED duty cycle, the system achieves 92.7dB consuming 8.1uW. Based on [30], [31] proposed second-order LDC. This work gets benefit of lower noise (DR=108.2dB), but consumes higher power(15.1μW). However, both [30] and [31] consume large LED power (1950μW and 264μW). [32] proposed reconfigurable LDC which uses a current integrator and a DAC. This work achieves 119dB DR with 196μW power consumption. Although the power of AFE is high, with lower LED Duty cycle (1%) LED power is lower than [30] and [31]. [33] proposed a hybrid architecture slope LDC to reduce AFE power. This work achieves 134dB DR with only 28μW AFE power.”

 

Thank you for your suggestion, and we hope that our modified version can meet your expectations.

Author Response File: Author Response.pdf

Round 2

Reviewer 2 Report

The manuscript can be accepted 

Author Response

We are very happy to hear this news. Thank you for your advice, we have benefited greatly.

Author Response File: Author Response.pdf

Reviewer 3 Report

The reviewer's recommendations are almost not fulfilled in this version of the manuscript. For example, a comment is made in the comparative analysis, given in the tables, but it is not explained what follows from this analysis. It is not clear what the purpose of the comparative analysis is. This has to be clarified by the authors in order for the article to be interesting for potential readers.

 In my opinion, minor editing of the English language is required.

Author Response

Thank you for your feedback on the revised version of the manuscript. We apologize that some of the recommendations were not addressed to your satisfaction. We appreciate your comments regarding the comparative analysis in the tables, and we agree that it needs further clarification. We included a dedicated paragraph for our own ideas after the comparative analysis of each section. In this revision, the description has been improved as follows:

• Table 1 summarizes the performance of state-of-the-art DDC-structured biopotential readout circuits and more conclusive opinions are provided in Line 177-783, page 6, as:

" Overall, compared to DT delta-sigma DDC structure, CT (continuous-time) delta-sigma DDC structure are more favored in neural signal acquisition systems because they do not require a high oversampling ratio and hence avoid noise aliasing. If a large input range is the primary requirement of the system, the preferred approach is to use low gains and ∆∑-∑ structures [8]. When input impedance is of paramount importance, a system without using large in-put capacitance becomes the primary choice [9][11]. When considering the number of acquisition channels limited by chip area, using the Gm-C structure without capacitors as an integrator has advantages, as demonstrated in [12][13]. "

• Some suggestions on using VCO-based neural recording circuits are offered in Line 289-297, page 10, as:

“Compared to the traditional DDC structure, the VCO-based DDC structure can achieve higher SNDR and FOM more easily because it has larger input range and less quantizer power consumption. The linearity of closed-loop structures is better [18-21] compared with the open-loop VCO-based structures in [17]. An obvious advantage of higher-order VCO-based DDC [21] is achieving large input range and high SNDR. When input impedance is the primary requirement, chopper-less designs [17][19] exhibit excel-lent performance at the cost of low frequency noise. When considering the area of the acquisition chip, the hybrid PLL DSM structure proposed in [18] is suitable due to its low VCO center frequency.”

(3) These sentences analyze Both the authors’ suggestions and future trends of PPG acquisition systems are analyzed in sentences Line 420-426, page 15, as:

“In bio-optical signal recording system, the LED power consumption is the main contributor to the system power consumption compared to AFE. Compared to using a one-bit quantizer LDC [30][31] structure, using slope-based LDC [32] and dual-slope-based LDC [33] can greatly reduce LED power consumption by low LED pulse frequency. Furthermore, compared to [32], although the dual- slope-based LDC has higher AFE power consumption, it can provide higher DR while consuming lower LED power.”

Thank you for your suggestion, and we hope that our modified version can meet your expectations.

Author Response File: Author Response.pdf

Round 3

Reviewer 3 Report

In this version of the manuscript, the authors have attempted to respond to the reviewer's questions and recommendations. I propose that this review article be accepted for publication in the journal. Regarding the authors' comment, I note that the circuit configuration in Figure 1 can only work with negative feedback. There are other circuits of this type that also have positive feedback, but for the circuit drawn, the feedback should only be negative, which can provide a linear mode of operation.

Minor editing of English language required