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Journal: J. Low Power Electron. Appl., 2014
Volume: 4
Number: 77
Article:
Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology
Authors:
by
Pooja Batra, Spyridon Skordas, Douglas LaTulipe, Kevin Winstel, Chandrasekharan Kothandaraman, Ben Himmel, Gary Maier, Bishan He, Deepal Wehella Gamage, John Golz, Wei Lin, Tuan Vo, Deepika Priyadarshini, Alex Hubbard, Kristian Cauffman, Brown Peethala, John Barth, Toshiaki Kirihata, Troy Graves-Abe, Norman Robson and add
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Link:
https://www.mdpi.com/2079-9268/4/2/77
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