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J. Low Power Electron. Appl.2014, 4(2), 77-89;https://doi.org/10.3390/jlpea4020077

Journal: Journal of Low Power Electronics and ApplicationsVolume: 4Number: 77

Article: Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

Authors:
Pooja Batra^1,*,
Spyridon Skordas² and
Douglas LaTulipe³
et al.

Link: https://www.mdpi.com/2079-9268/4/2/77

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