Order Article Reprints

Cheng X, Li Y, Zhao F, Chen A, Liu H, Li C, Zhang Q, Yin H, Luo J, Wang W. 4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process. Nanomaterials. 2022; 12(5):889. https://doi.org/10.3390/nano12050889

Cheng, Xiaohong, Yongliang Li, Fei Zhao, Anlan Chen, Haoyan Liu, Chun Li, Qingzhu Zhang, Huaxiang Yin, Jun Luo, and Wenwu Wang. 2022. "4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process" Nanomaterials 12, no. 5: 889. https://doi.org/10.3390/nano12050889

Cheng, X., Li, Y., Zhao, F., Chen, A., Liu, H., Li, C., Zhang, Q., Yin, H., Luo, J., & Wang, W. (2022). 4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process. Nanomaterials, 12(5), 889. https://doi.org/10.3390/nano12050889