A Multiport/Multiphase DC/DC Converter with Coupled Inductors for Hybrid Energy Storage Systems Suitable for Aircraft Applications

Abstract

This paper proposes a low weight hybrid battery–supercapacitor energy storage system interfaced with bidirectional DC/DC converters with high power/current capability for aircraft applications. The supercapacitor converter having high power uses two pairs of interleaved coupled inductors to reduce the overall current ripple whilst increasing the converter’s power density. Due to the sensitive performance to saturation of the coupled inductors, a phase current balancing strategy is proposed to counter the effect current imbalance in the channels that would cause saturation degrading overall performance. A power management strategy (PMS) is implemented along with a low pass filter to separate the supercapacitor high frequency power component reference from the battery low frequency power component; therefore, separating the energy and power requirement for the energy storage system contributing to minimizing its weight whilst ensuring the current/power stresses are correctly handled. The validity of the system design is validated by a series of transient tests is conducted both in a simulation model as well as experimentally.

1. Introduction

In the aviation industry, large power fluctuations during acceleration and regenerative braking impose significant stress on battery cells, restricting their ability to supply or absorb peak power demands and leading to accelerated ageing, reduced efficiency, and shortened lifetime [1]. Hybridizing batteries with supercapacitors (SCs) offers an effective solution to these limitations. SCs exhibit high specific power and fast charge–discharge capability, while batteries provide high specific energy. By allocating transient power demands to the SC, battery stress is reduced, resulting in improved battery lifetime, enhanced system efficiency, and reduced overall energy storage system (ESS) cost [2,3,4]. Hybrid energy storage systems (HESS) are increasingly employed in plug-in hybrid electric vehicles (PHEVs), hybrid electric vehicles (HEVs), and aerospace applications to leverage the complementary characteristics of batteries and supercapacitors (SCs) [5].

The HESS topologies are classified as passive, semi-active, or fully active according to their interface with the DC bus and HESS [6,7,8]. In the passive topology, the battery and SC are directly connected to the DC bus, resulting in a simple, low cost, and compact implementation. However, power sharing is determined by internal impedances, which limits SC utilization and degrades system performance [7,9]. Semi-active topologies employ a bidirectional converter to interface either the battery or the SC, enabling partial control of power flow. Active battery interfacing allows regulation of battery current and improves voltage-matching flexibility, whereas active SC interfacing enables peak power control but leaves the battery subject to current fluctuations [6,7,10]. In fully active topologies, both battery and SCs are independently interfaced through bidirectional converters, providing full control of power flow, improved dynamic performance and enhanced system lifetime [11].

Extensive research has been conducted on DC/DC converter topologies with the objective of minimizing system weight and volume. Among these, bidirectional half-bridge converters that combine buck and boost operating modes are widely adopted in ESS applications due to their simple structure and efficient utilization of power semiconductor devices [12,13]. In such configurations, the low voltage side is interfaced with the ESS, while the high voltage side interfaces with the DC bus. Bidirectional DC/DC converters used in ESS applications are generally classified into isolated and non-isolated topologies [14,15,16]. While isolated converters provide galvanic isolation, non-isolated DC/DC converters are often preferred owing to their reduced circuit complexity, lower cost, smaller weight and volume [14,17,18,19]. However, conventional non-isolated converters are typically limited to low-power applications as increasing power levels lead to higher stress on semiconductor devices and reduced system efficiency [13]. Moreover, the selection of appropriate passive elements together with switching frequency remains a key design challenge in conventional converter architectures. Although higher switching frequencies enable a reduction in passive component size and improved dynamic performance, they also increase switching losses and thermal stress, necessitating careful design trade-offs in high-power applications.

Interleaving techniques using non-coupled inductors have been widely employed to meet the growing demand for high power converters. By operating multiple phases with phase shifting technique, interleaved converters achieve a higher effective switching frequency, enabling a reduction in passive component size and improvement in power density. In addition, interleaving distributes the total current among multiple phases, thereby reducing current stress on individual power semiconductor devices and lowering conduction and switching losses in both active and passive components [20,21,22,23]. Although non-coupled interleaving is relatively straightforward to implement, it requires an increased number of magnetic components as the number of phases grows. Moreover, while increasing the number of interleaved channels reduces the overall current ripple, the resulting improvement becomes marginal beyond a certain number of phases [24,25,26]. To overcome these limitations, coupled inductor interleaved converter topologies have been extensively investigated.

The use of coupled inductors enables a significant reduction in magnetic volume and weight while improving converter performance in terms of current and voltage dynamic response and overall efficiency compared with non-coupled configurations [27,28,29,30,31,32]. That is, sharing of DC flux in the interleaved channel of a coupled inductor enables ripple current cancellation, thereby reducing the inductance per phase value. This, in turn, enables the design of smaller magnetic cores with fewer winding turns, resulting in reduction in core volume, weight, and copper losses. Figure 1 provides a schematic of E-shaped coupled inductor showing the cancellation of DC flux generated by inductor current in each of the interleaved channels. The green line represents the DC flux relating to leakage inductance (${\phi }_{\mathrm{l}\mathrm{k}1},{\phi }_{\mathrm{l}\mathrm{k}2}$) while the yellow line represents the DC flux relating to its mutual inductance (${\phi }_{\mathrm{m}}$) [33].

In multiphase converters employing coupled inductors, the current ripple characteristics are strongly dependent on the coupling coefficient. An increase in the coupling coefficient results in increased phase current ripple under direct coupling, whereas inverse coupling extends the operating range over which phase current ripple reduction can be achieved. In inversely coupled configurations, a lower coupling coefficient is effective in reducing the total input current ripple, while in directly coupled configurations, a higher coupling coefficient contributes to reduced total current ripple.

In interleaved converter topologies employing inversely coupled inductors, the magnetizing inductance affects the switching ripple in the circulating currents caused by the differential mode voltage, while the leakage inductance attenuates the switching ripple of the common-mode current component caused by the common mode voltage whilst the DC flux caused by the common mode/load current component in the two coupled windings cancels out. Proper design and tuning of these inductances are therefore critical to achieving reduced current ripple, improved dynamic performance, and lower current stress on the power semiconductor devices. A high magnetizing inductance mitigates the differential mode switching frequency component by presenting high impedance to the differential mode voltage across interleaved channels [29]. However, the smallest imbalance in the DC common mode current component could saturate the core which means that accurately monitoring the DC flux bias is essential. Conversely, the common mode current, which typically appears at twice the differential mode switching frequency is attenuated by the leakage inductance. When the inherent leakage inductance is insufficient, an external inductor rated for the converter current can be introduced to further suppress the common mode component [30]. For higher-power applications, additional interleaved channels may be employed using multiple coupled inductors with dedicated common mode inductances, enabling further reduction in current ripple and improved system dynamics.

Several studies have investigated hybrid battery–SC ESS employing fully active topologies to achieve enhanced system controllability and power management [34,35,36,37]. Some works have explored the use of coupled inductors in single energy storage systems to improve power density and magnetic component utilization [33,38,39]. A significant portion of the literature focuses on single-channel hybrid battery–SC converters for system operation and energy management [40,41,42,43], which may limit the potential for current ripple reduction and efficiency improvement. Other studies have considered interleaved converter configurations for HESS to enable phase current sharing and reduce current stress across converter channels [34,36,44]. In addition, Refs. [45,46,47] utilized multiport input transformers functioning as interleaved channels for both battery and SC converters to improve power density. More recently, the work reported in [35] employed two-channel coupled inductors for both battery and SC converters to improve current ripple performance and overall efficiency. However, this approach may introduce current imbalance due to the non-ideal characteristics of converter components.

In comparison with existing studies in the literature, this work is employed to meet the mission profile of the Air Race E Sport competition at the University of Nottingham. It proposes the use of two coupled inductors to realize four interleaved channels within the HESS architecture. The current state-of-the-art technology typically employs a four-channel converter with coupled inductor interfaced with the SC ESS due to its peak power demand, while the battery converter is commonly implemented as a single channel because of its relatively low power demand. The proposed configuration aims to improve reduction in current ripple, reduce the size of magnetic components, enable the use of lower current-rated switches, and enhance overall converter efficiency. Furthermore, a phase-balancing control strategy is developed to mitigate current imbalance between interleaved channels arising from the non-ideal behaviour of active and passive components. This strategy is integrated with a power management scheme aimed at ensuring the stability, reliability, and efficiency of the aircraft DC bus system. The effectiveness of the proposed approach is validated through experimental results, demonstrating improved current sharing and stable converter operation. The contribution of this work in comparison to similar studies in the literature is summarized in

Table 1. Contribution of this research work in comparison with other studies in the literature.

Contributions	This Paper	[34]	[35]	[36]	[48]	[44]	[37]	[49]	[50]	[40]	[51]	[3]	[47]
Battery and SC energy storage	✓	✓	✓	✓	*	✓	✓	✓	✓	✓	*	✓	✓
Fully active HESS topology	✓	✓	✓	✓	✓	*	✓	✓	*	✓	✓	✓	✓
Interleaved with coupled inductors	✓	*	*	*	*	*	*	*	*	*	*	*	✓
Mathematical equations	✓	*	✓	✓	*	*	*	✓	✓	✓	✓	✓	✓
Phase balancing strategy	✓	*	*	*	*	*	*	*	*	*	*	*	*
Power management strategy	✓	*	✓	*	✓	*	✓	*	✓	✓	✓	✓	✓
Load profile	✓	*	✓	*	✓	✓	✓	*	✓	✓	✓	✓	✓
Simulation platform	✓	✓	✓	✓	✓	✓	✓	✓	✓	*	✓	✓	✓
Experimental validation	✓	*	✓	*	✓	*	✓	*	*	✓	*	*	✓
Stability performance analysis	✓	✓	✓	✓	✓	✓	✓	*	✓	✓	✓	✓	✓

✓ means contribution is included, * means contribution is not included.

.

This paper is organized into seven sections. Section 2 provides the coupled inductor design criteria and Section 3 describes the hybrid battery–SC converter topology. Section 4 presents the proposed phase current balancing strategy for the SC converter. Section 5 investigates the power management strategy to ensure fast and efficient operation during the charging and discharging of the battery–SC ESS. Section 6 presents the simulation results of the HESS, while Section 7 provides a detailed experimental evaluation. The conclusions of this work are summarized in Section 8.

2. Design Criteria of the Coupled Inductor

The design is based on area product criteria by [30]. The design specifications include a maximum flux density ${\mathrm{B}}_{\mathrm{m}\mathrm{a}\mathrm{x}}$ of 0.4 T, ripple current of 0.8 A, RMS current of 10 A and an operating frequency of 20 kHz. The summary of the calculated parameter values for the coupled inductor is presented in

Table 2. Parameter values of the UI core coupled inductor.

Parameters	Symbol	Value
Magnetic path length	${\mathrm{l}}_{\mathrm{m}\mathrm{a}\mathrm{g}}$	0.258 $\mathrm{m}$
Core area	${\mathrm{A}}_{\mathrm{c}\mathrm{o}\mathrm{r}\mathrm{e}}$	840 ${\mathrm{m}\mathrm{m}}^2$
Core window area	${\mathrm{A}}_{\mathrm{w}\mathrm{i}\mathrm{n}\mathrm{d}}$	1695 ${\mathrm{m}\mathrm{m}}^2$
Total number of turns	${\mathrm{N}}_{\mathrm{t}\mathrm{u}\mathrm{r}\mathrm{n}\mathrm{s}}$	120
Airgap	${\mathrm{i}}_{\mathrm{g}\mathrm{p}\mathrm{a}}$	1.90 $\mathrm{m}\mathrm{m}$
Magnetizing inductance	${\mathrm{L}}_{\mathrm{m}}$	2.12 $\mathrm{m}\mathrm{H}$
Self-inductance	${\mathrm{L}}_{\mathrm{s}1}={\mathrm{L}}_{\mathrm{s}2}$	2.16 $\mathrm{m}\mathrm{H}$
Coupling factor	$\mathsf{\alpha }$	0.96

.

The inverse coupling configuration exhibits reduced phase current ripple compared to directly coupled and uncoupled configurations. When the coupling factor, $\mathsf{\alpha }=0$, the system represents an uncoupled configuration; $\mathsf{\alpha }>0$ indicates direct coupling, while $\mathsf{\alpha }<0$ corresponds to inverse coupling. The equivalent inductance is given as relation between the coupled inductance, ${\mathrm{L}}_{\mathrm{c}\mathrm{p}}$ and the uncoupled inductance ${\mathrm{L}}_{\mathrm{u}\mathrm{c}}$ for the inverse coupling is given in Equation (1) [52,53]. This is expressed in the ratio of coupling inductance to non-coupled inductance and the behaviour of the coupling factor is analyzed for a range of duty cycle from $0\le \mathrm{D}\le 1$.

$${\displaystyle \frac{L_{cp}}{L_{un}}}=\left\{\begin{array}{cc}{\displaystyle \frac{1-{\alpha }^2}{1+\frac{D\alpha }{(1-D)}}}\hfill & 0\le D\le 0.5\\ {\displaystyle \frac{1-{\alpha }^2}{1+\frac{(1-D)\alpha }{D}}}\hfill & 0.5\le D\le 1.0\end{array}\right.$$

(1)

Also, the relation between the ripple current, duty cycle and the converter switching frequency for the uncoupled inductance is:

$$L_{un}={\displaystyle \frac{V_{bus}(1-D)D}{\Delta i_{phase}\times f_{sw}}}$$

(2)

where ${\mathrm{f}}_{\mathrm{s}\mathrm{w}}$ is the switching frequency, and ${\mathrm{L}}_{\mathrm{u}\mathrm{c}}$, ${\mathrm{V}}_{\mathrm{b}\mathrm{u}\mathrm{s}}$, and $\mathrm{D}$ represent the uncoupled inductance, DC bus voltage, and duty cycle, respectively. The term $∆{\mathrm{i}}_{\mathrm{p}\mathrm{h}\mathrm{a}\mathrm{s}\mathrm{e}}$ represents the phase ripple.

A graph of the ratio of coupled to uncoupled inductance against duty cycle is plotted in shown in Figure 2. It shows that the equivalent inductance increases with the increase in duty cycle from 0 to 0.5 and then starts decreasing from 0.5 to 1.0. Also, at $\propto =0$, the equivalent inductance remains at 1, thus implying uncoupled inductor. This analysis highlights the impact of the coupling factor on the selection of an appropriate coupling value for a coupled inductor to achieve effective ripple reduction.

3. Description of the Hybrid Converter Topology

The simplified circuit diagram of the HESS is shown in Figure 3. The circuit consists of two energy storage subsystems, the battery stack sized to meet the energy demand of the mission and the SC stack sized to handle the power peak demand with each being interfaced with the main DC bus via a DC/DC converter to provide a bidirectional power flow between the battery and SC and the 270 V DC bus. Since the battery purpose is to provide the energy requirement and the SC the power requirement which results with a 5.6/1 power and current rating ratio, it was decided to employ fast switching for the SC converter to achieve a significant size reduction in magnetics whilst the battery converter that carries significantly less current was decided to be implemented with Silicon semiconductors embedded in a small size Econopak [54] power module casing. In order to reduce the size and volume of the magnetics and as a result of the high-power/current requirement from the converter specification, the DC/DC converter of the SC needs to split the overall SC current over four paralleled legs, therefore, needing to be connected with two interleaved coupled inductors each having two windings. This will require four half-bridges connected in parallel, thus resulting in eight SiC power modules which then connects to the DC bus. For the battery converter which has a significantly lower power/current requirement, only a single inductor is connected to a single half-bridge converter with a dual IGBT power module connected to the same DC bus. The letters ${\mathrm{L}}_{\mathrm{s}1}$, ${\mathrm{L}}_{\mathrm{s}2}$, ${\mathrm{L}}_{\mathrm{s}3}$ and ${\mathrm{L}}_{\mathrm{s}4}$ denote the self-inductance for each of the coupled inductors; ${\mathrm{L}}_{\mathrm{k}1}$ and ${\mathrm{L}}_{\mathrm{k}2}$ represents the leakage inductances of each coupled inductor, while ${\mathrm{L}}_{\mathrm{b}}$ and ${\mathrm{r}}_{\mathrm{b}}$ are the inductance and ESR of the battery converter respectively. The resistances ${\mathrm{r}}_1$, ${\mathrm{r}}_2$, ${\mathrm{r}}_3$, ${\mathrm{r}}_4$ and ${\mathrm{r}}_{\mathrm{k}1}$, ${\mathrm{r}}_{\mathrm{k}2}$ represents the ESR of the coupled and leakage inductances respectively. Each of the SC channel currents are represented as ${\mathrm{i}}_1$, ${\mathrm{i}}_2$, ${\mathrm{i}}_3$ and ${\mathrm{i}}_4$, with ${\mathrm{i}}_{\mathrm{i}\mathrm{n}}$ being the total input current and ${\mathrm{i}}_{\mathrm{b}\mathrm{a}\mathrm{t}}$ the input current of battery converter. ${\mathrm{S}}_1$–${\mathrm{S}}_8$ and ${\mathrm{S}}_{\mathrm{a}}$, ${\mathrm{S}}_{\mathrm{b}}$ denote the SC converter and battery converter switches respectively. The DC bus voltage is represented as ${\mathrm{V}}_{\mathrm{b}\mathrm{u}\mathrm{s}}$ and ${\mathrm{C}}_{\mathrm{b}\mathrm{u}\mathrm{s}}$ the capacitance of the DC bus while ${\mathrm{C}}_{\mathrm{c}\mathrm{a}\mathrm{p}}$ and ${\mathrm{C}}_{\mathrm{b}\mathrm{a}\mathrm{t}}$ are the input filters of the SC and battery converters respectively.

The switching state of the SC converter is illustrated in Figure 4 with the waveforms representing the SC converter PWM gating signals. As shown in the circuit diagram, each of the four phases in the SC converter consists of two complementary switches: ${\mathrm{S}}_1$ and ${\mathrm{S}}_2$, ${\mathrm{S}}_3$ and ${\mathrm{S}}_4$, ${\mathrm{S}}_5$ and ${\mathrm{S}}_6$, and then ${\mathrm{S}}_7$ and ${\mathrm{S}}_8$. The SC converter operates with eight switching modes within one switching cycle, whereas the battery converter has two operating states. A summary of the SC converter switching states is presented as a truth table in

Table 3. Operating modes of the SC converter.

Time	${\mathbf{S}}_1$	${\mathbf{S}}_2$	${\mathbf{S}}_3$	${\mathbf{S}}_4$	${\mathbf{S}}_5$	${\mathbf{S}}_6$	${\mathbf{S}}_7$	${\mathbf{S}}_8$
${\mathrm{t}}_0-{\mathrm{t}}_1$	1	0	1	0	0	1	1	0
${\mathrm{t}}_1-{\mathrm{t}}_2$	1	0	0	1	0	1	1	0
${\mathrm{t}}_2-{\mathrm{t}}_3$	1	0	0	1	0	1	0	1
${\mathrm{t}}_3-{\mathrm{t}}_4$	1	0	0	1	1	0	0	1
${\mathrm{t}}_4-{\mathrm{t}}_5$	0	1	0	1	1	0	0	1
${\mathrm{t}}_5-{\mathrm{t}}_6$	0	1	1	0	1	0	0	1
${\mathrm{t}}_6-{\mathrm{t}}_7$	0	1	1	0	0	1	0	1
${\mathrm{t}}_7-{\mathrm{t}}_8$	0	1	1	0	0	1	1	0

“1” means switch is ON, “0” means switch is OFF.

. For the single-channel battery converter, switches ${\mathrm{S}}_{\mathrm{a}}$ and ${\mathrm{S}}_{\mathrm{b}}$ operate in a complementary manner when switch ${\mathrm{S}}_{\mathrm{a}}$ is turned on, ${\mathrm{S}}_{\mathrm{b}}$ is turned off, and when switch ${\mathrm{S}}_{\mathrm{a}}$ is turned off, ${\mathrm{S}}_{\mathrm{b}}$ is turned on.

4. Phase Current Balancing Strategy on the Supercapacitor Converter

To achieve the best switching ripple cancellation in the SC converter, the PWM signal is phase shifted equally by $360°/\mathrm{N}$ between successive phases, where $\mathrm{N}$ is the number of interleaved channels generated by using a DSP-FPGA digital control platform. The phase shift sequence is made such that the gate signal for each channel in the coupled inductor is phase shifted by 180° for effective ripple cancellation. The phase shift angles are ${\mathrm{i}}_1$(0°) + ${\mathrm{i}}_2$(180°) and ${\mathrm{i}}_3$(90°) + ${\mathrm{i}}_4$(270°) at a switching frequency of 20 kHz. Each of the switching frequencies at the common point output has an effective switching frequency of 40 kHz for each coupled inductor output. However, with the actual phase shift, there still exist some issues of current imbalance in the converter phases which may result to inductor core saturation and damage of semiconductor device [55]. These imbalances created in the current levels in the different phases of the converter are due to the non-ideal nature of the converter’s active and passive components which leads to imbalances in the parasitic resistances (ESR) and inductances (ESL) or different ${\mathrm{R}}_{\mathrm{D}\mathrm{S}\_\mathrm{o}\mathrm{n}}$ of MOSFETS due to different junction temperatures. The effect of the current imbalance causes higher thermal stress on the converter component of the most loaded phase, thereby generating losses, and also may cause saturation, which means the filtering capability of the inductor is compromised. To solve the issue of the current imbalance, a proposed technique is implemented such that the current imbalance in each interleaved channel is cancelled out.

The block diagram in Figure 5 shows the proposed balancing strategy for the four-channel interleaved coupled converter. From the block diagram, the measured currents in each of the coupled inductor channel are fed to the current balancing block which calculates the current mismatch. The output of the current balancing block is divided by the number of interleaved channels, and this is shared equally to the summation block of the interleaved channels in order to calculate the error. The expression for the output currents from the current balancing block, ${\mathrm{i}}_{\mathrm{c}\mathrm{b}1}$ and ${\mathrm{i}}_{\mathrm{c}\mathrm{b}2}$ are expressed as:

$$i_{cb1}={\displaystyle \frac{i_1-i_2}{(N/2)}};i_{cb2}={\displaystyle \frac{i_3-i_4}{(N/2)}}$$

(3)

where $\mathrm{N}$ is the number of phases, and ${\mathrm{i}}_1$, ${\mathrm{i}}_2$, ${\mathrm{i}}_3$, ${\mathrm{i}}_4$ are the feedback phase currents.

5. Power Management Strategy of the Hybrid DC/DC Converter

The PMS is the most crucial aspect in the design of the bidirectional HESS. The aim is to ensure the power system stability, reliability, and efficiency of the aircraft DC bus system. The bidirectional DC/DC converters ensure fast and efficient operation in the charging and discharging mode of the battery and SC ESS. The idea behind the control strategy is to manage the two ESS by splitting the load power requirement into a slow varying and low magnitude component for the battery and a highly dynamic component for the SC, using the low pass filter (LPF) technique. With the SC operating at high power and low energy phases while the battery operating at low power and high energy phases, the LPF is employed to separate the two power components. The LPF therefore separates the SC high frequency components in the load from the battery low frequency component.

5.1. Traditional Control Strategy

The fundamental concept of this conventional control scheme is to separate the SC converter, which exhibits fast charge and discharge dynamics, from the battery converter, which has slower system dynamics. Figure 6 illustrates the block diagram of the HESS converter control [56]. The cascaded control structure comprises an outer voltage loop regulating the DC bus voltage, and inner loops controlling the currents of the battery and SC converters. The DC bus voltage error, obtained by subtracting the measured DC bus voltage ${\mathrm{V}}_{\mathrm{b}\mathrm{u}\mathrm{s}}$ from its reference ${\mathrm{V}}_{\mathrm{b}\mathrm{u}{\mathrm{s}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}$, is processed by a PI controller to generate the total output current supplied to the input inductors of both converters. A LPF separates the dynamic and average power: the dynamic component serves as the reference current for the SC converter ${\mathrm{i}}_{\mathrm{r}\mathrm{e}\mathrm{f}\_\mathrm{s}\mathrm{c}\mathrm{a}\mathrm{p}}$, while the average component serves as the reference current for the battery converter ${\mathrm{i}}_{\mathrm{r}\mathrm{e}\mathrm{f}\_\mathrm{b}\mathrm{a}\mathrm{t}}$. These reference currents are fed to their respective PI controllers to generate PWM signals for the converter switches.

5.2. Proposed Control Strategy

The primary contribution of this power management control strategy in comparison to conventional approaches lies in its ability to significantly reduce computational burden. This strategy demonstrates enhanced performance in voltage regulation, particularly during transient conditions such as step changes in load power. Furthermore, it achieves lower charge and discharge rates, which mitigates stress on the battery system. This reduction in stress is anticipated to extend the operational lifespan of the battery, thereby improving its long-term reliability and efficiency [57]. The impact of higher current stress on the converter components which may generate losses with potential core saturation is also prevented by the phase balancing strategy.

As shown in the block diagram of the HESS control strategy in Figure 7, the output DC bus voltage is compared with a reference voltage (270 V) and difference between the reference and feedback bus voltage gives the error which is fed to the PI controller of the voltage control loop, then estimates the ESS currents and then power requirement. The output of the PI controller estimates the total DC bus current to be supplied or consumed by the battery and SC converters. The mathematical expression for the total power, ${\mathrm{P}}_{\mathrm{t}\mathrm{o}\mathrm{t}}$ is given in the Equation (4):

$$P_{tot}(t)=P_{bat}(t)+P_{scap}(t)$$

(4)

where ${\mathrm{P}}_{\mathrm{b}\mathrm{a}\mathrm{t}}$ and ${\mathrm{P}}_{\mathrm{s}\mathrm{c}\mathrm{a}\mathrm{p}}$ are the power of the battery and SC respectively.

The high side DC bus current ${\mathrm{i}}_{\mathrm{t}\mathrm{o}\mathrm{t}}$ supplied to the battery and SC is expressed as:

$$i_{tot}(t)={\displaystyle \frac{P_{scap}(t)}{V_{bus}(t)}}+{\displaystyle \frac{P_{bat}(t)}{V_{bus}(t)}}$$

(5)

where ${\mathrm{P}}_{\mathrm{s}\mathrm{c}\mathrm{a}\mathrm{p}}$ is the peak power influenced by the maximum load fluctuations and ${\mathrm{P}}_{\mathrm{b}\mathrm{a}\mathrm{t}}$ is the battery power influenced by average load requirements. The total power is determined from outer loop voltage controller given in the equation:

$$P_{tot}(t)=\left[K_{pv}{V}_{err}(t)+K_{iv}{\displaystyle \underset{0}{\overset{t}{\int }}{V}_{err}(t)}dt\right]V_{bus\_ref}(t)+V_{bus}(t)i_{bus}(t)$$

(6)

$$V_{err}(t)=V_{bu{s}_{ref}}(t)-V_{bus}(t)$$

(7)

where ${\mathrm{K}}_{\mathrm{p}\mathrm{v}}$, ${\mathrm{K}}_{\mathrm{i}\mathrm{v}}$ are the DC bus PI controller parameters, ${\mathrm{V}}_{\mathrm{b}\mathrm{u}{\mathrm{s}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}$ is the reference DC bus voltage required to maintain to DC bus voltage ${\mathrm{V}}_{\mathrm{b}\mathrm{u}\mathrm{s}}$, ${\mathrm{i}}_{\mathrm{b}\mathrm{u}\mathrm{s}}$ is the DC bus current and voltage error ${\mathrm{V}}_{\mathrm{e}\mathrm{r}\mathrm{r}}$ is imputed to the controller.

The total power reference ${\mathrm{P}}_{\mathrm{t}\mathrm{o}\mathrm{t}}$ is passed through the LPF function (${\displaystyle \frac{2\mathsf{\pi }{\mathrm{f}}_{\mathrm{c}}{\mathrm{T}}_{\mathrm{s}}}{1+2\mathsf{\pi }{\mathrm{f}}_{\mathrm{c}}{\mathrm{T}}_{\mathrm{s}}}}$) to separate the high frequency component that corresponds to the load power requirement from the low frequency component that corresponds to the load average energy requirement. The LPF function is the discrete time implementation of the first order LPF used in the control system. It is the same as the ${\displaystyle \frac{{\mathrm{w}}_{\mathrm{c}}{\mathrm{T}}_{\mathrm{s}}}{1+{\mathrm{w}}_{\mathrm{c}}{\mathrm{T}}_{\mathrm{s}}}}$, where ${\mathrm{f}}_{\mathrm{c}}$ is the cut-off frequency and ${\mathrm{T}}_{\mathrm{s}}$ is the sampling time. A power limiter is also incorporated to limit the low frequency power component not to exceed the battery capability during the charge and discharge of the battery.

Let limiter function, ${\mathrm{P}}_{\mathrm{L}\mathrm{i}\mathrm{m}\mathrm{i}\mathrm{t}\mathrm{e}\mathrm{r}}$ representing the battery power constrain the total power, ${\mathrm{P}}_{\mathrm{t}\mathrm{o}\mathrm{t}}$ That is:

$$P_{Limiter}(t)=\mathrm{sat}(P_{tot}(t))$$

(8)

The term $\mathrm{s}\mathrm{a}\mathrm{t}\left({\mathrm{P}}_{\mathrm{t}\mathrm{o}\mathrm{t}}\right(\mathrm{t}\left)\right)$ is expressed as:

$$\mathrm{sat}(P_{tot}(t))=\left\{\begin{array}{l}{P}_{\max },\\ P_{tot}(t),\\ P_{\min },\end{array}\right.\begin{array}{c}{P}_{tot}(t)>P_{\max }\\ P_{\min }\le P_{tot}(t)\le P_{\max }\\ P_{tot}(t)<P_{\max }\end{array}$$

(9)

Therefore, battery reference power, ${\mathrm{P}}_{\mathrm{r}\mathrm{e}{\mathrm{f}}_{\mathrm{b}\mathrm{a}\mathrm{t}}}\left(\mathrm{t}\right)$ in time domain with LPF is expressed as:

$${\displaystyle \frac{d}{dt}}{P}_{re{f}_{bat}}(t)=w_c[P_{Limiter}(t)-P_{re{f}_{bat}}(t)]$$

(10)

where ${\mathrm{w}}_{\mathrm{c}}$ = 2$\mathsf{\pi }{\mathrm{f}}_{\mathrm{c}}$ is the cut-off frequency.

The battery reference power ${\mathrm{P}}_{\mathrm{r}\mathrm{e}\mathrm{f}\_\mathrm{b}\mathrm{a}\mathrm{t}}$ and the reference power of the SC are evaluated in the equation as:

The ${\mathrm{P}}_{\mathrm{r}\mathrm{e}\mathrm{f}\_\mathrm{b}\mathrm{a}\mathrm{t}}$ is divided by the battery voltage and compared with the feedback which is the measured inductor current of the battery converter to generate the current error ${\mathrm{i}}_{\mathrm{e}\mathrm{r}\mathrm{r}\_\mathrm{b}\mathrm{a}\mathrm{t}}$ which is inputted into the PI controller of the battery current as given in equation:

$$i_{err\_bat}(t)={\displaystyle \frac{P_{re{f}_{bat}}(t)}{V_{bat}(t)}}-i_{bat}(t)$$

(11)

On the high frequency component, the SC power reference is determined in Equation (12) as the difference between the total power and the battery reference power. The reference power of the SC, ${\mathrm{P}}_{\mathrm{r}\mathrm{e}\mathrm{f}\_\mathrm{s}\mathrm{c}\mathrm{a}\mathrm{p}}$ divide by the SC voltage, ${\mathrm{V}}_{\mathrm{s}\mathrm{c}\mathrm{a}\mathrm{p}}$ gives the high frequency current component ${\mathrm{i}}_{\mathrm{H}\mathrm{F}}$, as expressed in Equation (13). The SC current reference, ${\mathrm{i}}_{\mathrm{r}\mathrm{e}{\mathrm{f}}_{\mathrm{s}\mathrm{c}\mathrm{a}\mathrm{p}}}$ is achieved by summing the high frequency current component with the feed-forward compensation to support the uncompensated power from the battery due to its slow dynamic response. Also, the equation for the SC current reference, ${\mathrm{i}}_{{\mathrm{r}\mathrm{e}\mathrm{f}}_{\mathrm{s}\mathrm{c}\mathrm{a}\mathrm{p}}}$ is expressed in Equation (14) as:

$$P_{re{f}_{scap}}(t)=P_{tot}(t)-P_{re{f}_{bat}}(t)$$

(12)

$$i_{HF}(t)={\displaystyle \frac{P_{re{f}_{scap}}(t)}{V_{scap}(t)}}$$

(13)

$$i_{re{f}_{scap}}(t)={\displaystyle \frac{V_{bat}(t)}{V_{scap}(t)}}\times i_{err\_bat}(t)+i_{HF}(t)$$

(14)

The current balancing strategy is also implemented as explained previously, to maintain equal channel currents in the interleaved converter. The current error, ${\mathrm{i}}_{\mathrm{e}\mathrm{r}\mathrm{r}\_\mathrm{s}\mathrm{c}\mathrm{a}\mathrm{p}}$ for each of the four-channel currents (${\mathrm{i}}_1$, ${\mathrm{i}}_2$, ${\mathrm{i}}_3$, ${\mathrm{i}}_4$) of the SC are determined by comparing each measured channel current in the SC converter with their respective reference currents. Equation (15) evaluates the error in each of the channels taking into consideration the output balanced currents, ${\mathrm{i}}_{\mathrm{c}\mathrm{b}1}$ and ${\mathrm{i}}_{\mathrm{c}\mathrm{b}2}$:

$$\begin{gathered} i_{err\_scap1}=(i_{re{f}_{scap}}/4)-i_{cb1}-i_1 \\ {i}_{err\_scap2}=(i_{re{f}_{scap}}/4)+i_{cb1}-i_2 \\ {i}_{err\_scap3}=(i_{re{f}_{scap}}/4)-i_{cb2}-i_3 \\ {i}_{err\_scap4}=(i_{re{f}_{scap}}/4)+i_{cb2}-i_4 \end{gathered}$$

(15)

The errors computed in ${\mathrm{i}}_{\mathrm{e}\mathrm{r}\mathrm{r}\_\mathrm{b}\mathrm{a}\mathrm{t}}$ and ${\mathrm{i}}_{\mathrm{e}\mathrm{r}\mathrm{r}\_\mathrm{s}\mathrm{c}\mathrm{a}\mathrm{p}}$ are fed to the PI controllers of the battery and SC converter respectively and their duty ratios are generated. These expressions for the duty ratios of the battery, ${\mathrm{D}}_{\mathrm{b}\mathrm{a}\mathrm{t}}$ and the SC converter legs ${\mathrm{D}}_{1-4}$ are expressed in Equations (16) and (17) respectively.

$$D_{bat}=i_{err\_bat}{\displaystyle \frac{K_{pb}(1+s{T}_{ib})}{s{T}_i}}$$

(16)

$$\begin{gathered} D_1=i_{err\_scap1}{\displaystyle \frac{K_{p,1}(1+s{T}_{i,1})}{s{T}_{i,1}}} \\ {D}_2=i_{err\_scap2}{\displaystyle \frac{K_{p,1}(1+s{T}_{i,1})}{s{T}_{i,1}}} \\ {D}_3=i_{err\_scap3}{\displaystyle \frac{K_{p,1}(1+s{T}_{i,1})}{s{T}_{i,1}}} \\ {D}_4=i_{err\_scap4}{\displaystyle \frac{K_{p,1}(1+s{T}_{i,1})}{s{T}_{i,1}}} \end{gathered}$$

(17)

The parameters of the PI controller, ${\mathrm{K}}_{\mathrm{p}\mathrm{b}}$ and ${\mathrm{T}}_{\mathrm{i}\mathrm{b}}$, represent the proportional gain and integral time constant of the battery converter current controller. Similarly, ${\mathrm{K}}_{\mathrm{p},1}$ and ${\mathrm{T}}_{\mathrm{i},1}$ being the same for both channels represent the proportional gain and integral time constant of the SC converter current controller.

The battery error, ${\mathrm{e}}_{\mathrm{e}\mathrm{r}\mathrm{r}\_\mathrm{b}\mathrm{a}\mathrm{t}}$ to ${\mathrm{D}}_{\mathrm{b}\mathrm{a}\mathrm{t}}$ in Figure 7 is the PI controller with the implementation of a back-calculation anti-windup to regulate the battery converter current. The measured current (${\mathrm{i}}_{\mathrm{b}\mathrm{a}\mathrm{t}}$) is subtracted from the reference current (${\mathrm{i}}_{\mathrm{r}\mathrm{e}\mathrm{f}\_\mathrm{b}\mathrm{a}\mathrm{t}}$) to produce an error signal (${\mathrm{e}}_{\mathrm{e}\mathrm{r}\mathrm{r}\_\mathrm{b}\mathrm{a}\mathrm{t}}$), which is processed through proportional (${\mathrm{K}}_{\mathrm{p}\mathrm{b}}$) and integral (${\mathrm{K}}_{\mathrm{i}\mathrm{b}}$) paths to generate the control action. Under normal operating conditions, the proportional term provides an immediate response to changes in error, while the integral term accumulates the error over time to eliminate steady-state offset and maintain accurate current regulation. When the controller output reaches the saturation limit, the back-calculation anti-windup mechanism becomes active. The difference between the saturated output and the unsaturated controller output is fed back to the integrator input through a feedback path, effectively reducing the integrator accumulation during saturation. This prevents excessive integral buildup (windup), improves transient recovery, and ensures a faster return to stable operation once the controller re-enters the linear region. The back calculation anti-windup technique is also implemented in the SC converter PI controller.

The overvoltage or overshoot and the convergence (settling) time of control system are primarily influenced by the PI controller gains and the controller bandwidth selection. The proportional controller gains provide how quickly the system responds to disturbances or changes in reference while the integral gain helps in eliminating the steady state error in the system. With high proportional gain, the system speed response improves and reduces the time steady state time. However, if the proportional gain is too high, the system becomes unstable. For a high integral gain, the system response will help recover quickly in achieving the steady state after disturbance, but excessive integral gain may lead to high overshoot and long settling time. In addition to the controller gains, the relationship between the bandwidths of the inner and outer control loops is also critical to the overall dynamic performance. In a cascaded control structure, the inner current loops are designed to operate faster than the outer voltage loop to ensure stable operation and proper coordination between the converters.

6. Simulation Results

In order to ensure the stability of the cascaded control structure, the outer-loop PI controller is designed with a slower bandwidth than the inner-loop PI controllers. Owing to the faster charge and discharge capability of the SC, the bandwidth of the SC current control loop is limited to be limited to ${\mathrm{f}}_{\mathrm{s}\mathrm{w}}/4$ of the switching frequency, ${\mathrm{f}}_{\mathrm{s}\mathrm{w}}$ in order to prevent high-frequency oscillations and ensure stable current regulation. In contrast, the battery exhibits slower dynamic characteristics; therefore, the bandwidth of the battery current PI controller is made to be lower than that of the SC current controller and is set to ${\mathrm{f}}_{\mathrm{s}\mathrm{w}}/10$. For the voltage control loop operating at a slower dynamic than the inner-loo current controllers, the bandwidth of the outer voltage control loop is further reduced, limited to approximately ${\mathrm{f}}_{\mathrm{s}\mathrm{w}}/100$. As observed from the simulation waveform in Figure 8b, the DC bus voltage exhibits an overshoot of approximately 10% with a settling time of 13 ms, while the SC current shows an overshoot of about 11% with a settling time of 4 ms. These dynamic responses indicate that the control system remains stable and operates within acceptable performance standards for cascaded control systems.

The results of evaluating the control structure of the HESS converter are shown in Figure 8 as simulated using PLECS software (version 4.8). The HESS is simulated to emulate the proposed mission profile of the aircraft. In the first result of the simulation, the HESS is operated in steady state starting from the take-off phase, then cruising, and finally a descending phase. During the take-off phase where the power consumed is at the maximum (15.7 kW), the SC converter supplies a maximum power of 14 kW with the battery converter supporting a low power level of 1.7 kW at steady state conditions, as shown in Figure 8a. During the cruising and descending phases, where the power demand is low, the battery converter continuously maintains the required power at 1.7 kW while the SC converter power is reduced to zero.

In Figure 8b, the simulation results confirm the capability of the controller to maintain a constant DC bus voltage at 270 V and only demonstrate minor overshoots during the various power step changes, with 10% overshoot within the aircraft requirement [58]. In Figure 8c, it can be noted that there is a sharp voltage discharge initially from the SC during the take-off phase due to having to draw high current, while in Figure 8d the battery voltage is stable due to drawing constant and relatively smaller current throughout the whole flight mission.

In Figure 9, the total current discharged by the SC during the peak demand is 104 A with the interleaved converter contributing to 26 A per channel. For the low power battery converter, a constant current of 12.6 A is discharged from the battery throughout the flight mission while the SC current suddenly reduces to zero in the second part of the simulation as battery is able to supply the full cruising power.

To analyze the efficiency of the converters, the thermal models for the IGBT (from Infineon, Neubiberg, Germany) and SiC (from Wolfspeed, Durham, NC, USA) semiconductor switches were obtained from the manufacturers’ websites in the form of PLECS thermal models. Due to product discontinuation and the unavailability of the specific SiC model (CAS100H12AM1) utilized in this work, the CAS120M12BM2 power module [59] was employed as a substitute. It is important to note that this substitution may introduce discrepancies between the simulation and experimental results due to variations in module specifications. The efficiencies of the SC converter, ${\mathsf{\eta }}_{\mathrm{e}\mathrm{f}{\mathrm{f}}_{\mathrm{S}\mathrm{C}}}$, and the battery converter, ${\mathsf{\eta }}_{\mathrm{e}\mathrm{f}{\mathrm{f}}_{\mathrm{b}\mathrm{a}\mathrm{t}}}$, are expressed as:

$${\eta }_{ef{f}_{SC}}=\left[1-{\displaystyle \frac{P_{Los{s}_{SC}}}{P_{in\_scap}}}\right]\times 100$$

(18)

$${\eta }_{ef{f}_{bat}}=\left[1-{\displaystyle \frac{P_{Los{s}_{bat}}}{P_{in\_bat}}}\right]\times 100$$

(19)

where ${\mathrm{P}}_{\mathrm{L}\mathrm{o}\mathrm{s}{\mathrm{s}}_{\mathrm{S}\mathrm{C}}}$ and ${\mathrm{P}}_{\mathrm{L}\mathrm{o}\mathrm{s}{\mathrm{s}}_{\mathrm{b}\mathrm{a}\mathrm{t}}}$ represents the energy losses of the SC converter and battery converter respectively. The terms ${\mathrm{P}}_{\mathrm{i}\mathrm{n}\_\mathrm{s}\mathrm{c}\mathrm{a}\mathrm{p}}$ and ${\mathrm{P}}_{\mathrm{i}\mathrm{n}\_\mathrm{b}\mathrm{a}\mathrm{t}}$ represents the battery input power and the SC input power respectively.

The aircraft power profile has a maximum power of 4.0 kW during the take-off phase, where the SC converter supplies 3.4 kW while the battery converter supplies 0.6 kW. This generated losses of 42.52 W from the SC converter and 11.19 W from the battery converter with efficiency of the 98.73% and 98.35% respectively. During the cruising and descending phases, the battery discharges continuously at constant power while the SC is completely discharged. Therefore, the losses and efficiency of the battery converter remain the same with the SC completely discharged. A relatively lower efficiency observed in the HESS converter is primarily attributed to the lightly loaded SC converter, where a 100 A SiC device operates at approximately 12% of its rated current capacity, as well as the battery converter employing a 30 A IGBT half-bridge, which operates at about 16% of its rated current capacity. The junction temperatures, conduction losses, and switching losses of the lower switches ${\mathrm{S}}_2$ and ${\mathrm{S}}_{\mathrm{b}}$ in the SC converter and battery converter, respectively, are captured. The recorded waveforms also present the DC bus voltage and the corresponding total converter currents, as illustrated in Figure 10a,b.

7. Experimental Results

The control platform is implemented using TMS320C6713 DSP/FPGA by Texas Instrument (Dallas, TX, USA), and Host Port Interface (HPI) for communication. The DSP operates at a clock frequency of 225 MHz and provides a 32-bit external memory interface shared with the FPGA and a daughter card. Control algorithms are implemented in code composer studio. The daughter card interfaces with the DSP host port to enable code download and bidirectional data exchange between the host PC and the DSP. Both the DSP sampling frequency and the PWM switching frequency are set to 20 kHz. Experimental waveforms are captured using Rohde & Schwarz oscilloscopes developed by Rohde & Schwartz GmbH and Co. (Munich, Germany) with a sampling rate of 2.5 GSa/s. The list of the key components with their parameters is given in

Table 4. Key components used in the experiment.

Component	Description
DSP board	TMS320C6713/FPGA
Optic fibre cables	Transmitters and Receivers
IGBT Module	FS30R06W1E3 (600 V, 30 A IGBT Module (1 Leg used))
SiC Module	CAS100H12AM1 (1.2 kV, 100 A Half-bridge module)
Transducer sensors	LEM Current and Voltage sensors LA 55-P and LV 25-P

and the corresponding specifications of the experimental are given in

Table 5. Component specifications used in the experiment.

Parameters	Values
Input battery voltage: ${\mathrm{V}}_{\mathrm{b}\mathrm{a}\mathrm{t}}$	135 V
SC rated voltage: ${\mathrm{V}}_{\mathrm{s}\mathrm{c}\mathrm{a}\mathrm{p}}$	135 V
Coupled inductance: ${\mathrm{L}}_{\mathrm{s}},$ ${\mathrm{L}}_{\mathrm{m}},$ ${\mathrm{L}}_{\mathrm{l}\mathrm{k}}$	2.16 $\mathrm{m}\mathrm{H},$2.12 µH, 14.0 µH
Common mode inductance: ${\mathrm{L}}_{\mathrm{k}}$	1.50 $\mathrm{m}\mathrm{H}$
Input capacitance: ${\mathrm{C}}_{\mathrm{s}\mathrm{c}\mathrm{a}\mathrm{p}}$	8.0 $\mathsf{\mu }\mathrm{F}$
Inductance of battery converter: ${\mathrm{L}}_{\mathrm{b}\mathrm{a}\mathrm{t}}$	2.5 $\mathrm{m}\mathrm{H}$
Input capacitance: ${\mathrm{C}}_{\mathrm{b}\mathrm{a}\mathrm{t}}$	7.5 $\mathsf{\mu }\mathrm{F}$
DC link voltage and capacitance: ${\mathrm{V}}_{\mathrm{b}\mathrm{u}\mathrm{s}}$ & ${\mathrm{C}}_{\mathrm{b}\mathrm{u}\mathrm{s}}$	270 V, 600 $\mathsf{\mu }\mathrm{F}$
Switching frequency: ${\mathrm{f}}_{\mathrm{s}\mathrm{w}}$	20 kHz
Maximum Load power: ${\mathrm{P}}_{\mathrm{t}\mathrm{o}\mathrm{t}}$	4.0 kW

.

Experimental setup is implemented to validate the proposed hybrid converter system with the experimental setup shown in Figure 11. Due to the limitations of the available laboratory equipment, the power rating was scaled down to a peak power of 4.0 kW, while maintaining the converter’s input and DC bus voltages.

The experimental waveforms for the interleaved channel currents with SC converter under imbalance conditions are supplemented to validate the phase current balance strategy. The interleaved channel currents measured with four current probes for each channel are measured when the converter is operating in open loop condition as shown in Figure 12. The current channels are made unequal by deliberately adding some parasitic resistances in the channel to create unbalance condition between the components. There is a significant variation in the current channels at unbalanced conditions. In coupled inductor 1, ${\mathrm{i}}_1$ and ${\mathrm{i}}_2$ are 5.7 A and 5.2 A respectively. In coupled inductor 2, ${\mathrm{i}}_3$ and ${\mathrm{i}}_4$ are 6.8 A and 7.1 A respectively.

The balanced current control strategy and with the phase shift between the channel currents ${\mathrm{i}}_1$, ${\mathrm{i}}_2$, ${\mathrm{i}}_3$ and ${\mathrm{i}}_4$ are successfully implemented. A current of 6 A in each channel is seen in Figure 13, with a very slight variation in the each of the channel currents. The slight variation is unavoidable, and this could be due to the difference in taking the initial current (at zero) in the sensors and also setting a current zero reading on the four different current probes. Current ripple and sampling time are measured to be 0.76 A and 50.28 $\mathsf{\mu }$s (20 kHz) respectively, thereby validating the simulation results.

Also, Figure 14a provides the block diagram of the setup of the hybrid battery and SC converter interfaced with power supplies. The experiment utilized two bidirectional power supplies (SM1500-CP-30) to serve as inputs for the battery and SC converter power supply and a bidirectional programmable power supply (IT6018C-800-75) is used to act as the output power source, facilitating the generation of the flight mission.

The initial experiment assesses the converter’s performance under steady state conditions in Figure 14b, where a peak power demand of 4.0 kW is observed during the take-off phase in stage 1. Due to the substantial power requirement, the SC storage system discharges a significant power at a maximum current of 25 A, while the battery provides supplementary power at 5 A. The four-channel interleaved configuration on the SC converter equally shares 6.3 A among the channels. In stage 2, corresponding to the aircraft’s cruising and descending phases, the power demand is decreased to 0.6 kW. At this stage, the SC current is reduced to zero while the battery converter continuously supplies power by discharging 5 A average current throughout the mission profile and ensuring the DC bus voltage of the aircraft is maintained at 270 V throughout the mission. The zoomed ripple currents for the battery converter, ${\mathrm{i}}_{\mathrm{b}\mathrm{a}\mathrm{t}}$ and for one of the interleaved channels of the SC converter, ${\mathrm{i}}_1$ during peak and low power conditions are captured, as shown in Figure 14b. The ripple current for the battery converter is measured to be 1.3 A, while the ripple current of the interleaved converter channel is 0.8 A, which is also consistent across the remaining interleaved channels. These ripple values align closely with the simulation results.

The second experiment evaluates the hybrid DC/DC converter performance during transient state under imposed changes in the output current with the resulting waveform shown in Figure 15. The load current is varied using the programmable power supply. Initially, the load current draws 2.4 A at constant power of 0.65 kW for 6 s. The current from the battery converter draws 4.8 A while the SC current is zero. The load demand is suddenly increased from 2.4 A to 7.5 A at 2 kW of power at 6 s. This suddenly decreases the DC bus voltage to the proportion of the increased load current. This demand is supplied by the SC system, thereby discharging its current to maintain the DC bus voltage at 270 V and then diverts the low frequency component to the battery current.

The SC current returned to zero while the battery current is increased to 15 A. At 16 s, the load current is suddenly reduced to 2.5 A from 7.5 A at a constant power of 0.68 kW. The DC bus voltage is increased in proportion to the sudden load demand to maintain the 270 V DC bus. At this point, it is observed the SC current starts approaching zero after a sudden current charging, while the battery current is maintained at 5 A under steady state conditions. The measured DC bus voltage ripple is observed to be 4 V (1.5% of the ${\mathrm{V}}_{\mathrm{b}\mathrm{u}\mathrm{s}}$), also aligning with the design specification for the aircraft DC bus ripple ($\le$6.0 V) [58]. The test also shows the capability of the converter to maintain the regulation of the DC bus voltage at different changes in the output power.

8. Conclusions

This paper provides the simulation of a multiport interleaved DC/DC converter for HESS to power the aircraft throughout its mission profile whilst minimizing the overall weight of ESS by allowing each component to be sized according to the expected demand: the battery for the mission energy demand and the supercapacitor for the mission power peak demands. The power management strategy, being a critical aspect of the design, is implemented to ensure the reliability and stability of the aircraft’s 270 V DC bus system. The power control strategy incorporates a low pass filter to adjust the high-frequency power components to be sourced by the supercapacitor and the low frequency limited power components that comes from the battery according to their expected dynamics. During the take-off phase, the supercapacitor power converter delivers a peak power of 14 kW, while the battery converter supplies a consistent low power of 1.7 kW throughout the mission profiled which matches its maximum power specification, limiting its ageing and improving overall reliability. A reduced scale experimental result is also presented which validated the simulation results.