Design of a High-Gain Common-Grounded ZVT DC-DC Converter with Sustained Soft Switching

Abstract

To address the performance requirements of power interface converters in fuel cell vehicles, a high-voltage gain DC–DC converter with a common-ground structure and zero-voltage-transition (ZVT) operation is proposed. The converter employs two interleaved boost cells in an input-parallel output-series (IPOS) configuration to achieve low input-current ripple and high voltage gain. A single auxiliary circuit enables soft-switching for all switches during turn-on and turn-off, while diodes operate under zero-current switching (ZCS), reducing switching and reverse-recovery losses. In addition, voltage stress across devices is limited to half of the output voltage, allowing the use of lower-rated components. A 1 kW prototype operating at 50 V input and 400 V output at 50 kHz is experimentally validated. The converter achieves efficiency above 92.5%, with a peak of 95.46% and up to 97.41% at higher input voltages, while maintaining stable output performance. These results demonstrate the suitability of the proposed converter for high-efficiency fuel cell-based applications.

1. Introduction

Due to the progressive depletion of conventional fossil fuel reserves and the deterioration of environmental quality, electrified transportation systems have attracted increasing interest. Fuel cells, recognized for their high efficiency and zero-emission characteristics, represent a promising energy source for electric vehicles [1,2]. However, their practical deployment is restricted by several inherent limitations. A single fuel cell generally provides a low output voltage of approximately 1.16 V, necessitating the series connection of many cells to obtain a usable voltage level, an arrangement that may compromise the long-term robustness and operational dependability of the stack [3,4]. Additionally, the output voltage of fuel cells fluctuates significantly with load variations due to their soft output characteristics [5]. Consequently, directly interfacing the fuel cell stack with a DC bus, which typically operates around 400 V in electric vehicle systems, is not feasible. To address this, a dc–dc converter with a high conversion ratio is therefore required to facilitate the connection between the fuel cell and the system’s DC bus [6], as depicted in Figure 1. Moreover, the converter must ensure minimal input-current ripple to prolong the fuel cell’s operational lifespan and incorporate the same ground to both input and output sides to mitigate electromagnetic interference (EMI) and enhance operational stability [7]. Isolated step-up DC–DC converters are capable of achieving high voltage gain primarily through an increase in the transformer turns ratio [8,9,10]. However, in applications such as electric vehicles, where system size and cost are critical considerations, non-isolated transformerless high-gain converters are often preferred. Their reduced hardware requirements and compact design make them more suitable as interface converters under such constraints. The conventional boost converter represents the most fundamental non-isolated topology [11]. While a sufficiently high duty cycle theoretically allows it to achieve large voltage gain, practical limitations such as parasitic effects restrict the achievable gain. Additionally, it is prone to extreme duty ratios, pronounced diode reverse-recovery losses, and hard-switching stress. These drawbacks make the conventional boost converter unsuitable for fuel cell applications.

To improve voltage gain, numerous boosting techniques have been explored [12]. One approach is the switched-inductor topology, as studied in [13,14]. The design in [13] provides a simple configuration with reduced input-current ripple, but the absence of a common ground between input and output can generate significant EMI issues. Conversely, the converter in [14] uses a shared ground but achieves only limited voltage gain. In [15], a switched-capacitor converter is proposed that doubles the output voltage and lowers voltage stress on diodes and capacitors; nevertheless, the switches operate under hard-switching, which constrains efficiency enhancement. Magnetically coupled structures provide another effective approach for boosting voltage, categorized into horizontal [16,17] and vertical [18,19] arrangements depending on the circuit layout. Coupled-inductor converters in [20,21] further enhance voltage gain without extreme duty cycles and enable soft-switching of main switches, though the soft-switching range is limited. In addition, these converters’ complex topologies increase overall size and cost.

For fuel cell vehicle applications, interface converters must exhibit minimal input-current ripple. By employing interleaved configurations, these converters effectively minimize input current variations and reduces current stress on switching elements by distributing the input current across multiple paths [22]. To enhance core utilization, a single coupled inductor with inverse [23] or direct [24] coupling can replace two separate inductors. Nevertheless, these designs still rely on hard switching for active switches. Auxiliary circuits are integrated in [25,26,27] to facilitate soft switching. In particular, the approach presented in [27] reduces the zero-crossing period of the current in the auxiliary circuit by connecting the auxiliary inductor to the primary inductor. However, despite this enhancement, the voltage step-up capacity of these converter designs is still inadequate to fulfill the operational demands of fuel cell systems.

The aforementioned non-isolated DC-DC converter topologies are incapable of simultaneously providing a high voltage conversion ratio, small input-current ripple, and complete soft-switching operation for all semiconductor devices. To address this limitation, this paper proposes a new interleaved converter that integrates the parallel-interleaved technique, flying-capacitor approach, switched-capacitor methodology, and ZVT cell. The proposed converter has the following advantages:

• The main switches S_m1 and S_m2 turn on and off under ZVS, while the auxiliary switch turns on with ZCS and off with ZVS.
• Main output diodes and auxiliary diodes turn off with ZCS, resulting in negligible reverse-recovery losses.
• Voltage stress on all power semiconductors and capacitors is limited to half of the output voltage, reducing switching and conduction losses and improving efficiency and reliability.
• Input-current ripple is minimized through interleaving of two inductors, lowering stress on the fuel cell and enhancing efficiency.
• The converter shares a common ground between input and output, reducing EMI and simplifying system integration.

By combining these advantages in one compact topology, the converter offers an effective alternative to conventional designs that typically compromise between gain, efficiency, and switching performance. The structure of this paper is as follows: Section 2 details the circuit configuration and operational principles of the proposed converter. Section 3 provides a comprehensive analysis of the converter’s characteristics. Subsequently, Section 4 outlines the parameter design methodology and discusses the experimental results. Finally, the conclusion is summarized in Section 5.

2. Operating Principle of the Converter

Figure 2a illustrates the circuit configuration of the proposed converter. The converter is composed of a two-phase interleaved boost converter, where one cell is made up of L_m1, S_m1, D₁, and C₁, and the second cell includes L_m2, S_m2, D₂, and C₂. It also features a diode-capacitor network formed by D₃ and C₃, along with a single auxiliary soft-switching circuit that consists of the auxiliary switch S_a, auxiliary inductor L_a, auxiliary capacitor C_a, and auxiliary diodes D_a1, D_a2, D_a3, and D_a4. The two boost converter stages are configured in an input-parallel and output-series (IPOS) arrangement, facilitating a reduction in input-current ripple while enhancing the output voltage gain.

Typically, the operating behavior of a two-phase interleaved boost converter can be classified into two conditions: when the duty cycle is greater than or less than 0.5. In this study, the focus is solely on the case where the duty cycle is greater than 0.5, as it sufficiently meets the voltage gain requirements of the target application. In this operating mode, the converter undergoes 20 different intervals within a single switching cycle. Owing to the symmetry of the interleaved structure, only the ten stages associated with switch S_m1 are examined, as the behavior of the complementary phase is identical. A simplified operational flowchart of the proposed converter is shown in Figure 2b to provide a clear overview of the overall system operation. The corresponding key waveforms, obtained from MATLAB R2024b/Simulink simulations, and the equivalent circuit for each stage are presented in Figure 3 and Figure 4, respectively. The description of each operating stage is provided as follows.

Stage 1 [Before Turn−Off of the Main Switch S_m1, Figure 4a]: During this interval, i_Sm1 = I_Lm1, i_Sm2 = I_Lm2 + I₁, i_Sa = 0, i_La = 0, i_D1 = 0, i_D2 = 0, i_D3 = I₁ and V_Ca = 0. Before the instant t₁, the interleaved boost converter operates in its normal on−state interval with a duty ratio greater than 0.5. In this interval, both main switches and diode D₃ are conducting, while the auxiliary switch and main diodes D₁ and D₂ remain in the off state. During this mode, the input inductors L_m1 and L_m2 are energized by the input source V_in, thus

$$L_{m1}{\displaystyle \frac{d{i}_{Lm1}}{dt}}=L_{m2}{\displaystyle \frac{d{i}_{Lm2}}{dt}}=V_{in}$$

(1)

Since capacitors C₁ and C₃ are charged in parallel, the voltage difference between them remains small, though it cannot be neglected. This slight voltage imbalance gives rise to a current through diode D₃, denoted as I₁. Under this condition, the current through switch S_m1 corresponds to the inductor current L_m1, while the current through switch S_m2 is the sum of i_Lm2 and I₁. This stage ends when the main switch S_m1 turns off at time t = t₁.

Stage 2 [t₁ < t < t₂, Figure 4b]: At t = t₁, auxiliary diodes D_a1 and D_a3 become forward biased and start conducting. During this interval, the main inductor current I_Lm1 discharges the auxiliary capacitor C_a, while the output capacitance of main switch C_Sm1 is simultaneously charged. Because C_a has a significantly higher capacitance compared to C_Sm1, the main switch S_m1 achieves turn−off under ZVS condition. The voltage equations of the circuit elements in this interval are described as follows:

$$V_{Ca}(t)={\displaystyle \frac{I_{Lm1}}{C_a+C_{Sm1}}}(t-t_1)$$

(2)

$$V_{Sm1}=V_{C1}-V_{Ca}\left(t\right)$$

(3)

The parasitic capacitor C_Sm1 charges up to the voltage V_C1 while the capacitor C_a discharges completely to zero at t = t₂. At this moment, the auxiliary diodes D_a1 and D_a3 turn off with ZVS and this stage ends. The time span of this interval is obtained as follows:

$$t_2-t_1={\displaystyle \frac{C_a{V}_{C1}}{I_{Lm1}}}$$

(4)

Stage 3 [t₂ < t < t₃, Figure 4c]: Before this interval, i_Sm1 = 0, i_Sm2 = I_Lm2 + I₁, i_Sa = i_La = 0, i_D1 = 0, i_D2 = 0, i_D3= I₁ and V_Ca = 0 are valid. At instant t₂, the main diode D₁ switches on, directing the input current toward the load. This stage concludes at t₃, when the auxiliary switch S_a begins to turn on. During this stage, the input voltage V_in charges L_m2 and L_m1 together with V_in supplies energy to C₁ and C₃. So, for this stage, the equations

$$L_{m1}{\displaystyle \frac{d{i}_{Lm1}}{dt}}=V_{in}-V_{C1}$$

(5)

$$L_{m2}{\displaystyle \frac{d{i}_{Lm2}}{dt}}=V_{in}$$

(6)

are valid.

Stage 4 [t₃ < t < t₄, Figure 4d]: Before this interval, i_Sm1 = 0, i_Sm2 = I_Lm2 + I₁, i_Sa = i_La = 0, i_D1 = I_Lm1, i_D2 = 0, i_D3 = I₁ and V_Ca = 0 are valid. At t₃, auxiliary switch S_a turns on. As a result, the current i_La begin to rise linearly, with the rate of increase governed by the slope given below:

$${\displaystyle \frac{d{i}_{La}}{dt}}={\displaystyle \frac{V_{C1}}{L_a}}$$

(7)

This effectively redirects the current flow away from the primary diode D₁. Thus, the auxiliary switch S_a activates with ZCS condition at t₄, while the main diode D₁ deactivates under ZCS at t₄. This occurs because of the series arrangement between the auxiliary switch S_a and the inductor L_a. The interval concludes at t₄, when current i_La equals the input current I_Lm1 and the current i_D1 reaches zero. The duration of this interval can be calculated using (7) as follows:

$$t_{01}={\displaystyle \frac{I_{Lm1}}{V_{C1}}}{L}_a={\displaystyle \frac{P_o}{V_{in}{V}_{C1}}}{L}_a$$

(8)

Stage 5 [t₄ < t < t₅, Figure 4e]: At moment t₄, the main diode D₁ is turned off. Subsequently, resonance begins between L_a and C_Sm1, transferring the entire stored energy in C_Sm1 to L_a. This mode concludes once C_Sm1’s voltage drops to zero and the current through the auxiliary inductor L_a reaches its peak value, I_La,peak.

$$i_{La}(t)=I_{Lm1}+{\displaystyle \frac{V_{C1}}{Z_1}}\sin \left[{\omega }_1(t-t_4)\right], t_4<t<t_5$$

(9)

$$V_{C_{Sm1}}(t)=V_{C1}\cos \left[{\omega }_1(t-t_4)\right], t_4<t<t_5$$

(10)

In Equations (9) and (10),

$$Z_1=\sqrt{{\displaystyle \frac{L_a}{C_{Sm1}}}}$$

(11)

$${\omega }_1={\displaystyle \frac{1}{\sqrt{L_a{C}_{Sm1}}}}$$

(12)

I_La,peak can be determined from Equation (9) at time t = t₅ by

$$I_{La,\mathrm{peak}}=I_{Lm1}+{\displaystyle \frac{V_{C1}}{Z_1}}$$

(13)

The duration of this operating interval is obtained from the following relation:

$$t_{02}={\displaystyle \frac{\pi }{2{\omega }_1}}={\displaystyle \frac{\pi }{2}}\sqrt{L_a{C}_{Sm1}}$$

(14)

Stage 6 [t₅ < t < t₆, Figure 4f]: At t = t₅, once V_CSm1 reaches zero, the body diode D_Sm1 of the switch S_m1 is activated. This clamps the voltage across S_m1 and L_a to zero and holds the current i_La constant at I_La,peak. This allows switch S_m1 to be turned on with ZVS condition. The mathematical relations describing this interval are given by the following:

$$I_{D_{Sm1}}=I_{La,\mathrm{peak}}-I_{Lm1}$$

(15)

Stage 7 [t₆ < t < t₇, Figure 4g]: At the start of this interval, i_Sm1 = 0, i_Sm2 = I_Lm2 + I₁, i_Sa = i_La = I_La,peak, i_D1 = 0, i_D2 = 0, i_D3 = I₁ and V_Ca = 0 are valid. At moment t = t₆, the auxiliary diode D_a1 turn off with ZVS, the main switch S_m1 receives a turn-on gate signal, and the auxiliary switch S_a has its gate signal removed at the same instant. As a result, S_m1 achieves ZVS turn-on, while S_a undergoes ZVS turn-off via capacitor C_a. Once S_a is switched off, conduction transfers to diode D_a2, which turns on with ZVS, and subsequently, L_a engages in a resonant interaction with C_a and C_Sa. The governing equations for this resonant interval can be derived as follows:

$$i_{La}(t)=I_{La,\mathrm{peak}}\cos \left[{\omega }_2(t-t_6)\right], t_6<t<t_7$$

(16)

$$V_{C_{Sa}}(t)=V_{Ca}(t)=I_{La,\mathrm{peak}}{Z}_2(t)\sin \left[{\omega }_2(t-t_6)\right], t_6<t<t_7$$

(17)

In Equations (16) and (17),

$$Z_2=\sqrt{{\displaystyle \frac{L_a}{C_{Sa}+C_a}}}$$

(18)

$${\omega }_2={\displaystyle \frac{1}{\sqrt{L_a\left(C_{Sa}+C_a\right)}}}$$

(19)

The length of this resonance interval is determined using the following expression:

$$t_7-t_6=\sqrt{L_a\left(C_a+C_{Sa}\right)}{\sin }^{-1}\left({\displaystyle \frac{V_{C1}}{I_{La,\mathrm{peak}}\sqrt{\frac{L_a}{C_a+C_{Sa}}}}}\right)$$

(20)

The auxiliary switch’s turn off voltage is predominantly influenced by C_a and L_a because C_Sa is significantly smaller than C_a. This interval terminates at t = t₇, when V_Ca and V_CSa rise to V_C1, resulting in the forward conduction of diode D_a3.

Stage 8 [t₇ < t < t₈, Figure 4h]: Once V_Ca reaches V_C1, diode D_a3 conducts, transferring the remaining energy stored in the auxiliary inductor L_a to the output. This interval concludes at t = t₈, when the current i_La falls to zero, resulting in the ZCS turn-off of diodes D_a2 and D_a4.

Stage 9 [t₈ < t < t₉, Figure 4i]: At t = t₈, C_Sa and L_a enter a resonant interaction. Since C_a is much larger than C_Sa, V_Ca is therefore assumed constant throughout this resonant interval. Consequently, the voltages and currents equations of the elements involved in the resonant process can be analytically determined as follows:

$$i_{La}(t)=-V_{C1}{Z}_3\sin \left[{\omega }_3(t-t_8)\right], t_8<t<t_9$$

(21)

$$V_{C_{Sa}}(t)=V_{C1}\cos \left[{\omega }_3(t-t_8)\right], t_8<t<t_9$$

(22)

In Equations (21) and (22),

$$Z_3=\sqrt{{\displaystyle \frac{C_{Sa}}{L_a}}}$$

(23)

$${\omega }_3={\displaystyle \frac{1}{\sqrt{L_a{C}_{Sa}}}}$$

(24)

This resonant mode ends once V_Sa reaches zero and the inductor current i_La attains its minimum I_La,min which can be determined from Equation (21) as follows:

$$I_{La,\min }=-V_{C2}{Z}_3$$

(25)

The length of this mode is computed as

$$t_9-t_8={\displaystyle \frac{\pi }{2}}\sqrt{L_a{C}_{Sa}}$$

(26)

Stage 10 [t₉ < t < t₁₀, Figure 4j]: At t₉, the anti-parallel diode of auxiliary switch D_Sa becomes forward-biased, initiating a resonant process between L_a and C_a. The current and voltage equations for this resonant interval can be found as follows:

$$i_{La}(t)=I_{La,\min }\cos \left[{\omega }_4(t-t_9)\right], t_9<t<t_{10}$$

(27)

$$V_{C_{Sa}}(t)=V_{C1}+I_{La,\min }{Z}_4(t)\sin \left[{\omega }_4(t-t_9)\right], t_9<t<t_{10}$$

(28)

In Equations (27) and (28),

$$Z_4=\sqrt{{\displaystyle \frac{L_a}{C_a}}}$$

(29)

$${\omega }_4={\displaystyle \frac{1}{\sqrt{L_a{C}_a}}}$$

(30)

The interval terminates once i_La falls to zero, and its duration can be determined from the following expression:

$$t_{10}-t_9={\displaystyle \frac{\pi }{2}}\sqrt{L_a{C}_a}$$

(31)

The voltage variation ∆VC_a across C_a during this interval can be evaluated from Equations (25), (28) and (31) as follows:

$$\Delta V_{Ca}=V_{C1}\sqrt{{\displaystyle \frac{C_{Sa}}{C_a}}}$$

(32)

Upon completion of this interval, the first segment of the switching cycle, which characterizes the conduction and switching of S_m1, concludes. The subsequent segment, associated with S_m2, occurs next, following the same operational pattern to maintain interleaved symmetry.

3. Analysis of the Converter Characteristics

The detailed analysis of the proposed converter is as follows.

3.1. Voltage Gain

3.1.1. Ideal Voltage Gain of the Proposed Converter

For the proposed converter, the auxiliary circuit has a small impact on the voltage gain. Therefore, for simplification of the derivation, the auxiliary circuit can be disregarded. It is assumed that all circuit elements are ideal and the capacitance and inductance values are sufficiently large so that the voltage across each capacitor remains essentially constant. Figure 4c indicates that S_m2 is switched on while diode D₃ is conducting. Under this condition, C₁ and C₃ are linked in parallel, so the voltage on each capacitor becomes the same. In CCM operation, the converter’s voltage gain is derived by applying the volt-second balance principle to the input inductors L_m1 and L_m2.

$$V_{in}d+\left(V_{in}-V_{C1}\right)\left(1-d\right)=0$$

(33)

$$V_{in}d+\left(V_{in}+V_{C1}-V_o\right)\left(1-d\right)=0$$

(34)

also

$$V_{C1}=V_{C3}$$

(35)

Within a single switching period, the converter’s output voltage can be expressed as follows:

$$V_{C1}+V_{C2}=V_o$$

(36)

where V_in and V_o refer to the input and output voltages, while V_C1, V_C2, and V_C3 correspond to the voltages across C₁, C₂, and C₃. Thus,

$$\left\{\begin{array}{l}{V}_o={\displaystyle \frac{2V_{in}}{1-d}}\hfill \\ V_{C1}=V_{C2}=V_{C3}={\displaystyle \frac{V_{in}}{1-d}}\hfill \end{array}\right.$$

(37)

using Equation (37), the voltage gain G is given by

$$G={\displaystyle \frac{2}{1-d}}$$

(38)

3.1.2. Non-Ideal Voltage Gain of the Proposed Converter

In order to evaluate the voltage gain considering parasitic components, the parasitic elements are defined as follows: r_S is the MOSFET on-resistance and the corresponding conduction voltage drop is modeled as V_S, V_fd is the diode forward conduction voltage drop, r_L is the equivalent series resistance (ESR) of the input inductors, and the ripple current in the inductors is neglected. The configuration of the proposed converter, along with its parasitic components, is shown in Figure 5. Just like the ideal case, the influence of the ZVT cell on the voltage gain is small and can thus be ignored. Using the volt-second balance principle for inductors L_m1 and L_m2, and the ampere-second balance principle for capacitors C₁–C₃ in CCM, the following expressions can be obtained:

$$\left\{\begin{array}{l}\begin{array}{l}d{T}_s(V_{in}-I_{Lm1}{r}_L-V_S)\\ +(1-d)T_s(V_{in}-I_{Lm1}{r}_L-V_{fd}-V_{C1})=0\end{array}\hfill \\ \begin{array}{l}[d{T}_s(V_{in}-I_{Lm2}{r}_L-V_S)\\ +(1-d)T_s(V_{in}-I_{Lm2}{r}_L-V_{C2}-V_S-2V_{fd})=0\end{array}\hfill \end{array}\right.$$

(39)

$$\left\{\begin{array}{l}\left(I_{Lm2}-{\displaystyle \frac{V_o}{R}}\right)T_s(1-d)+\left(-{\displaystyle \frac{V_o}{R}}\right)d{T}_s=0\hfill \\ I_{D2}{T}_s=I_{Lm2}(1-d)T_s\hfill \end{array}\right.$$

(40)

During the switching period, the output voltage of the converter is always described by

$${\mathrm{V}}_o{=\mathrm{V}}_{C1}{+\mathrm{V}}_{C2}$$

(41)

According to Equations (39)–(41) the volage gain G and the capacitor voltages could be derived by

$$G={\displaystyle \frac{V_o}{V_{in}}}={\displaystyle \frac{2-\frac{(1+d)V_S+3(1-d)V_{fd}}{V_{in}}}{1-d+\frac{2r_L}{R(1-d)}}}$$

(42)

The capacitor voltages are calculated by

$$V_{C1}={\displaystyle \frac{V_{in}-I_{L1}{r}_L-d{V}_S-(1-d)V_{fd}}{1-d}}$$

(43)

$$V_{C2}={\displaystyle \frac{V_{in}-I_{L2}{r}_L-V_S}{1-d}}-2V_{fd}$$

(44)

$$V_{C3}={\displaystyle \frac{V_{in}-I_{L1}{r}_L-V_S-2(1-d)V_{fd}}{1-d}}$$

(45)

3.2. Voltage and Current Stress Across the Semiconductor Devices

The operating principles indicate that C₁, C₂ and C₃ sustain identical voltages, each equal to half of the output voltage, i.e., V_o/2. The main switch S_m1 and auxiliary switch S_a experience voltage stresses equal to V_C1, while the main switch S_m2 is subjected to a voltage stress of V₀ − V_C3. The diodes D₁, D₂, and D₃ are stressed by voltages of V_C1, V_o −V_C3, and V_C2, respectively. Accordingly, the capacitor and device voltages are expressed as

$$\left\{\begin{array}{l}{V}_{C1}=V_{C2}=V_{C3}=V_{Ca}={\displaystyle \frac{V_o}{2}}\hfill \\ V_{Sm1}=V_{Sm2}=V_{Sa}={\displaystyle \frac{V_o}{2}}\hfill \\ V_{D1}=V_{D2}=V_{D3}={\displaystyle \frac{V_o}{2}}\hfill \\ V_{Da1}=V_{Da2}=V_{Da3}=V_{Da4}={\displaystyle \frac{V_o}{2}}\hfill \end{array}\right.$$

(46)

As all switches experience a voltage stress of V_o/2, devices with low conduction resistance may be utilized to effectively reduce conduction losses and thereby improve the overall efficiency. In addition, the voltage stresses across the capacitors are restricted to 50% of the output voltage, contributing to smaller component sizes, minimized risk of failure, and enhanced system reliability.

Based on the steady-state operation under CCM and the waveforms shown in Figure 3 along with the equivalent circuits in Figure 4, the average currents of the main switches and diodes are derived as follows:

$$\left\{\begin{array}{l}{I}_{Sm1,avg}={\displaystyle \frac{d}{1-d}}\times {\displaystyle \frac{V_o}{R}}\\ I_{Sm2,avg}={\displaystyle \frac{1}{1-d}}\times {\displaystyle \frac{V_o}{R}}\\ I_{D1,avg}=I_{D2,avg}=I_{D3,avg}={\displaystyle \frac{V_o}{R}}\end{array}\right.$$

(47)

Similarly, the average currents of the auxiliary switches and diodes are derived as follows:

$$\left\{\begin{array}{l}{I}_{Sa,avg}={\displaystyle \frac{I_{La,peak}{t}_{Sa}}{T_s}}\\ I_{Da1,avg}={\displaystyle \frac{1}{T_s}}\left[V_{C1}{C}_a+{\displaystyle \frac{1}{2}}{I}_{La,peak}{t}_{Sa}\right]\\ I_{Da2,avg}={\displaystyle \frac{1}{T_s}}\left[V_{C1}(C_a+C_{Sa})+{\displaystyle \frac{L_a{I}_{La,peak}^2}{V_{C1}}}\right]\\ I_{Da3,avg}={\displaystyle \frac{1}{T_s}}\left[V_{C1}\left(C_a-C_{Sa}\right)+{\displaystyle \frac{L_a{I}_{La,peak}^2}{V_{C1}}}\right]\\ I_{Da4,avg}={\displaystyle \frac{1}{T_s}}\left[V_{C1}(2C_a+C_{Sa})+{\displaystyle \frac{1}{2}}{I}_{La,peak}{t}_{Sa}+{\displaystyle \frac{L_a{I}_7^2}{2V_{C1}}}\right]\end{array}\right.$$

(48)

The RMS currents of the main switches and diodes are given as follows:

$$\left\{\begin{array}{l}{I}_{Sm1,rms}={\displaystyle \frac{\sqrt{d}}{1-d}}\times {\displaystyle \frac{V_o}{R}}\\ I_{Sm2,rms}={\displaystyle \frac{1}{\sqrt{d}(1-d)}}\times {\displaystyle \frac{V_o}{R}}\\ I_{D1,rms}=I_{D3,rms}={\displaystyle \frac{1}{\sqrt{1-d}}}\times {\displaystyle \frac{V_o}{R}}\\ I_{D2,rms}={\displaystyle \frac{1}{\sqrt{d}}}\times {\displaystyle \frac{V_o}{R}}\end{array}\right.$$

(49)

Similarly, the RMS currents of the auxiliary switches and diodes are given as follows:

$$\left\{\begin{array}{l}{I}_{Sa,rms}=I_{La,peak}\sqrt{{\displaystyle \frac{2t_{Sa}}{3T_s}}}\\ I_{Da1,rms}=\sqrt{{\displaystyle \frac{I_{Lm1}{C}_a{V}_{C1}+\frac{I_{La,peak}^2{t}_{Sa}}{3}}{T_s}}}\\ I_{Da2,rms}=I_{La,peak}\sqrt{{\displaystyle \frac{2[(t_7-t_6)+(t_8-t_7)]}{3T_s}}}\\ I_{Da3,rms}=\sqrt{{\displaystyle \frac{2I_{Lm1}{C}_a{V}_{C1}+\frac{2}{3}{I}_7^2{t}_{78}}{T_s}}}\\ I_{Da4,rms}=\sqrt{{\displaystyle \frac{I_{Lm1}{C}_a{V}_{C1}+\frac{I_{La,peak}^2{t}_{Sa}}{3}+\frac{I_7^2\left(t_8-t_7\right)}{3}}{T_s}}}\end{array}\right.$$

(50)

3.3. Ripple Analysis

Over a single switching period, switches S_m1 and S_m2 share the same duty cycle while being phase-shifted by 180°. This phase arrangement effectively minimizes the ripple in the input current.

Using Equation (40), the average values of the inductor currents I_Lm1 and I_Lm2 are determined, and their final forms are shown in Equation (51):

$$I_{Lm1}=I_{Lm2}={\displaystyle \frac{V_o}{R\left(1-d\right)}}$$

(51)

$$I_{in}=I_{Lm1}+I_{Lm2}={\displaystyle \frac{2V_o}{R\left(1-d\right)}}$$

(52)

In the switching interval when S_m1 is turned on, the inductor L_m1 is directly connected to the input source and its current increases linearly. Similarly, when S_m2 is turned on, the inductor L_m2 experiences the input voltage and its current rises with the same linear slope. Based on these charging intervals, the current ripples of L_m1 and L_m2 can be expressed as follows:

$$\Delta i_{Lm1}=\Delta i_{Lm2}={\displaystyle \frac{d{V}_{in}}{L{f}_s}}$$

(53)

where f_s represents the switching frequency of the power switches. For d > 0.5, the two inductor currents overlap for (2d − 1)T_s.

The input current slope is

$$\Delta i_{Lm1}=\Delta i_{Lm2}={\displaystyle \frac{d{V}_{in}}{L{f}_s}}$$

(54)

Hence, the input current is

$$\Delta i_{in}={\displaystyle \frac{V_{in}}{L}}(2d-1)T_s={\displaystyle \frac{V_{in}\left(2d-1\right)}{L{f}_s}}$$

(55)

And the ripple rates r_L1 and r_L2 of inductors L_m1 and L_m2 can also be found as

$$r_{L1}=r_{L2}={\displaystyle \frac{d{(1-d)}^{2}R}{2L{f}_s}}$$

(56)

A slight increase in input-current ripple may occur if the two interleaved input inductors have different values, due to differences in their charging and discharging rates. In an interleaved converter, the total input current is the sum of the phase currents, so any imbalance reduces the natural ripple-cancelation effect. As shown in Figure 6, the input-current ripple is minimal when the inductors are equal, slightly higher for small differences, and largest for significant mismatches. This behavior is typical in all interleaved converters. Importantly, these variations do not affect the proposed converter’s soft-switching operation, voltage gain, or voltage stress, which are determined by the topology and duty cycle rather than the exact inductor values.

3.4. Comparisons with Other Converters

A comparison between the proposed converter and the closely related interleaved converters from recent literature is presented in

Table 1. Comparison of converter topologies.

Converters	Voltage Gain	Voltage Stress Across the Switches	Voltage Stress Across the Diodes	Soft-Switching	No. of Components (S/D/C/Core)	Input-Current Ripple	Common Ground
[28]	${\displaystyle \frac{2}{1-D}}$	${\displaystyle \frac{1}{2}}{V}_o$	${\displaystyle \frac{1}{2}}{V}_o$	Hard Switching	2/4/3/2	High	Yes
[29]	${\displaystyle \frac{2}{1-D}}$	${\displaystyle \frac{1}{2}}{V}_o$	${\displaystyle \frac{1}{2}}{V}_o$	Hard Switching	2/3/3/2	Small	No
[30]	$\begin{array}{l}D<0.5:{\displaystyle \frac{1}{1-kD}}\\ D>0.5:{\displaystyle \frac{1+N}{1-D}}\end{array}$	$V_o$	${\displaystyle \frac{1}{2}}{V}_o$	Hard Switching	2/4/1/1	Small	Yes
[31]	${\displaystyle \frac{n(2+D)+3}{1-D}}$	${\displaystyle \frac{V_o}{n(2+D)+3}}$	${\displaystyle \frac{n+1}{n(2+D)+3}}{V}_o$	Hard Switching	1/5/5/1	Large	Yes
[32]	${\displaystyle \frac{4}{1-D}}$	${\displaystyle \frac{3}{8}}{V}_o$	${\displaystyle \frac{1}{2}}{V}_o$	Hard Switching	2/4/5/2	Small	No
[33]	${\displaystyle \frac{1}{1-D}}$	$V_o$	$V_o$	ZVZCS	4/4/3/4	Small	Yes
[34]	${\displaystyle \frac{2\left(n+1\right)}{1-D}}$	${\displaystyle \frac{V_o}{2\left(n+1\right)}}$	${\displaystyle \frac{(2n+1)V_o}{2(n+1)}}$	ZVS	4/2/3/2	Small	Yes
[35]	${\displaystyle \frac{2\left(2n+1\right)}{1-D}}$	${\displaystyle \frac{V_o}{2\left(2n+1\right)}}$	${\displaystyle \frac{1}{2}}{V}_o$	ZVS	4/4/5/1	Small	No
[36]	${\displaystyle \frac{2\left(n+2\right)}{1-D}}$	${\displaystyle \frac{V_o}{2\left(n+2\right)}}$	${\displaystyle \frac{n+1}{n+2}}{V}_o$	ZVS/ZCS	3/6/4/2	Small	No
[37]	${\displaystyle \frac{1}{Q+0.5-D}}$	${\displaystyle \frac{1}{2}}{V}_o$	${\displaystyle \frac{1}{2}}{V}_o$	ZVS/ZCS	3/3/3/1	Very Small	Yes
Proposed Converter	${\displaystyle \frac{2}{1-D}}$	${\displaystyle \frac{1}{2}}{V}_o$	${\displaystyle \frac{1}{2}}{V}_o$	ZVS/ZCS	3/3/4/3	Very Small	Yes

.

The converters in [28,29] achieve the same voltage gain and offer reduced input-current ripple. Nevertheless, in comparison with the proposed converter, the converter in [33] experiences relatively high voltage stress on two diodes and one capacitor, equal to the output voltage. Furthermore, the design in [29] lacks a common ground, which can introduce EMI concerns. In addition, in both converters, the power switches operate under hard-switching conditions, leading to increased switching losses and reduced efficiency. In [30], a converter employing a three-winding coupled inductor is proposed. Its advantages include small input-current ripple, high step-up ratio, and reduced voltage stress on the diodes. Nevertheless, the switching devices operate under hard-switching conditions. Furthermore, every switch experiences a voltage stress identical to the output voltage. In [31], a single-switch converter based on a coupled inductor is proposed to achieve ultra-high voltage gain. Although this configuration reduces the voltage stresses on both the semiconductor switches and diodes, the improvement in efficiency is limited by the hard-switching operation of the semiconductor switches and the reverse-recovery characteristics of the diodes. Moreover, the high input-current ripple limits its suitability for fuel cell vehicle applications. In [32], a converter employing an improved Dickson-based charge-pump voltage multiplier at the output is introduced to achieve high voltage gain and reduce switch voltage stress. However, the semiconductor devices still experience hard-switching losses, reducing efficiency, and the complex circuit structure increases both the converter’s volume and cost. The interleaved converter in [33] incorporates auxiliary circuits in each phase to achieve complete soft-switching operation. However, the resulting voltage gain is insufficient to effectively connect the fuel cell with the DC power system. In addition, the converter in [33] requires twice as many auxiliary circuits as the proposed design. Coupled-inductor-based interleaved structures are proposed in [34,35,36], which are capable of achieving both low input-current ripple and high voltage gain simultaneously. Moreover, by incorporating an active clamp circuit, the main switches operate under soft-switching conditions. Nevertheless, the soft-switching capability in [34,35] is restricted to an arrow range, and the non-common ground between the input and output in [35,36] introduces considerable EMI concerns. In addition, their circuit structures are more complex than those of the proposed converter, leading to increased volume and cost. Although the CI-based converter proposed in [37] has a low number of components as compared to the proposed converter, the turn-off of the main switches is hard-switched which reduces overall efficiency. From the above comparisons, it can be concluded that the proposed converter offers superior performance, characterized by reduced input-current ripple, high step-up ratio with reduced component stress, wide-range soft-switching capability for all active devices, and a common-ground structure.

4. Parameter Design and Experimental Results

In this section, the design considerations of the proposed converter are presented. The proposed interleaved boost converter is configured to operate in continuous conduction mode (CCM), while ensuring both ZVS and ZCS conditions.

4.1. Selection of the Boost Inductors L_m1 and L_m2

The inductor design is influenced by the allowable current ripple rates r_Lm1 and r_Lm2, the nominal input and output voltages V_in and V_o, the rated load resistance, and the operating switching frequency f_s:

$$L_{m1}=L_{m2}={\displaystyle \frac{d{(1-d)}^2\times R}{2f_{s}r}}$$

(57)

The proposed converter typically operates with a duty cycle between 0.5 and 0.75. At a 0.5 duty cycle, the design requires the maximum inductance values. At this point, to keep the inductor currents continuous, both inductor current ripple ratios r_Lm1 and r_Lm2 are set to 70%.

$${\mathrm{L}}_{\mathrm{m}1}={\mathrm{L}}_{\mathrm{m}2}={\displaystyle \frac{0.5\times {(1-0.5)}^2\times 160}{2\times 50000\times 0.7}}=285\mathsf{\mu }\mathrm{H}$$

(58)

To ensure the inductor current ripple remains small during light-load operation, and to provide additional margin, the inductance is set to 330 μH.

4.2. Capacitor Design

When selecting the output capacitors, the output-voltage ripple must be carefully considered. Although larger capacitors help to minimize this ripple, they also increase the converter’s overall cost and physical size. Thus, an appropriate trade-off between capacitance and cost must be achieved. Given that capacitors C₁ and C₂ govern the output-voltage ripple in the proposed converter, the corresponding output-voltage ripple Δu_o can be formulated as

$$\Delta V_o=\Delta V_{C1}+\Delta V_{C2}$$

(59)

where ∆V₁ and ∆V₂ are the voltage ripples across C₁ and C₂, respectively. To facilitate maintenance and simplify the analysis, the capacitors are selected to have equal values, i.e., C₁ = C₂ = C₃ = C. Consider the sub-interval where S_m1 ON and S_m2 is off; D₂ conducts while D₁ and D₃ blocks. In this interval, L_m1 is charged from the input with a linearly increasing current, while the input source together with L_m2 and C₃ transfer energy to C₁, C₂, and the load, so I_Lm2 decreases. The currents through C₁ and C₂ point toward their positive plates (charging), which drives a roughly linear rise in the output voltage during this sub-interval. Therefore, the output-voltage ripple over one switching period can be computed from the linear capacitor charge in this sub-interval, leading to Equation (60).

$$\Delta V_o={\displaystyle \frac{2d^2{V}_o}{RfC\left(1-d\right)}}$$

(60)

Considering that the proposed converter is connected in series with the inverter, the allowable ripple of the output voltage is restricted to ±0.15% of the rated output voltage in order to meet load requirements. The capacitor sizing is then determined using Equation (61) as follows:

$$\mathrm{C}={\displaystyle \frac{2{\mathrm{d}}^2{\mathrm{V}}_{\mathrm{o}}}{(1-\mathrm{d})\mathrm{f}\mathrm{R}\Delta {\mathrm{V}}_{\mathrm{o}}}}=375\mathsf{\mu }\mathrm{F}$$

(61)

Finally, to prevent excessive output-voltage ripple under heavy-load conditions and to provide an adequate design margin, a capacitor value of 450 μF is selected.

4.3. Condition of Soft Switching

The resonant capacitors C_Sm1 and C_Sm2 are the parasitic capacitances of the main switches S_m1 and S_m2, respectively. In contrast, the resonant capacitor C_a and the resonant inductor L_a are additionally added components introduced into the circuit to form the resonant network. To ensure ZVS during the turn-on transition of the main switches, the auxiliary switch S_a must satisfy the following condition at its turn-on time:

$$t_{Sa}\ge t_{01}+t_{02}$$

(62)

where t_Sa denotes the turn-on time of the auxiliary switch, t₀₁ represents the current rise time of the auxiliary inductor L_a during Mode 1, and t₀₂ is the resonant transition time in Mode 2. The selection of t_Sa is critical and must satisfy two primary constraints. First, to significantly reduce the reverse-recovery losses of the main diodes, i.e., D₁ and D₂, the current rise time of the auxiliary inductor during Mode 1 should be larger than three times the diode’s reverse-recovery time t_rr. Considering Mode 2’s resonant interval t₀₂, t_sa is chosen to be five times greater than t_rr. Second, to minimize conduction losses and maintain a compact auxiliary circuit, t_Sa should be chosen to be less than one-tenth of the switching period T_s. Therefore, t_sa is constrained by

$$5t_{rr}\le t_{Ss}\le {\displaystyle \frac{1}{10}}{T}_s$$

(63)

The main diode generally has a reverse-recovery time of several tens of nanoseconds. Thus, considering the chosen switching frequency and Equation (63), t_Sa ≤ 2 μs is determined. If t_sa is chosen too small, the inductance of the auxiliary inductor becomes insufficient to support proper resonant operation, causing the main switch to fail to achieve ZVS turn-on at light load. Conversely, if t_Sa is too large, the conduction losses in the auxiliary components increase significantly. Hence, t_Sa = 1000 ns is selected.

4.4. Auxiliary Inductor Design

The auxiliary inductor L_a governs the current change rate di/dt in the auxiliary switch at the moment of turn-on. Based on Equations (8), (14) and (62), the required value of L_a is selected as

$$L_a\le {\left({\displaystyle \frac{-\frac{\pi }{2}\sqrt{C_{Sm1}}+\sqrt{\frac{{\pi }^2}{4}{C}_{Sm1}+4\frac{P_o}{V_i{V}_o}{t}_{Sa}}}{2\frac{P_o}{V_i{V}_o}}}\right)}^2$$

(64)

Based on the design parameters, the maximum value of the auxiliary inductor obtained from (64) is L_a ≤ 16.96 μH. To reduce the freewheeling interval and associated conduction losses, L_a should be chosen below this upper limit. Therefore, in this work, L_a = 10 μH is selected.

4.5. Auxiliary Capacitor Design

The auxiliary capacitor C_a provides dv/dt for auxiliary switch S_a during turn-off. For the main switch to realize ZVS turn-off, the voltage across the auxiliary capacitor must reach the voltage across C₁ at the end of stage 7. Since the auxiliary inductor supplies the required charging energy to the auxiliary capacitor, the capacitance value is determined according to Equation (65).

$$C_a<L_a{\left({\displaystyle \frac{I_{La,\mathrm{peak}}}{V_o}}\right)}^2$$

(65)

From Equation (65), the value of auxiliary capacitance C_a is obtained as C_a ≤ 10 nF. To improve the ZVS turn-off range when the converter operates at light load, C_a needs to be chosen as small as possible to the maximum value. Accordingly, a capacitance of 3.3 nF is chosen in this work.

4.6. Experimental Results

To validate the theoretical analysis of the proposed converter, an experimental prototype with a 1 kW rating was constructed. The details of parameters used in the experiment are outlined in

Table 2. Experimental parameters of the converter.

Specification	Symbol	Value
Input Voltage	Vin	50 V
Output Voltage	Vo	400 V
Output Power	Po	1 kW
Switching Frequency	fs	50 kHz
Main Boost Inductor	Lm1, Lm2	330 μH
Output Capacitor	C1, C2, C3	270 μF
Resonant Inductor	La	10 μH
Resonant Capacitor	Ca	3.3 nF
Main Switches	Sm1, Sm2	IRF300P226
Auxiliary Switch	Sa	IRF300P226
Main Diodes	D1, D2, D3	VS-60APH03-N3
Auxiliary Diodes	Da1, Da2, Da3, Da4	VS-60APH03-N3

, and resistive load is employed during the measurements. Figure 7a depicts a photograph of the developed dc–dc converter used in the laboratory setup, while Figure 7b illustrates the experimental test arrangement.

The KEYSIGHT InfiniiVision MSOx2024A oscilloscope (Keysight Technologies, Santa Rosa, CA, USA) is employed to measure the current and voltage waveforms. A digital signal processor (DSP) platform based on the TMS320F28335 is employed to generate PWM gate signals for the MOSFETs in the experimental setup. The ePWM module is utilized to produce gate pulses with complementary duty ratios. The gate signal profiles, along with the measured output-voltage waveform corresponding to a 50 V input condition, are presented in Figure 8a. As shown in Figure 8a, the output voltage reaches 400 V, corresponding to a voltage-gain factor of 8. These results indicate that the proposed converter architecture supports high step-up voltage conversion capability.

The experimental results for the soft switching of main switches S_m1 and S_m2 are depicted in Figure 9a,b. As illustrated in Figure 9a, the control signal of the main switch S_m1, its drain–source voltage V_Sm1, and drain current i_Sm1 are compared. Similarly, Figure 9b presents the corresponding waveforms for S_m2. It can be observed that the drain to source voltages of the main switches S_m1 and S_m2 reduce to zero prior to the application of the turn-on signal, confirming that each switch operates under ZVS at turn-on. Furthermore, the main switches also turn off under ZVS conditions, confirming the effectiveness of the proposed auxiliary circuit. Consequently, the two main switches in the dual branches achieve full ZVS during both switching intervals with the support of a single auxiliary network. Moreover, the voltage stress of each active switch remains limited to approximately one-half of the output voltage (200 V), which agrees with Equation (46).

Figure 10 illustrates the measured soft-switching behavior of the auxiliary switch S_a. As observed, the drain–source voltage V_Sa and drain current i_Sa confirm that the auxiliary switch S_a turns on under ZCS conditions due to the series resonant inductor. Once the device enters the on-state, the current through S_a rises in linear manner, while the drain–source voltage V_Sa falls to zero whereas i_Sa stays low, thereby achieving a soft turn-on transition. During turn-off, S_a operates under ZVS conditions because of the parallel resonant capacitor, which allows the voltage across the switch to rise only after the current has decayed to zero. Consequently, both ZCS turn-on and ZVS turn-off are achieved, resulting in very low switching losses in the auxiliary circuit. Moreover, as the auxiliary switch operates for only a brief interval in each cycle, the associated conduction losses in the auxiliary path are substantially reduced. Therefore, the introduction of the auxiliary circuit adds only minimal conduction losses while effectively reducing the overall switching losses of the main switches.

The experimental waveforms of D₁ and D₂ are illustrated in Figure 11a and Figure 11b, respectively. As demonstrated in Figure 11a,b, the diode D₁ and D₂ is turned on with ZVS and turned off with ZCS. The reverse-recovery losses of the main diode were eliminated because the main diode turned off with ZCS due to the series inductor. In addition, the voltage stress across D₁ and D₂ is limited to about 200 V, i.e., nearly half of the output voltage, which shows that the proposed converter effectively reduces the voltage stress on the diodes. Figure 12a–d shows the voltage and current waveforms of the voltage, as well as current waveforms of the auxiliary diodes D_a1, D_a2, D_a3, and D_a4. All the diodes turn off under soft-switching conditions, which eliminates reverse-recovery losses. Moreover, the voltage stress across each auxiliary diode is only half of the output voltage. For evaluating the converter’s stability under dynamic conditions, the input voltage was varied between 50 V and 80 V. The respective waveforms for the input voltage, input current, and output voltage are presented in Figure 8b. Despite the changes in input voltage, the output voltage remains stable around the reference value of 400 V. This indicates that the converter can maintain a consistent output voltage across a range of input voltages. Therefore, the converter demonstrates strong dynamic stability. At rated power, the converter’s inductor currents I_Lm1 and I_Lm2 and the input current I_in are shown in Figure 13. Figure 13a presents I_Lm1 and I_Lm2 for an input of 50 V and an output of 400 V. Both inductor currents exhibit continuous conduction and are 180° out of phase, with nearly identical average values. Figure 13b compares the input current I_in with I_Lm2; the input current is roughly twice that of i_Lm2 and exhibits significantly lower ripple than the inductor currents.

The measured efficiency characteristics are presented in Figure 14. As observed from Figure 14a, the efficiency of the proposed converter varies with the output power level. The proposed converter achieves over 92.5% efficiency across most load conditions. Under light-load operation, the efficiency is approximately 92.9% whereas at rated power, the peak efficiency reaches 95.46%. Figure 14b illustrates how efficiency changes with respect to input voltage for a 1 kW, 400 V output. At V_in = 50 V, the minimum efficiency is 95.46% while the highest efficiency of 97.41% occurs when V_in = 80 V. Moreover, due to the soft-switching operation of the converter, switching losses are inherently minimized. As a result, the overall efficiency improves with increasing input volatge.

A comprehensive loss breakdown analysis was conducted to determine the efficiency of the proposed converter. Given the soft-switching operation of the converter, switching losses are assumed to be negligible. The remaining losses are divided into six parts. The first part is the capacitive turn-on loss of the auxiliary switch, which is calculated as 1/2C_SaV_Sa(t₀)f_s = 0.55 W, where C_Sa is the switch parasitic capacitance and V_S(t₀) is the switch voltage before it is turned on. The second part consists of the switch conduction loss, which is computed as R_DS(on)(I²_Sm1,rms + I²_Sm2,rms + I²_Sa,rms) = 6.07 W, with R_DS(on) representing the static drain-to-source on-resistance. The third part corresponds to the conduction loss in the diodes, calculated as V_F (I_D1,avg + ⋯ + I_Da4,avg) = 21.76 W, where V_F is the instantaneous forward voltage. The fourth part includes the conduction loss of the input inductors and auxiliary inductor, calculated as r_Lm(I²_Lm1,rms + I²_Lm2,rms) + r_LaI²_La,rms = 4.07 W, where r_Lm and r_La are the resistances of L_m and L_a, respectively. The fifth part is the ESR loss in the capacitors, calculated as (I²C_1,rms + I²C_2,rms + I²C_3,rms)r_c = 10.56 W, where rc is the series resistance. The sixth part is the inductor core loss, calculated as Pcore = P_vV_e = 2.52 W, where P_v is the core loss density and V_e is the effective core volume. Additionally, approximately 2 W is attributed to miscellaneous losses in the prototype, including PCB trace conduction losses, parasitic resistances, gate drive consumption, and minor switching-related losses not explicitly modeled.

5. Conclusions

In this study, a novel soft-switched interleaved DC-DC boost converter with a common ground is proposed, specifically designed for high-voltage and high-power applications operating in CCM. Compared to traditional non-isolated topologies, the proposed converter provides simultaneous benefits of small input-current ripple, high step-up ratio, and reliable soft-switching operation during turn-on and turn-off events, all within a structurally simple auxiliary circuit. Furthermore, the voltage stress across each switching device and capacitor is limited to half of the total output voltage. An auxiliary circuit is introduced, which, despite minor conduction losses, significantly reduces the switching losses in the main power devices, resulting in high overall efficiency. Experimental results validate the proposed design and confirm its effectiveness. Hence, the proposed converter presents itself as an effective power interface solution between a fuel cell source and a high-voltage DC bus, making it well-suited for use in fuel cell-based power conditioning systems. Despite these advantages, the proposed converter is a non-isolated topology, which may limit its use in applications where galvanic isolation is required for safety. Future work will focus on extending the proposed interleaved high-gain topology to include isolation while retaining the single auxiliary ZVT/ZCS circuit, high voltage gain, low input-current ripple, and soft-switching operation. In addition, the converter will be further evaluated at higher power levels and a wider input voltage range to demonstrate scalability and practical applicability in EV fuel cell systems.