Search Results (9)

A dual Al₂O₃ MIS gate structure is proposed to enhance the DC and RF performance of enhancement-mode GaN high-electron mobility transistors (HEMTs). As a result, the proposed MOS-HEMT with a dual recessed MIS gate structure offers 84% improvements in cutoff frequency (f_T) and 92% improvements in maximum oscillation frequency (f_max) compared to conventional HEMTs (from 7.1 GHz to 13.1 GHz and 17.5 GHz to 33.6 GHz, respectively). As for direct-current characteristics, a remarkable reduction in off-state gate leakage current and a 26% enhancement in the maximum saturation drain current (from 519 mA·mm⁻¹ to 658 A·mm⁻¹) are manifested in HEMTs with new structures. The maximum transconductance (g_m) is also raised from 209 mS·mm⁻¹ to 246 mS·mm⁻¹. Correspondingly, almost unchanged gate–source capacitance curves and gate–drain capacitance curves are also discussed to explain the electrical characteristic mechanism. These results indicate the superiority of using a dual Al₂O₃ MIS gate structure in GaN-based HEMTs to promote the RF and DC performance, providing a reference for further development in a miniwatt antenna amplifier and sub-6G frequencies of operation. Full article

In this article, a novel double-trench SiC MOSFET with an integrated MOS-channel diode (MCD) is proposed and analyzed through TCAD simulations. The MCD incorporates a short channel, where the channel length can be adjusted by modifying the recess depth. Owing to the drain-induced barrier-lowering (DIBL) effect, a low potential barrier is created for electrons flowing from the JFET region to the N+ source region. This effectively eliminates the bipolar degradation of the parasitic body p-i-n diode and reduces the cut-in voltage $V_{\mathrm{on}}$ by 69.2%. Additionally, the breakdown voltage (BV) remains nearly unchanged. The reduction in the p-well region alleviates the JFET effect, successfully lowering the specific on-resistance $R_{\mathrm{on},\mathrm{sp}}$, making the channel easier to turn on, and reducing the threshold voltage ($V_{\mathrm{th}}$). However, the increase in the gate charge $Q_{\mathrm{g}}$ results in a slight rise in the switching loss. Full article

In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si_0.5Ge_0.5 layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The proposed full BDI scheme flow is compatible with the main process flow of NS-GAA transistor fabrication and provides a large window for process fluctuations, such as the thickness of the S/D recess. It is an ingenious solution to insert the dielectric material under the source, drain and gate regions to remove the parasitic channel. Moreover, because the S/D-first scheme decreases the problem of high-quality S/D epitaxy, the innovative fabrication scheme introduces full BDI formation after S/D epitaxy to mitigate the difficulty of providing stress engineering in the full BDI formation before S/D epitaxy (Full BDI_First). The electrical performance of Full BDI_Last is demonstrated by a 4.78-fold increase in the drive current compared to Full BDI_First. Furthermore, compared to traditional punch through stoppers (PTSs), the proposed Full BDI_Last technology could potentially provide an improved short channel behavior and good immunity against parasitic gate capacitance in NS-GAA devices. For the assessed inverter ring oscillator (RO), applying the Full BDI_Last scheme allows the operating speed to be increased by 15.2% and 6.2% at the same power, or alternatively enables an 18.9% and 6.8% lower power consumption at the same speed compared with the PTS and Full BDI_First schemes, respectively. The observations confirm that the novel Full BDI_Last scheme incorporated into an NS-GAA device can be utilized to enable superior characteristics to benefit the performance of integrated circuits. Full article

Impacts of source/drain (S/D) recess engineering on the device performance of both the gate-all-around (GAA) nanosheet (NS) field-effect transistor (FET) and FinFET have been comprehensively studied at 5 nm node technology. TCAD simulation results show that the device off-leakage, including subthreshold leakage through the channel (I_sub) and punch-through leakage (I_PT) in the sub-channel, is strongly related to the S/D recess process. Firstly, device electrical characteristics such as current density distributions, On/Off-state current (I_on, I_off), subthreshold swing (SS), RC delay, and gate capacitance (C_gg) are investigated quantitatively for DC/AC performance evaluation and comparison according to S/D lateral recess depth (L_rcs) variations. For both device types, larger L_rcs will result in a shorter effective channel length (L_eff), so that the I_on and I_off simultaneously increase. At the constant I_off, the L_rcs can be optimized to enhance the device’s drivability by ~3% and improve the device’s RC delay by ~1.5% due to a larger C_gg as a penalty. Secondly, S/D over recess depth (H_rcs) in the vertical direction severely affects the punch-through leakage in the Sub-Fin or bottom parasitic channel region. The NSFET exhibits less I_off sensitivity provided that it can be well controlled under 12 nm since the bottom parasitic channel is still gated. Furthermore, with both H_rcs and L_rcs accounted for in the device fabrication, the NSFET still shows better control of the off-leakage in the intrinsic and bottom parasitic channel regions and ~37% leakage reduction compared with FinFETs, which would be critical to enable further scaling and the low standby power application. Finally, the S/D recess engineering strategy has been given: a certain lateral recess could be optimized to obtain the best drive current and RC delay, while the vertical over-recess should be in tight management to keep the static power dissipation as low as possible. Full article

The inner spacer thickness (T_IS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable T_IS variation (ΔT_IS). The gate length (L_G) depends on the T_IS. Thus, the DC/AC performance is significantly affected by ΔT_IS. Because the effects of ΔT_IS on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔT_IS should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (tr_pbt) should be considered with ΔT_IS because the gate controllability over tr_pbt is significantly dependent on ΔT_IS,B. If the S/D recess depth (T_SD) variation cannot be completely eliminated, reducing ΔT_IS,B is crucial for suppressing the effects of tr_pbt. It is noteworthy that reducing ΔT_IS,B is the most important factor when the T_SD variation occurs, whereas reducing ΔT_IS,T and ΔT_IS,M is crucial in the absence of T_SD variation to minimize the DC performance variation. As the T_IS increases, the gate capacitance (C_gg) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of C_gg to each ΔT_IS is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since T_SD of 5 nm increases the off-state current (I_off) sensitivity to ΔT_IS,B by a factor of 22.5 in NFETs, the ΔT_IS,B below 1 nm is essential for further scaling and yield enhancement. Full article

Glaciers are vital to water resources in the arid land of central Asia. Long-term runoff records in the glacierized area are particularly valuable in terms of evaluating glacier recession and water resource change on both a regional and global scale. The runoff records of streams draining basins with 46% current glacier cover, located at the Urumqi Glacier No. 1 in the source area of the Urumqi River in eastern Tianshan, central Asia, were examined for the purpose of assessing climatic and glacial influences on temporal patterns of streamflow for the period 1959–2018. Results suggest that runoff from the catchment correlates well with temperature and associated precipitation data. During the period 1993–2018, it increased by 114.39 × 10⁴ m³, which was 1.7 times the average runoff during the period 1959–1992. A simple water balance model is introduced to calculate the different components of the runoff, including precipitation runoff from glacier surface and from nonglacial areas, glacier mass balance and glacial runoff. Thus, the long-term change of each component and its response to climate change are revealed. We found that the period 1997–2018 is likely to be the “peak water” (tipping point) of the glacial runoff resulting from shrinkage of glacier area. Full article

We have simulated a U-shape recessed channel floating gate memory by Sentaurus TCAD tools. Since the floating gate (FG) is vertically placed between source (S) and drain (D), and control gate (CG) and HfO₂ high-k dielectric extend above source and drain, the integrated density can be well improved, while the erasing and programming speed of the device are respectively decreased to 75 ns and 50 ns. In addition, comprehensive synaptic abilities including long-term potentiation (LTP) and long-term depression (LTD) are demonstrated in our U-shape recessed channel FG memory, highly resembling the biological synapses. These simulation results show that our device has the potential to be well used as embedded memory in neuromorphic computing and MCU (Micro Controller Unit) applications. Full article

A novel AlGaN/GaN high-electron-mobility transistor (HEMT) with a high gate and a multi-recessed buffer (HGMRB) for high-energy-efficiency applications is proposed, and the mechanism of the device is investigated using technology computer aided design (TCAD) Sentaurus and advanced design system (ADS) simulations. The gate of the new structure is 5 nm higher than the barrier layer, and the buffer layer has two recessed regions in the buffer layer. The TCAD simulation results show that the maximum drain saturation current and transconductance of the HGMRB HEMT decreases slightly, but the breakdown voltage increases by 16.7%, while the gate-to-source capacitance decreases by 17%. The new structure has a better gain than the conventional HEMT. In radio frequency (RF) simulation, the results show that the HGMRB HEMT has 90.8%, 89.3%, and 84.4% power-added efficiency (PAE) at 600 MHz, 1.2 GHz, and 2.4 GHz, respectively, which ensures a large output power density. Overall, the results show that the HGMRB HEMT is a better prospect for high energy efficiency than the conventional HEMT. Full article

In this paper, we proposed a novel saddle type FinFET (S-FinFET) to effectively solve problems occurring under the capacitor node of a dynamic random-access memory (DRAM) cell and showed how its structure was superior to conventional S-FinFETs in terms of short channel effect (SCE), subthreshold slope (SS), and gate-induced drain leakage (GIDL). The proposed FinFET exhibited four times lower I_off than modified S-FinFET, called RFinFET, with more improved drain-induced barrier lowering (DIBL) characteristics, while minimizing I_on reduction compared to RFinFET. Our results also confirmed that the proposed device showed improved drain-induced barrier lowering (DIBL) and I_off characteristics as gate channel length decreased. Full article