Sensitivity of Inner Spacer Thickness Variations for Sub-3-nm Node Silicon Nanosheet Field-Effect Transistors

The inner spacer thickness (TIS) variations in sub-3-nm, node 3-stacked, nanosheet field-effect transistors (NSFETs) were investigated using computer-aided design simulation technology. Inner spacer formation requires a high selectivity of SiGe to Si, which causes inevitable TIS variation (ΔTIS). The gate length (LG) depends on the TIS. Thus, the DC/AC performance is significantly affected by ΔTIS. Because the effects of ΔTIS on the performance depend on which inner spacer is varied, the sensitivities of the performance to the top, middle, and bottom (T, M, and B, respectively) ΔTIS should be studied separately. In addition, the source/drain (S/D) recess process variation that forms the parasitic bottom transistor (trpbt) should be considered with ΔTIS because the gate controllability over trpbt is significantly dependent on ΔTIS,B. If the S/D recess depth (TSD) variation cannot be completely eliminated, reducing ΔTIS,B is crucial for suppressing the effects of trpbt. It is noteworthy that reducing ΔTIS,B is the most important factor when the TSD variation occurs, whereas reducing ΔTIS,T and ΔTIS,M is crucial in the absence of TSD variation to minimize the DC performance variation. As the TIS increases, the gate capacitance (Cgg) decreases owing to the reduction in both parasitic and intrinsic capacitance, but the sensitivity of Cgg to each ΔTIS is almost the same. Therefore, the difference in performance sensitivity related to AC response is also strongly affected by the DC characteristics. In particular, since TSD of 5 nm increases the off-state current (Ioff) sensitivity to ΔTIS,B by a factor of 22.5 in NFETs, the ΔTIS,B below 1 nm is essential for further scaling and yield enhancement.


Introduction
Silicon fin-shaped field-effect transistors (FinFETs) have been continuously scaled down from 22-nm to 5-nm nodes using fins with high aspect ratios and design technology co-optimization [1][2][3][4][5][6]. However, increasing the fin aspect ratio is challenging owing to the process complexity, and FinFETs with narrow fins exhibit threshold-voltage variations and performance degradation induced by the quantum confinement effect [7][8][9][10]. By contrast, Silicon gate-all-around nanosheet field-effect transistors (NSFETs) have received considerable attention as promising devices that can replace FinFETs in sub-3-nm nodes, as they can overcome these limitations through stacked nanosheet (NS) channels [11]. Furthermore, NSFETs provide excellent electrostatics because the gate surrounds the NS channels and drives a larger current within the same footprint with a wider effective channel width than FinFETs [11,12].
The inner spacer is a distinctive structural feature of NSFETs that has not been employed in previous devices. Typically, selective etching of the SiGe sacrificial layers is performed to form the inner spacer. However, selective etching requires a high selectivity of SiGe to Si and lateral etching. Therefore, it can be vulnerable to process variations [13,14]. Furthermore, because the inner spacer determines the gate length (L G ), these variations result in NSFETs with unintended L G changes and cause unoptimized leakage and DC/AC performance [11,15]. Therefore, precise control of the inner spacer thickness (T IS ) is crucial for performance optimization.
Previous studies related to the inner spacer have focused on the electrical properties of NSFETs, assuming the same shape and thickness from the top inner spacer to the bottom inner spacer [11,15]. However, in the actual process, the T IS variation (∆T IS ) may not occur uniformly [11,16]. In addition, for three-stacked NSFETs, the top and middle inner spacers adjoin two adjacent NS channels, while the bottom inner spacer adjoins only one NS channel and a punch-through stopper (PTS) region. Thus, the thickness variations of the top/middle/bottom (T/M/B) inner spacers have different effects on the device behavior; i.e., the T/M/B ∆T IS (∆T IS,T /∆T IS,M /∆T IS,B ) have different effects on the performance. Therefore, the performance sensitivities must be studied separately. Additionally, the over-etched S/D recess is a crucial factor determining the effects of the parasitic bottom transistor (tr pbt ) on the DC performance [17]. The effects of tr pbt on performance become more pronounced as L G decreases, which is a potential threat for further scaling [17,18]. However, there have been no studies on the effects of the S/D recess depth (T SD ) along with T/M/B ∆T IS on the device behavior. In this study, for the first time, we comprehensively analyzed the sensitivity of the DC/AC characteristics to each ∆T IS considering the T SD , and the off-state characteristics were analyzed in detail using fully calibrated computer-aided design (TCAD) simulation technology [19].

Device Structure and Simulation Methodology
The sub-3-nm node NSFETs investigated in this study were simulated using Sentaurus TCAD tools. The following physical models were considered in the TCAD simulation:

•
The drift-diffusion model was considered using Poisson's equations and the continuity equations to determine the electrostatic potential and carrier transport.

•
The density gradient model was considered for the quantum confinement effect in the drift-diffusion model [20,21].

•
The Slotboom bandgap narrowing model was considered for doping-dependent bandgap narrowing in Si and SiGe [22,23]. • A low-field ballistic mobility model was considered for quasi-ballistic transport [24]. • Mobility degradation at the interfaces was considered for remote phonon scattering and remote Coulomb scattering [25].

•
The inversion and accumulation layer mobility models were considered for Coulomb impurity, phonon scattering, and surface roughness scattering [26]. • A high-field saturation model was considered for carrier velocity saturation under a strong electric field [27]. • The deformation potential model was considered for the strain-induced density of states, effective mass of carriers, and energy-band shift [28].

•
The Auger and Shockley-Read-Hall (SRH) recombination models were used. Figure 1a shows schematics of the sub-3-nm node 3-stacked NSFETs. Among the T/M/B ∆T IS , we varied only one of the T/M/B T IS , with the others fixed at 5 nm, to investigate the effects of the T/M/B ∆T IS on the DC/AC characteristics separately. Here, the thicknesses of the T/M/B inner spacers were defined as T IS,T , T IS,M , and T IS,B , respectively. In addition, T SD of 0 and 5 nm were used to consider the effects of T SD on the performance along with those of ∆T IS [14]. Therefore, a comprehensive analysis of ∆T IS considering the T SD effect was performed. The TIS without variation (TIS,ref) was set as 5 nm, and only one of the three TIS was varied from 3 to 7 nm (Figure 1b). In this study, ΔTIS was defined as TIS − TIS,ref, and the LG of each channel depended on ΔTIS (LG = 22 − 2 × (TIS,ref + ΔTIS)). Si0.98C0.02 (Si0.5Ge0.5) S/D doped with phosphorus (boron) at 4 × 10 20 cm −3 was used for the NFETs (PFETs). The contact resistance of the S/D was set as 1 nΩ•cm 2 . The PTS layer was doped at 3 × 10 18 cm −3 , and the drain voltage (Vds) was fixed at |0.7| V. The geometric parameters are presented in Table 1. The NSFETs were calibrated to TSMC's 5-nm node FinFETs [5], and the same physical parameters were used, as shown in our previous studies [29]. The drain current was fitted by adjusting the doping profile, ballistic coefficient, and saturation velocity. The doping profile was changed to fit the subthreshold swing and DIBL since the doping profile is deeply concerned with the device behaviors in the subthreshold region. The ballistic coefficient was tuned to fit the drain current in the linear region, and the saturation velocity was set to fit the drain current in the saturation region. We extracted the on-state current (Ion) and gate capacitance (Cgg) at |Vgs| = 0.7 V and |Vds| = 0.7 V. Moreover, the offstate current (Ioff) and parasitic capacitance (Cpara) were extracted at |Vgs| = 0 V and |Vds| = 0.7 V. The T IS without variation (T IS,ref ) was set as 5 nm, and only one of the three T IS was varied from 3 to 7 nm (Figure 1b). In this study, ∆T IS was defined as T IS − T IS,ref , and the L G of each channel depended on ∆T IS (L G = 22 − 2 × (T IS,ref + ∆T IS )). Si 0.98 C 0.02 (Si 0.5 Ge 0.5 ) S/D doped with phosphorus (boron) at 4 × 10 20 cm −3 was used for the NFETs (PFETs). The contact resistance of the S/D was set as 1 nΩ·cm 2 . The PTS layer was doped at 3 × 10 18 cm −3 , and the drain voltage (V ds ) was fixed at |0.7| V. The geometric parameters are presented in Table 1. The NSFETs were calibrated to TSMC's 5-nm node FinFETs [5], and the same physical parameters were used, as shown in our previous studies [29]. The drain current was fitted by adjusting the doping profile, ballistic coefficient, and saturation velocity. The doping profile was changed to fit the subthreshold swing and DIBL since the doping profile is deeply concerned with the device behaviors in the subthreshold region. The ballistic coefficient was tuned to fit the drain current in the linear region, and the saturation velocity was set to fit the drain current in the saturation region. We extracted the on-state current (I on ) and gate capacitance (C gg ) at |V gs | = 0.7 V and |V ds | = 0.7 V. Moreover, the off-state current (I off ) and parasitic capacitance (C para ) were extracted at |V gs | = 0 V and |V ds | = 0.7 V.  Figure 2 shows the transfer curves of NSFETs with different T IS,B for T SD = 0 and 5 nm. No significant dependence of the DC performance on ∆T IS,B was observed at T SD = 0 ( Figure 2a). By contrast, at T SD = 5 nm, the I off increased significantly as T IS,B increased ( Figure 2b). The T SD typically impacts the I off of tr pbt [17], where T IS,B determines the L G of tr pbt . Because the L G of tr pbt affects the gate controllability over the PTS region, an increase in ∆T IS,B significantly degrades the DC performance. As an increase in T SD degrades the gate controllability of tr pbt , T IS,B is a critical factor determining the parasitic punch-through current (I pt ) in the PTS region. Therefore, the subthreshold swing and DIBL are significantly degraded, as shown in the inset of Figure 2 and Table 2.   Figure 2 shows the transfer curves of NSFETs with different TIS,B for TSD = 0 and 5 nm. No significant dependence of the DC performance on ΔTIS,B was observed at TSD = 0 ( Figure  2a). By contrast, at TSD = 5 nm, the Ioff increased significantly as TIS,B increased ( Figure 2b). The TSD typically impacts the Ioff of trpbt [17], where TIS,B determines the LG of trpbt. Because the LG of trpbt affects the gate controllability over the PTS region, an increase in ΔTIS,B significantly degrades the DC performance. As an increase in TSD degrades the gate controllability of trpbt, TIS,B is a critical factor determining the parasitic punch-through current (Ipt) in the PTS region. Therefore, the subthreshold swing and DIBL are significantly degraded, as shown in the inset of Figure 2 and Table 2.    NFETs   3  60  67  5  62  72  7  67  81   PFETs   3  51  54  5  53  57  7 58 61

Type T IS,B [nm] DIBL [mV/V] T SD = 0 nm T SD = 5 nm
The I off sensitivities to the T/M/B ∆T IS (S Ioff,T /S Ioff,M /S Ioff,B ) are compared in Figure 3. We defined S Ioff as the slope of I off −∆T IS , which indicates how sensitively I off varies with respect to ∆T IS . For the NFETs with T SD = 0 nm, the S Ioff,T (0.208) and S Ioff,M (0.228) slightly exceeded the S Ioff,B (0.104 nA/nm), and similar S Ioff tendencies were observed for the PFETs. The T SD variation not only increased I off , but also significantly increased S Ioff,B for both the NFETs and the PFETs. The S Ioff,B for the NFETs is greater than that for the PFETs, which is mainly attributed to the S/D dopant diffusion into the PTS region. Phosphorus has a higher diffusivity than boron; therefore, more S/D dopant diffuses into the PTS region in NFETs than in PFETs [30]. Consequently, the NFETs are more sensitive to the ∆T IS,B in terms of I off . For the NFETs with T SD = 5 nm, S Ioff,T , S Ioff,M , and S Ioff,B were 0.195, 0.209, and 2.34 nA/nm, respectively. S Ioff,T and S Ioff,M were almost identical regardless of the T SD , but S Ioff,B increased by a factor of 22.5 when the T SD increased from 0 to 5 nm. This indicated that the S/D recess process variation slightly affects S Ioff,T and S Ioff,M but significantly affects S Ioff,B . Thus, if the T SD variation is not perfectly eliminated, ∆T IS,B should be controlled below 1 nm, because devices with greater than 10 times in I off are not suitable for the intended system-on-chip applications.  NFETs   3  60  67  5  62  72  7  67  81   PFETs   3  51  54  5  53  57  7 58 61 The Ioff sensitivities to the T/M/B ΔTIS (SIoff,T/SIoff,M/SIoff,B) are compared in Figure 3. W defined SIoff as the slope of Ioff−ΔTIS, which indicates how sensitively Ioff varies with resp to ΔTIS. For the NFETs with TSD = 0 nm, the SIoff,T (0.208) and SIoff,M (0.228) slightly exceed the SIoff,B (0.104 nA/nm), and similar SIoff tendencies were observed for the PFETs. The T variation not only increased Ioff, but also significantly increased SIoff,B for both the NFE and the PFETs. The SIoff,B for the NFETs is greater than that for the PFETs, which is main attributed to the S/D dopant diffusion into the PTS region. Phosphorus has a higher d fusivity than boron; therefore, more S/D dopant diffuses into the PTS region in NFE than in PFETs [30]. Consequently, the NFETs are more sensitive to the ΔTIS,B in terms Ioff. For the NFETs with TSD = 5 nm, SIoff,T, SIoff,M, and SIoff,B were 0.195, 0.209, and 2.34 nA/n respectively. SIoff,T and SIoff,M were almost identical regardless of the TSD, but SIoff,B increas by a factor of 22.5 when the TSD increased from 0 to 5 nm. This indicated that the S/D rece process variation slightly affects SIoff,T and SIoff,M but significantly affects SIoff,B. Thus, if t TSD variation is not perfectly eliminated, ΔTIS,B should be controlled below 1 nm, becau devices with greater than 10 times in Ioff are not suitable for the intended system-on-ch applications. The differences in the SIoff shown in Figure 3 can be explained using the Ioff-dens profiles (Figure 4). In NSFETs with TSD = 0 nm, most carriers existed in the NS channe and a few were in the PTS region owing to the heavily doped PTS. Furthermore, ΔT induced Ioff density variations mainly arose in the NS channels next to the inner spac with variations in the thickness. Thus, the top and middle inner spacers adjacent to t NS channels with high carrier concentrations exhibited larger changes in the Ioff dens  The differences in the S Ioff shown in Figure 3 can be explained using the I off -density profiles (Figure 4). In NSFETs with T SD = 0 nm, most carriers existed in the NS channels, and a few were in the PTS region owing to the heavily doped PTS. Furthermore, ∆T ISinduced I off density variations mainly arose in the NS channels next to the inner spacer with variations in the thickness. Thus, the top and middle inner spacers adjacent to the NS channels with high carrier concentrations exhibited larger changes in the I off density than the bottom inner spacer. Therefore, S Ioff,T and S Ioff,M are higher than S Ioff,B for the NSFETs with T SD = 0 nm. By contrast, S Ioff,B was the highest when the T SD was 5 nm. Figure 4b shows the I off density profiles for NFETs with different T IS,B in the case of T SD = 5 nm. As T IS,B increased, the off-state I pt (I pt,off ) was not suppressed, resulting in a significant increase in I off , as shown in Figure 2. The I off density varied according to ∆T IS,B in the bottom NS and PTS regions but varied to a significantly larger extent in the PTS region. Specifically, the T SD variation significantly enhanced the effects of tr pbt on I off , and the change in I pt,off was a dominant factor in the S Ioff,B increment. This is because the PTS region was only controlled by the bottom gate. Therefore, the bottom gate could not effectively control the PTS region far from the bottom gate. As a result, worse short-channel effects (SCEs) were observed in the PTS region than in the NS channel.
Nanomaterials 2022, 12, x FOR PEER REVIEW 6 of 11 than the bottom inner spacer. Therefore, SIoff,T and SIoff,M are higher than SIoff,B for the NSFETs with TSD = 0 nm. By contrast, SIoff,B was the highest when the TSD was 5 nm. Figure  4b shows the Ioff density profiles for NFETs with different TIS,B in the case of TSD = 5 nm. As TIS,B increased, the off-state Ipt (Ipt,off) was not suppressed, resulting in a significant increase in Ioff, as shown in Figure 2. The Ioff density varied according to ΔTIS,B in the bottom NS and PTS regions but varied to a significantly larger extent in the PTS region. Specifically, the TSD variation significantly enhanced the effects of trpbt on Ioff, and the change in Ipt,off was a dominant factor in the SIoff,B increment. This is because the PTS region was only controlled by the bottom gate. Therefore, the bottom gate could not effectively control the PTS region far from the bottom gate. As a result, worse short-channel effects (SCEs) were observed in the PTS region than in the NS channel.   Figure 5a shows the conduction band energy (Ec) diagrams of the source-PTS-drain in the NFETs, which were extracted under the off-state bias condition. As the TSD increased from 0 to 5 nm, the significant reduction in the energy barrier height (Φb) from 478 to 402 mV was caused by the larger amount of S/D dopant diffusion into the PTS region at a TSD of 5 nm. In NFETs with TSD = 0 nm, the Φb of the PTS region was sufficiently high to control Ipt,off regardless of ΔTIS,B (Figure 5b). Therefore, Ioff can be effectively controlled even with ΔTIS,B. However, if Φb is not sufficiently high, the additional Φb reduction due to ΔTIS,B can be a critical factor in inducing Ipt,off. An additional Φb reduction was observed when TIS,B increased, and the change in Φb by ΔTIS,B significantly contributed to the Ipt,off variation (Figures 3 and 5c). Therefore, the bottom LG of trpbt, which is related to TIS,B, is important for suppressing SCEs in the PTS region. According to these results, SIoff,B is significantly affected by TSD. Thus, minimizing ΔTIS,B is more crucial when an over-etched S/D recess occurs.  Figure 5a shows the conduction band energy (E c ) diagrams of the source-PTS-drain in the NFETs, which were extracted under the off-state bias condition. As the T SD increased from 0 to 5 nm, the significant reduction in the energy barrier height (Φ b ) from 478 to 402 mV was caused by the larger amount of S/D dopant diffusion into the PTS region at a T SD of 5 nm. In NFETs with T SD = 0 nm, the Φ b of the PTS region was sufficiently high to control I pt,off regardless of ∆T IS,B (Figure 5b). Therefore, I off can be effectively controlled even with ∆T IS,B . However, if Φ b is not sufficiently high, the additional Φ b reduction due to ∆T IS,B can be a critical factor in inducing I pt,off . An additional Φ b reduction was observed when T IS,B increased, and the change in Φ b by ∆T IS,B significantly contributed to the I pt,off variation (Figures 3 and 5c). Therefore, the bottom L G of tr pbt , which is related to T IS,B , is important for suppressing SCEs in the PTS region. According to these results, S Ioff,B is significantly affected by T SD . Thus, minimizing ∆T IS,B is more crucial when an over-etched S/D recess occurs. Figure 6 shows the relationship between the on-state current (I on ) and ∆T IS , and the slope indicates the I on sensitivity (S Ion ). For the NFETs, the S Ion,T and S Ion,M are slightly higher than the S Ion,B regardless of the T SD . By contrast, for the PFETs, the S Ion,B varied significantly with respect to the T SD , leading to an increase in S Ion,B by a factor of 1.9. Thus, an increase in ∆T IS,B can cause severe I on variations when the T SD is not precisely controlled. The reason for the differences in the S Ion is explained in Figure 7.  Figure 6 shows the relationship between the on-state current (Ion) and ΔTIS, and the slope indicates the Ion sensitivity (SIon). For the NFETs, the SIon,T and SIon,M are slightly higher than the SIon,B regardless of the TSD. By contrast, for the PFETs, the SIon,B varied significantly with respect to the TSD, leading to an increase in SIon,B by a factor of 1.9. Thus, an increase in ΔTIS,B can cause severe Ion variations when the TSD is not precisely controlled. The reason for the differences in the SIon is explained in Figure 7.    Figure 6 shows the relationship between the on-state current (Ion) and ΔTIS, and slope indicates the Ion sensitivity (SIon). For the NFETs, the SIon,T and SIon,M are slightly hig than the SIon,B regardless of the TSD. By contrast, for the PFETs, the SIon,B varied significa with respect to the TSD, leading to an increase in SIon,B by a factor of 1.9. Thus, an incre in ΔTIS,B can cause severe Ion variations when the TSD is not precisely controlled. The rea for the differences in the SIon is explained in Figure 7.  The Rsd sensitivity (SRsd) and on-state Ipt (Ipt,on)-density variations to the ΔTIS account for the differences in T/M/B SIon (Figure 7). Rsd was extracted using Y-function techniques, as described in [31]. Two main factors determine SIon: Rsd and inversion charges in the PTS region. Additionally, the major factors affecting SIon depend on the TSD. For both the NFETs and PFETs with TSD = 0 nm, SIon was mainly affected by the change in Rsd, which consisted of the series S/D epi resistance (Repi) and extension resistance (Rext). Repi did not change with respect to ΔTIS, but Rext did. Because SRsd varied proportionally to the number of NS channels adjacent to the inner spacer where ΔTIS occurred (Figure 7a), SIon,T and SIon,M were greater than SIon,B. However, the inversion charges in the PTS region significantly affected SIon when TSD was 5 nm. As the deep TSD caused a substantial current to flow through trpbt, the Ion contribution of the PTS region was no longer small. The inversion charges in the PTS region should also be considered (Figure 7b). For the NFETs, the Ipt,on density in trpbt decreased slightly as TIS,B increased, whereas the large decrease in Ipt,on was observed for the PFETs. This is because higher SCEs and Vth reductions were observed in the NFETs, as the large amounts of diffused S/D dopants reduced Φb (Figures 2b and 5a). Therefore, in the NFETs, the Vth reduction of trpbt lowered the effects of the increase in Rsd, which was the dominant factor determining SIon,B. By contrast, in the PFETs, the Vth reduction of trpbt was small; thus, Ipt,on decreased significantly owing to the increase in the Rsd of trpbt. Consequently, SIon,B was the smallest for the NFETs, but for the PFETs, the TSD variation caused Ion to be most sensitive to ΔTIS,B.
Based on these results, we can provide two guidelines for controlling the DC performance variation, which depends on TSD. In the case of TSD = 0, precisely controlling TIS,T and TIS,M rather than TIS,B is effective for minimizing the variations in Ioff and Ion, as shown in Figures 3 and 6. However, considering the TSD variation, it is necessary to focus on the bottom inner spacer, because a precisely controlled TIS,B, can considerably reduce the performance variation. Otherwise, the effects of trpbt on the DC performance become large as TIS,B increases, resulting in the worst case with the highest Ioff and lowest Ion in PFETs, which significantly diminishes the performance advantages of NSFETs.
The gate capacitance (Cgg) with respect to ΔTIS for NSFETs (TSD = 0) is shown in Figure  8, and Cgg is decomposed into the intrinsic capacitance (Cint) and parasitic capacitance (Cpara). Cpara was extracted under the off-state bias, and Cint was calculated by subtracting The R sd sensitivity (S Rsd ) and on-state I pt (I pt,on )-density variations to the ∆T IS account for the differences in T/M/B S Ion (Figure 7). R sd was extracted using Y-function techniques, as described in [31]. Two main factors determine S Ion : R sd and inversion charges in the PTS region. Additionally, the major factors affecting S Ion depend on the T SD . For both the NFETs and PFETs with T SD = 0 nm, S Ion was mainly affected by the change in R sd , which consisted of the series S/D epi resistance (R epi ) and extension resistance (R ext ). R epi did not change with respect to ∆T IS , but R ext did. Because S Rsd varied proportionally to the number of NS channels adjacent to the inner spacer where ∆T IS occurred (Figure 7a), S Ion,T and S Ion,M were greater than S Ion,B . However, the inversion charges in the PTS region significantly affected S Ion when T SD was 5 nm. As the deep T SD caused a substantial current to flow through tr pbt , the I on contribution of the PTS region was no longer small. The inversion charges in the PTS region should also be considered (Figure 7b). For the NFETs, the I pt,on density in tr pbt decreased slightly as T IS,B increased, whereas the large decrease in I pt,on was observed for the PFETs. This is because higher SCEs and V th reductions were observed in the NFETs, as the large amounts of diffused S/D dopants reduced Φ b (Figures 2b and 5a). Therefore, in the NFETs, the V th reduction of tr pbt lowered the effects of the increase in R sd , which was the dominant factor determining S Ion,B . By contrast, in the PFETs, the V th reduction of tr pbt was small; thus, I pt,on decreased significantly owing to the increase in the R sd of tr pbt . Consequently, S Ion,B was the smallest for the NFETs, but for the PFETs, the T SD variation caused I on to be most sensitive to ∆T IS,B .
Based on these results, we can provide two guidelines for controlling the DC performance variation, which depends on T SD . In the case of T SD = 0, precisely controlling T IS,T and T IS,M rather than T IS,B is effective for minimizing the variations in I off and I on , as shown in Figures 3 and 6. However, considering the T SD variation, it is necessary to focus on the bottom inner spacer, because a precisely controlled T IS,B , can considerably reduce the performance variation. Otherwise, the effects of tr pbt on the DC performance become large as T IS,B increases, resulting in the worst case with the highest I off and lowest I on in PFETs, which significantly diminishes the performance advantages of NSFETs.
The gate capacitance (C gg ) with respect to ∆T IS for NSFETs (T SD = 0) is shown in Figure 8, and C gg is decomposed into the intrinsic capacitance (C int ) and parasitic capac-itance (C para ). C para was extracted under the off-state bias, and C int was calculated by subtracting C para from C gg under the on-state bias. As shown in Figure 8a, the differences in the C gg sensitivity to T/M/B ∆T IS (S Cgg ) were small. However, the changes in C int and C para for each ∆T IS did not have the same sensitivity. C para , which was determined by the fringing field between the gate and S/D, was affected by the T IS . Therefore, the sensitivity of C para to ∆T IS was almost identical among the T/M/B ∆T IS (Figure 8b). However, the sensitivity of C int to ∆T IS,B was lower than those of ∆T IS,T and ∆T IS,M (Figure 8c). Although the inversion charge variations caused by ∆T IS,B mainly occurred in the bottom NS and PTS regions, the charge variations in the PTS region were smaller than those in the NS channels, leading to different AC sensitivities to the T/M/B ∆T IS . However, because the differences in the C int sensitivity to the T/M/B ∆T IS were not large, it can be concluded that the overall performance sensitivity difference induced by each ∆T IS has greater effects on DC (I off , I on ) rather than the AC performance. Cpara from Cgg under the on-state bias. As shown in Figure 8a, the differences in the Cgg sensitivity to T/M/B ΔTIS (SCgg) were small. However, the changes in Cint and Cpara for each ΔTIS did not have the same sensitivity. Cpara, which was determined by the fringing field between the gate and S/D, was affected by the TIS. Therefore, the sensitivity of Cpara to ΔTIS was almost identical among the T/M/B ΔTIS (Figure 8b). However, the sensitivity of Cint to ΔTIS,B was lower than those of ΔTIS,T and ΔTIS,M (Figure 8c). Although the inversion charge variations caused by ΔTIS,B mainly occurred in the bottom NS and PTS regions, the charge variations in the PTS region were smaller than those in the NS channels, leading to different AC sensitivities to the T/M/B ΔTIS. However, because the differences in the Cint sensitivity to the T/M/B ΔTIS were not large, it can be concluded that the overall performance sensitivity difference induced by each ΔTIS has greater effects on DC (Ioff, Ion) rather than the AC performance.

Conclusions
The sensitivities of the DC/AC performance to the T/M/B ΔTIS in sub-3-nm node NSFETs were quantitatively investigated using a fully calibrated TCAD simulation. The DC performance sensitivities (Ioff, Ion) to the T/M/B ΔTIS differed. However, there were no significant differences in the AC sensitivities. One of the notable results was that ΔTIS, which varied the performance the most, was different according to the TSD variations. In NSFETs with TSD = 0 nm, SIoff,B was lower than SIoff,T and SIoff,M because the effects of ΔTIS,B were primarily observed in the bottom NS channel. However, trpbt was no longer negligible when the TSD was 5 nm. Thus, if the TSD variation is not controlled, NFETs (PFETs) have higher SIoff,B (SIon,B) because of the effects of trpbt. It can be concluded that the bottom

Conclusions
The sensitivities of the DC/AC performance to the T/M/B ∆T IS in sub-3-nm node NSFETs were quantitatively investigated using a fully calibrated TCAD simulation. The DC performance sensitivities (I off , I on ) to the T/M/B ∆T IS differed. However, there were no significant differences in the AC sensitivities. One of the notable results was that ∆T IS , which varied the performance the most, was different according to the T SD variations. In NSFETs with T SD = 0 nm, S Ioff,B was lower than S Ioff,T and S Ioff,M because the effects of ∆T IS,B were primarily observed in the bottom NS channel. However, tr pbt was no longer negligible when the T SD was 5 nm. Thus, if the T SD variation is not controlled, NFETs (PFETs) have higher S Ioff,B (S Ion,B ) because of the effects of tr pbt . It can be concluded that the bottom inner spacer is the element with the most significant effect on the DC/AC performance. Hence, reducing ∆T IS,B is important for yield enhancement.