Search Results (49)

NanoArduSiPM represents a paradigm shift in the ArduSiPM (Architected Detection Unit for Silicon Photomultipliers) roadmap, evolving from a standalone instrument into a high-density modular building block (36 mm × 42 mm × 3 mm, 7 g). This revision does not merely pursue miniaturization; it re-engineers the signal-processing chain to maintain high performance within a scaled-down footprint, enabling the transition from single-unit detection to scalable, distributed multi-detector systems. NanoArduSiPM is based on a three-layer architecture comprising an external scintillator and Silicon Photomultiplier (SiPM) detection module, a dedicated high-speed discrete analog front-end, and a System-on-Chip (SoC) for embedded acquisition and processing. The physical implementation adopts high-integrity PCB routing and rigorous isolation techniques designed to suppress digital–analog coupling, a critical requirement in such a compact form factor. This deterministic layout strategy provides the architectural foundation for time-tagging capabilities, currently under quantitative characterization, by addressing the fundamental sources of signal interference at the hardware level. Beyond hardware integration, NanoArduSiPM introduces the capability for extended firmware functionality, including event tagging via external inputs and the implementation of coincidence and veto logic. This framework supports the acquisition of multiple correlated histograms and allows multiple units to be interconnected on a shared SPI bus. By shifting from standalone operation to a coordinated, hierarchical architecture, NanoArduSiPM enables distributed detection schemes where event selection and correlation are handled natively within the system, reducing the dependency on external data acquisition electronics. The compact modular architecture, together with the high-performance discrete analog front-end and embedded data handling, makes NanoArduSiPM suitable for applications where low mass and low power consumption are critical, targeting applications such as space-based payloads, laboratory instrumentation, remote sensing, and large-scale distributed multi-channel detection systems. While no radiation-tolerance qualification of the complete system has been performed in this work, the microcontroller family used in the design is also available in radiation-tolerant variants, which may support future implementations targeting more demanding radiation environments. Full article

Neuronal excitability manifests itself mainly in the form of non-linear, self-regenerative waves of electricity moving along the surface of neuronal axons. These waves are commonly known as action potentials (APs). Theoretical and experimental investigations of the physical and functional characteristics of APs have broadly followed along the lines of the ionic hypothesis and the associated mathematical model introduced by Hodgkin and Huxley (HH). In the current form of this bioelectrical framework, adopted in mainstream physiology and other biological sciences, the axonal membrane is conceptualized as an electronic circuit where electric current is generated and propelled as a result of the time-dependent opening and closure of voltage-operated ion channel proteins, allowing passive flow of specific ions across and along the membrane, powered by their respective electrochemical gradients. Although representing mainstream research, the bioelectric perspective has been criticized for its narrow focus on the electrical characteristics of APs, whilst ignoring other physical manifestations of the nerve signal, particularly mechanical and thermal changes coinciding with AP propagation. As an alternative, a macroscopic thermodynamics-based acoustic theory has been outlined, in which all electric and non-electric manifestations of the nerve signal are considered as a result of a single density pulse in the axonal membrane carried by a reversible lipid membrane phase transition and momentum conservation. Representing a minority view, however, this unified, acoustic perspective on the physical nature of neuronal excitability is largely ignored by representatives of the bioelectric perspective. Here, we draw special attention to the philosophical dimension of the communication failure between the two communities of scientists. We argue that adherents of the bioelectric perspective favor a mechanist type of explanation, whilst supporters of the acoustic perspective are committed to so-called covering-law types of explanation. We conclude that it is this thus far unrecognized philosophical rift, rather than specific scientific differences in opinion, that blocks fruitful interdisciplinary cooperation necessary for building a comprehensive, fully integrated notion of the physical nature of neuronal excitability. Suggestions of how to bridge this conceptual gap are formulated. Full article

Optical synaptic transistors employing polymer dielectrics have emerged as promising building blocks for neuromorphic computing due to their low power consumption and rich photo-induced memory behaviors. While extensive experimental studies have demonstrated various synaptic functions, a unified physical understanding of the coupled charge trapping and ionic polarization processes governing device dynamics remains incomplete. In this work, we develop a unified physical model to investigate optical synaptic behaviors in polymer-based transistors with oxide interlayers. The model explicitly describes the time-dependent evolution of photo-induced charge trapping at the semiconductor–dielectric interface and ionic polarization within the polymer dielectric, which jointly modulate the effective threshold voltage of the transistor channel. Based on this framework, key synaptic functions including excitatory postsynaptic current (EPSC), paired-pulse facilitation (PPF), and pulse-dependent potentiation are quantitatively reproduced. The model further reveals how dielectric structure and trapping strength govern the transition between short-term and long-term plasticity. This study provides a physically intuitive and experimentally relevant modeling framework for understanding optical synaptic transistors, offering guidance for the rational design and optimization of polymer-based neuromorphic devices. Although simplified, the proposed model captures the essential physics governing optical synaptic behaviors and provides a general framework applicable to a wide class of ion–electronic neuromorphic devices. Experimental measurements are used as physically motivated proxies to validate the multi-timescale structure of the model rather than direct numerical fitting. Full article

Traditional complementary metal-oxide-semiconductor (CMOS) logic gates serve as the fundamental building blocks of modern computing, operating through the electron charge manipulation wherein binary information is encoded as distinct high- and low-voltage states. However, as physical dimensions approach the quantum limit, conventional logic gates encounter fundamental bottlenecks, including power consumption barriers, memory limitations, and a significant increase in static power dissipation. Consequently, the pursuit of novel low-power computing methodologies has emerged as a research hotspot in the post-Moore era. Logic gates based on magnetic skyrmions constitute a highly promising candidate in this context. Magnetic skyrmions, nanoscale quasiparticles endowed with topological protection, offer ideal carriers for information transmission due to their exceptional stability and mobility. In this work, we provide a concise overview of the current development status and underlying operating principles of magnetic skyrmion logic gates across various magnetic materials, including ferromagnetic, synthetic antiferromagnetic, and antiferromagnetic systems. The introduction of magnetic skyrmion-based logical operations represents a paradigm shift from traditional Boolean logic to architectures integrating memory and computation, as well as brain-inspired neuromorphic computing. Although significant challenges remain in the synthesis of materials, fabrication, and detection, magnetic skyrmion-based logic computing holds considerable potential as a future ultra-low-power computing technology. Full article

Amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) have emerged as promising candidates for next-generation large-area and low-power electronics due to their high mobility, low leakage current, and compatibility with low-temperature fabrication on flexible or transparent substrates. In this work, we report the fabrication of bottom-gate a-IGZO NMOS TFTs using HfO₂ as high-k gate dielectric and Mo top contacts. The devices were electrically characterized through capacitance–voltage (C–V) and current–voltage (I–V) measurements, from which key parameters were extracted. Based on these transistors, we designed, fabricated, and characterized inverters employing four different load configurations: resistive, diode, depletion, and pseudo-CMOS. A comparative analysis was performed in terms of voltage transfer characteristics (VTCs), gain, and noise margins, highlighting that depletion-load inverters offer the highest gain and robust noise margins. Finally, a two-channel multiplexer was designed and fabricated. The multiplexer was characterized under both square and sinusoidal input signals up to 1 kHz, demonstrating correct channel selection and robust switching behavior. These results confirm the potential of a-IGZO TFT-based circuits as building blocks for low-power and high-reliability digital and mixed-signal electronics. Full article

The increased penetration of power electronics interfaced resources in modern power systems is unlocking new opportunities and challenges. New concepts like multiport converters can further enhance the efficiency and power density of power electronics-based solutions. The triple active bridge is an isolated multiport converter with soft switching and high voltage gain that can integrate different sources, storage, and loads, or act as a building block for modular systems. However, the triple active bridge suffers from power flow cross-coupling, which affects its dynamic performance if it is not removed or mitigated. Unlike the extensive literature on two-port power converters, studies on modeling and control comparison for multiport converters are still lacking. Therefore, this paper presents and compares different modeling and decoupling control approaches applied to the triple active bridge converter, highlighting their benefits and limitations. The converter operation and modulation are introduced, and modeling and control strategies based on the single phase shift power flow control are detailed. The switching model, generalized full-order average model, and the reduced-order model derivations are presented thoroughly, and a comparison reveals that first harmonic approximations can be detrimental when modeling the triple active bridge. Furthermore, the model accuracy is highly sensitive to the operating point, showing that the generalized average model better represents some dynamics than the lossless reduced-order model. Furthermore, three decoupling control strategies are derived aiming to mitigate cross-coupling effects to ensure decoupled power flow and improve system stability. To assess their performance, the TAB converter is subjected to power and voltage disturbances and parameter uncertainty. A comprehensive comparison reveals that linear PI controllers with an inverse decoupling matrix can effectively control the TAB but exhibit large settling time and voltage deviations due to persistent cross-coupling. Furthermore, the decoupling matrix is highly sensitive to inaccuracies in the converter’s model parameters. In contrast, linear active disturbance rejection control and sliding mode control based on a linear extended state observer achieve rapid stabilization, demonstrating strong decoupling capability under disturbances. Furthermore, both control strategies demonstrate robust performance under parameter uncertainty. Full article

This position paper extends the author’s keynote address from the 2024 IEEE European Solid-State Electronics Research Conference, offering a perspective on effective strategies for the advancement of analog and mixed-signal (AMS) integrated circuit (IC) design. It is argued that traditional methodologies, characterized by their focus on transistor-level optimization within individual sub-blocks, are insufficient for satisfying the stringent performance and power consumption demands of contemporary information and communication technologies (ICT), especially in the context of expanding AI applications. Consequently, a paradigm shift is necessary, emphasizing “full-stack” solutions that prioritize comprehensive system-level analysis and aim to minimize physical resources and reduce complexity by innovating across the established boundaries of design abstraction levels. Building on prior work, this manuscript offers a more thorough justification for the proposed full-stack analog design methodology, supported by broader evidence and more comprehensive discussion. It also identifies key considerations regarding EDA and workforce development as topics for future work. Full article

Phase-Locked Loops (PLLs) are fundamental building blocks in modern electronic systems, enabling precise frequency synthesis, signal synchronization, and clock generation. This paper provides a comprehensive system-level analysis of PLLs, covering their fundamental operation, key architectures, performance considerations, and applications in emerging technologies. Additionally, this paper discusses current challenges and future trends in PLL design, including low-power optimization, noise reduction, and integration with machine learning techniques. Full article

The rapid development of wearable electronics requires multifunctional, transient electronic devices to reduce the ecological footprint and ensure data security. Unfortunately, existing transient electronic materials need to be degraded in chemical solvents or body fluids. Here, we report green luminescent, water-soluble, and biocompatible piezoelectric nanofibers developed by electrospinning green carbon quantum dots (G-CQDs), mulberry silk fibroin (SF), and polyvinyl alcohol (PVA). The introduction of G-CQDs significantly enhances the piezoelectric output of silk fibroin-based fiber materials. Meanwhile, the silk fibroin-based hybrid fibers maintain the photoluminescent response of G-CQDs without sacrificing valuable biocompatibility. Notably, the piezoelectric output of a G-CQD/PVA/SF fiber-based nanogenerator is more than three times higher than that of a PVA/SF fiber-based nanogenerator. This is one of the highest levels of state-of-the-art piezoelectric devices based on biological organic materials. As a proof of concept, in the actual scenario of a rope skipping exercise, the G-CQD/PVA/SF fiber-based nanogenerator is further employed as a self-powered wearable sensor for real-time sensing of athletic motions. It demonstrates high portability, good flexibility, and stable piezoresponse for smart sports applications. This class of water-disposable, piezo/photoactive biological materials could be compelling building blocks for applications in a new generation of versatile, transient, wearable/implantable devices. Full article

When a line-commutated converter–high-voltage direct current (LCC-HVDC) transmission system with large-scale integration of renewable energy encounters HVDC-blocking events, the sending-end power system is prone to transient overvoltage (TOV) risks. Renewable energy units that are connected via power electronic devices are susceptible to large-scale cascading disconnections due to electrical endurance and insulation limitations when subjected to an excessively high TOV, which poses a serious threat to the safe and stable operation of the system. Therefore, the prediction of TOV at renewable energy stations (RES) under DC blocking (DCB) scenarios is crucial for developing strategies for the high-voltage ride-through of renewable energy sources and ensuring system stability. In this paper, an approximate analytical expression for the TOV at RES under DCB fault conditions is firstly derived, based on a simplified equivalent circuit of the sending-end system that includes multiple DC transmission lines and RES, which can take into consideration the multiple renewable station short-circuit ratio (MRSCR). Building on this, a knowledge-embedded enhanced deep neural network (KEDNN) approach is proposed for predicting the RES’s TOV for complex power systems. By incorporating theoretical calculation values of the TOV into the input features, the task of the deep neural network (DNN) shifts from mining relationships within large datasets to revealing the correlation patterns between theoretical calculations and real values, thereby improving the robustness of the prediction model in cases of insufficient training data and irrational feature construction. Finally, the proposed method is tested on a real-world regional power system in China, and the results validate the effectiveness of the proposed method. The approximate analytical expression for the TOV at RES and the KEDNN-based TOV prediction method proposed in this paper can provide valuable references for scholars and engineers working in the field of power system operation and control, particularly in the areas of overvoltage theoretical calculation and mitigation. Full article

Quantum-dot cellular automata (QCA) is an emerging transistor-less field-coupled nanocomputing (FCN) approach to ultra-scale ‘nanochip’ integration. In QCA, to represent digital circuitry, electrostatic repulsion between electrons and the mechanism of electron tunnelling in quantum dots are used. QCA technology can surpass conventional complementary metal oxide semiconductor (CMOS) technology in terms of clock speed, reduced occupied chip area, and energy efficiency. To develop QCA circuits, irreversible majority gates are typically used as the primary components. Recently, some studies have introduced reversible design techniques, using reversible majority gates as the main building block, to develop ultra-energy-efficient QCA circuits. However, this approach resulted in time delays, an increase in the number of QCA cells used, and an increase in the chip area occupied. This work introduces a novel hybrid design strategy employing irreversible, reversible, and partially reversible QCA gates to establish an optimal balance between power consumption, delay time, and occupied area. This hybrid technique allows the designer to have more control over the circuit characteristics to meet different system needs. A combination of reversible, irreversible, and innovative partially reversible majority gates is used in the proposed hybrid design method. We evaluated the hybrid design method by examining the half-adder circuit as a case study. We developed four hybrid QCA half-adder circuits, each of which simultaneously incorporates various types of majority gates. The QCADesigner-E 2.2 simulation tool was used to simulate the performance and energy efficiency of the half-adders. This tool provides numerical results for the circuit input/output response and heat dissipation at the physical level within a microscopic quantum mechanical model. Full article

Photosynthesis, as the primary source of energy for all life forms, plays a crucial role in maintaining the global balance of energy, entropy, and enthalpy in living organisms. Among its various building blocks, photosystem I (PSI) is responsible for light-driven electron transfer, crucial for generating cellular reducing power. PSI acts as a light-driven plastocyanin-ferredoxin oxidoreductase and is situated in the thylakoid membranes of cyanobacteria and the chloroplasts of eukaryotic photosynthetic organisms. Comprehending the structure and function of the photosynthetic machinery is essential for understanding its mode of action. New insights are offered into the structure and function of PSI and its associated light-harvesting proteins, with a specific focus on the remarkable structural conservation of the core complex and high plasticity of the peripheral light-harvesting complexes. Full article

Forward body biasing (FBB) has often been exploited in the literature for improving the performance of both analog and digital building blocks. Recent works have explored the application of FBB variants to mixed-signal electronics and in particular to dynamic comparators, where these techniques can help to relax the trade-off between speed and power consumption at medium and low supply voltages. However, the literature lacks a structured analysis of the solutions that have been developed and of the trade-offs that affect them. This work attempts to fill the gap by providing a survey of the application of FBB techniques to dynamic comparators. The analysis focuses on the two most popular dynamic comparator topologies, the Strong Arm latch and Elzakker’s comparator. Several FBB variants are examined from a theoretical point of view. Moreover, the benefits and the limitations of the different approaches are assessed in terms of the main figures of merit through a systematic campaign of simulations in a 55 nm CMOS technology. Full article

Multiplication is a fundamental arithmetic operation in electronic processing units such as microprocessors and digital signal processors as it plays an important role in various computational tasks and applications. There exist many designs of synchronous multipliers in the literature. However, in the domain of Input–Output Mode (IOM) asynchronous design, there is relatively less published research on multipliers. Some existing works have considered quasi-delay-insensitive (QDI) asynchronous implementations of multipliers. However, the QDI asynchronous design paradigm, in general, is not area- and speed-efficient. This article presents an efficient alternative implementation of IOM asynchronous multipliers based on the concept of monotonic Boolean networks. The array multiplier architecture has been considered for demonstrating the usefulness of our proposition. The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). The multipliers were implemented using a 28 nm CMOS process technology. Full article

Quantum-dot cellular automata (QCA) are a promising nanoscale computing technology that exploits the quantum mechanical tunneling of electrons between quantum dots in a cell and electrostatic interaction between dots in neighboring cells. QCA can achieve higher speed, lower power, and smaller areas than conventional, complementary metal-oxide semiconductor (CMOS) technology. Developing QCA circuits in a logically and physically reversible manner can provide exceptional reductions in energy dissipation. The main challenge is to maintain reversibility down to the physical level. A crucial component of a computer’s central processing unit (CPU) is the arithmetic logic unit (ALU), which executes multiple logical and arithmetic functions on the data processed by the CPU. Current QCA ALU designs are either irreversible or logically reversible; however, they lack physical reversibility, a crucial requirement to increase energy efficiency. This paper shows a new multilayer design for a QCA ALU that can carry out 16 different operations and is both logically and physically reversible. The design is based on reversible majority gates, which are the key building blocks. We use QCADesigner-E software to simulate and evaluate energy dissipation. The proposed logically and physically reversible QCA ALU offers an improvement of 88.8% in energy efficiency. Compared to the next most efficient 16-operation QCA ALU, this ALU uses 51% fewer QCA cells and 47% less area. Full article