Search Results (5)

In high-throughput, high-concurrency, low-latency cryptographic scenarios, the throughput of public-key cryptography is a decisive performance metric. As China’s national elliptic curve cryptography standard, the SM2 signature algorithm has been widely adopted, yet scalar multiplication—the core primitive of SM2 signature—constitutes the dominant latency bottleneck. This paper proposes a high-throughput ASIC architecture that integrates precomputation with parallel task scheduling to accelerate SM2 signature generation. First, we design a Comb-algorithm-based precomputation hardware scheme for fixed-base scalar multiplication. The 256-bit scalar is partitioned into 32 segments, and 32 dedicated lookup tables are precomputed in on-chip SRAMs, which reduces fixed-base scalar multiplication to at most 31 elliptic curve point additions. Second, a six-arithmetic-unit parallel scheduling framework is developed for variable-base scalar multiplication. Equipped with two three-stage pipelined Montgomery multipliers and four modular adders, the design overlaps point addition and point doubling across pipeline stages to boost hardware resource utilization. Moreover, we build a 16-core parallel computing platform integrated with hardware task queues and DMA automatic scheduling, achieving efficient throughput scalability with the increase in core count. The proposed design has been taped out in the TSMC 28 nm CMOS process with completed physical design, including placement, clock tree synthesis, and routing. Post-layout simulation results, with full parasitic extraction (RC) and static timing analysis (STA), demonstrate that a single core achieves 89,593 signatures per second at a post-layout maximum frequency of 600 MHz. Its normalized area efficiency, measured as signatures per kilo gate equivalent (KGE), reaches 33.31 sig/s/KGE under the TSMC 28 nm process at 600 MHz. It should be noted that this metric is significantly influenced by the advanced process node and higher operating frequency; therefore, to enable a fairer assessment of intrinsic microarchitectural efficiency independent of process scaling, the frequency-normalized metric (sig/s/MHz/KGE) is adopted as the primary cross-design benchmark. Under this metric, our design achieves 55.5 × 10⁻³ sig/s/MHz/KGE, which is comparable to the 55.0 × 10⁻³ sig/s/MHz/KGE of the most area-efficient referenced design, with a marginal improvement of approximately 0.9%. The area efficiency comparison is presented only as a supplementary reference within a limited and clearly defined scope, acknowledging that the compared designs differ in functionality, process technology, and evaluation methodology. Furthermore, our design achieves the lowest Area–Time (AT) product of 30.03 KGE·ms among the compared works, indicating that our architectural innovation achieves a favorable AT trade-off for high-throughput applications rather than a fundamental shift in circuit efficiency. The 16-core parallel computing platform reaches an overall throughput of 1.03 million signatures per second. In addition, first-order arithmetic masking and key blinding are integrated into the scalar-multiplication data path to resist first-order side-channel attacks, and simulation-based TVLA evaluation indicates its leakage suppression capability under simulated conditions. Full article

This paper presents a rule-based LVS-driven methodology for parasitic RC extraction from CMOS layouts for post-layout SPICE simulation. The proposed approach operates directly within foundry-qualified rule environments, ensuring consistency with Process Design Kits (PDKs) and enabling seamless integration with existing design and verification flows without requiring field-solver execution during the production extraction flow. The methodology provides a generalized framework for deriving electrical parameters from layout geometries and is applicable to interconnects, contacts, vias, and gate structures in multilayer CMOS technologies. By decomposing conductive regions into directional components and applying geometric and Boolean operations, the method captures the impact of layout topology and process-dependent features on circuit-level behavior. In addition, a model-order reduction technique based on π-equivalent representations is introduced to simplify the resulting networks while preserving timing accuracy. This enables the scalable simulation of complex layouts with reduced computational overhead. The proposed framework supports layout optimization, variability-aware design, and process-technology co-design, particularly for mature and advanced planar nodes. The methodology is evaluated using register-file layout test cases and post-layout SPICE simulations. The results show that the proposed rule-based extraction and RC-merging flow preserve timing behavior while reducing netlist complexity. Full article

Conventional RC snubber design relies on oscillation frequency-based estimation, which is often influenced by uncontrolled parasitic elements and can therefore limit the accuracy of surge voltage prediction in GaN HEMT flyback converters. To overcome this limitation, a drain-voltage assessment-based design approach is introduced, in which the snubber parameters are extracted directly from the measured voltage characteristics during the turn off transition. This method allows the surge voltage to be modeled more precisely and enables the snubber capacitance to be selected without unnecessary oversizing. Simulation results using the GaN Systems GS66516T device show that the proposed approach reduces the total power loss by 27.67% and 21.84% relative to two empirical design methods and achieves up to 53.64% lower loss compared with other RC combinations in the explored design space. The method suppresses the surge voltage from 877 V to 556 V, which closely aligns with the design target of 550 V, whereas the empirical methods result in maximum voltages of 637 V and 603 V. Finally, the thermal feasibility of the snubber resistor is analytically assessed, indicating that the estimated temperature rise remains within the safe operating range of commercial components. Full article

A novel snapback-free superjunction reverse-conducting insulated gate bipolar transistor (SJ-RC-IGBT) is proposed and verified by simulation. In the SJ-RC-IGBT, the parasitic P/N/P/N structure as thyristor or Shockley diode demonstrates large conductivity due to an overabundance of carriers for reverse conduction. By preventing electrons from leaking across the N+ region at the collector side, the extra electron-blocking (EB) layer introduced in the SJ-RC-IGBT can dramatically enhance electron–hole pairs in the N/P-pillars. Hence, the SJ-RC-IGBT demonstrates a low on-state voltage (V_on). In addition, snapback-free characteristics and a large safe operating area (SOA) are also achieved in the SJ-RC-IGBT. During the turn-off process, a significant amount of electrons are extracted by parasitic MOS across the EB layer at the collector side to decrease the turn-off loss (E_off). According to the optimized results, the SJ-RC-IGBT with EB layer obtains an ultralow E_off of 3.9 mJ/cm² at V_on = 1.38 V with 88% and 81% decreases, respectively, compared with the conventional reverse-conducting IGBT (CRC-IGBT) and superjunction IGBT (SJ-IGBT). Full article

Three millimeter-wave (mm-Wave) power amplifiers (PAs) that cover the key 5G FR2 band of 24.25 to 43.5 GHz are designed in two different state-of-the-art device technologies and are presented in this work. First, a single-ended broadband PA that employs a third-order input matching network is designed in a 40 nm GaN/SiC HEMT (High Electron Mobility Transistor) technology. Good agreement between the measurement and post-layout parasitic extracted (PEX) electromagnetic (EM) simulation data is observed, and it achieves a measured 3-dB BW (bandwidth) of 18.0–40.3 GHz and >20% maximum PAE (power-added-efficiency) across the entire 20–44 GHz band. Expanding upon this measured design, a differential broadband GaN PA that utilizes neutralization capacitors is designed, laid out, and EM simulated. Simulation results indicate that this PA achieves 3-dB BW 20.1–44.3 GHz and maximum PAE > 23% across this range. Finally, a broadband mm-Wave differential CMOS PA using a cascode topology with RC feedback and neutralization capacitors is designed in a 22 nm FD-SOI (fully depleted silicon-on-insulator) CMOS technology. This PA achieves an outstanding measured 3-dB BW of 19.1–46.5 GHz and >12.5% maximum PAE across the entire frequency band. This CMOS PA as well as the single-ended GaN PA are tested with 256-QAM-modulated 5G NR signals with an instantaneous signal BW of 50/100/400/9 × 100 MHz at a PAPR (peak-to-average-power ratio) of 8 dB. The data exhibit impressive linearity vs. P_OUT trade-off and useful insights on CMOS vs. GaN PA linearity degradation against an increasing BW for potential mm-Wave 5G applications. Full article