Search Results (10)

In this work, an energy-efficient noise-shaping (NS) successive-approximation (SAR) capacitance-to-digital converter (CDC) is proposed. The interface is based on a direct-comparison technique, in which the sensor capacitance is compared directly to an on-chip binary weighted capacitive digital-to-analog converter (DAC). To implement NS, a 2nd order feed-forward loop filter processes the extracted residue at the end of each conversion cycle. Employing NS to achieve the target resolution leads to a small capacitive DAC and hence a small Si-area compared to the conventional SAR approach that would require a capacitive DAC with the same resolution as the overall CDC resolution. The proposed capacitive NS SAR sensor interface is designed and implemented in 130 nm CMOS technology for a 4 pF dynamic range and achieves an effective number of bits (ENOB) of 12.0 bits with a measurement time of 2.5 ms. The CDC dissipates 1.0 $\mathsf{\mu }$A from a 0.8 V supply resulting in a figure of merit (FoM) of 488 fJ/conversion-step. Full article

In this work, the system-level design of noise-shaping (NS) successive-approximation (SAR) analog-to-digital converters (ADCs) is investigated and analyzed. It is shown that despite the fact that the NS SAR architecture shares the same fundamental NS principle with the $\Sigma \Delta$ architecture, there are a few implementation differences that imply different considerations for optimum system-level design, particularly in the selection of the system oversampling ratio (OSR) and consequent resolution of the associated digital-to-analog converter (DAC) for a certain target overall resolution. In addition, the impacts of the OSR value on the power dissipation and figure-of-merit (FOM) are addressed in details. Full article

The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma ($\mathsf{\Delta }\Sigma$) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. This paper presents a tutorial for the design of NS-SAR ADC with capacitor stacking and buffering. The fundamental principle of the NS-SAR loop filter is analyzed, an ADC design example is provided, and the circuit implementation details with considerations on the non-idealities and trade-offs are discussed. This paper can be used as a tutorial for designing high-resolution and high-order NS-SAR ADC. Full article

This paper presents a novel second-order passive noise shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) based on active gain. The proposed scheme achieves a further improvement in the signal-to-noise ratio (SNR) of the proposed NS SAR ADC by reducing the kT/C noise and the conversion rate. After having presented the conversion principle, the theoretical analysis of the performance enhancement based on noise and other considerations is presented. Full article

A general overview of Noise-Shaping Successive Approximation Register (SAR) analog-to-digital converters is provided, encompassing the fundamentals, operational principles, and key architectures of Noise-Shaping SAR (NS SAR). Key challenges, including inherent errors in processing circuits, are examined, along with current advancements in architecture design. Various issues, such as loop filter optimization, implementation methods, and DAC network element mismatches, are explored, along with considerations for voltage converter performance. The design of dynamic comparators is examined, highlighting their critical role in the SAR ADC architecture. Various architectures of dynamic comparators are extensively explored, including optimization techniques, performance considerations, and emerging trends. Finally, emerging trends and future challenges in the field are discussed. Full article

This paper presents a first-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) with a process, (supply) voltage, and temperature (PVT)-insensitive closed-loop integrator and data-weighted averaging (DWA). The use of a cascode floating inverter amplifier (FIA)-type dynamic amplifier with high gain enables an aggressive noise transfer function while minimizing the power consumption associated with the use of an active filter. In the proposed ADC, the residue is generated by a capacitive digital-to-analog converter (CDAC) employing DWA, which is made possible by employing a second CDAC, which operates after the SAR operation is completed. The proposed ADC is designed with a 28 nm CMOS process with 1 V power supply. The simulation results show that the ADC achieves the SNDR of 71.2 dB and power consumption of 228 μW when operated with a sampling rate of 80 MS/s and oversampling ratio (OSR) of 10. The Schreier figure-of-merit (FoM) is 173.6 dB, and Walden FoM is 9.6 fJ/conversion-step. Full article

The noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC) is an innovative hybrid structure that offers performance advantages. The NS-SAR ADC leverages the SAR ADC as its foundation and combines oversampling technology and noise-shaping technology found in Sigma-Delta ADC. This integration effectively combines the strengths of both structures and enhances overall performance. The ADC features a simple circuit structure, compact chip area, and high energy efficiency, which has positioned it as a prominent research area. In this paper, leveraging the TSMC 65 nm GP process, the NS-SAR ADC is designed with a power supply voltage of 1 V. This design adopts an 8-bit differential capacitor structure, operates at a sampling frequency of 16 MS/s, and achieves an oversampling rate of 16 times the desired performance indicators. Through extensive circuit post simulation verification, the SNR obtained reaches 78 dB, providing an effective bit resolution of 12.7 bits. The core chip area of the ADC measures 366 × 333 μm², while the power consumption is impressively low at 417 μW and FoMs is 168 dB. Full article

In this paper, the most suited analog-to-digital (A/D) converters (ADCs) for Internet of Things (IoT) applications are compared in terms of complexity, dynamic performance, and energy efficiency. Among them, an innovative hybrid topology, a digital–delta (Δ) modulator (ΔM) ADC employing noise shaping (NS), is proposed. To implement the active building blocks, several standard-cell-based synthesizable comparators and amplifiers are examined and compared in terms of their key performance parameters. The simulation results of a fully synthesizable Digital-ΔM with NS using passive and standard-cell-based circuitry show a peak of 72.5 dB in the signal-to-noise and distortion ratio (SNDR) for a 113 kHz input signal and 1 MHz bandwidth (BW). The estimated ${\mathrm{FoM}}_{\mathrm{Walden}}$ is close to 16.2 fJ/conv.-step. Full article

The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e⁻ at 0 pF with a noise slope of 16.32 e⁻/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm² die area. Full article

Hough transform (HT) is a useful tool for both pattern recognition and image processing communities. In the view of pattern recognition, it can extract unique features for description of various shapes, such as lines, circles, ellipses, and etc. In the view of image processing, a dozen of applications can be handled with HT, such as lane detection for autonomous cars, blood cell detection in microscope images, and so on. As HT is a straight forward shape detector in a given image, its shape detection ability is low in noisy images. To alleviate its weakness on noisy images and improve its shape detection performance, in this paper, we proposed neutrosophic Hough transform (NHT). As it was proved earlier, neutrosophy theory based image processing applications were successful in noisy environments. To this end, the Hough space is initially transferred into the NS domain by calculating the NS membership triples (T, I, and F). An indeterminacy filtering is constructed where the neighborhood information is used in order to remove the indeterminacy in the spatial neighborhood of neutrosophic Hough space. The potential peaks are detected based on thresholding on the neutrosophic Hough space, and these peak locations are then used to detect the lines in the image domain. Extensive experiments on noisy and noise-free images are performed in order to show the efficiency of the proposed NHT algorithm. We also compared our proposed NHT with traditional HT and fuzzy HT methods on variety of images. The obtained results showed the efficiency of the proposed NHT on noisy images. Full article