# All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications

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## Abstract

**:**

## 1. Introduction

## 2. Most-Suited Analog-to-Digital Converter (ADC) Architectures for Internet of Things (IoT)

#### 2.1. Delta Modulator (ΔM) ADC

#### 2.2. SAR-ADC with Noise Shaping (NS)

#### 2.3. First-Order Delta–Sigma ($\Delta \Sigma $) Modulator ($\Delta \Sigma $M) ADC

#### 2.4. Delta–Delta–Sigma ($\Delta \Delta \Sigma $) Modulator ($\Delta \Delta \Sigma $M) ADC

#### 2.5. Proposed Hybrid ADC: Digital–Delta (Δ) Modulator (ΔM) with Noise Shaping (NS)

#### 2.6. Comparison among the Most-Suited Architectures

## 3. Standard-Cell-Based Active Building Blocks

#### 3.1. Dynamic Comparators Using Standard Logic Circuitry

#### 3.2. Inverter-Based OTA Topologies

- OTA 3: a single-path three-stage pseudodifferential Nagaraj integrator using a fully passive SC CMFB, as shown in Figure 14.

## 4. A Standard-Cell-Based Digital–Delta (Δ) Modulator (ΔM) with Noise Shaping (NS)

## 5. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 2.**SAR-ADC employing NS: (

**a**) block diagram and (

**b**) illustrative magnitude of STF, NTF and ${S}_{max}$.

**Figure 3.**First-order $\Delta \Sigma $M ADC: (

**a**) block diagram and (

**b**) illustrative magnitude of STF, NTF and ${S}_{max}$.

**Figure 4.**$\Delta \Delta \Sigma $M ADC [5]: (

**a**) block diagram and (

**b**) illustrative magnitude of STF, NTF and ${S}_{max}$.

**Figure 6.**Proposed digital-ΔM employing NS: (

**a**) block diagram and (

**b**) illustrative magnitude of STF, NTF and ${S}_{max}$.

**Figure 7.**GATE-based comparator proposed by Weaver et al. [19].

**Figure 9.**NAND-based four-input clocked comparator proposed by Ojima et al. [21].

**Figure 11.**Scheme of the SC integrator proposed by Nagaraj et al. [26].

**Figure 12.**OTA 1: a pseudodifferential inverter-based Nagaraj integrator with a fully passive SC CMFB circuit [24].

**Figure 13.**OTA 2: a pseudodifferential with a three-stage multipath inverter-based Nagaraj integrator [29].

**Figure 14.**OTA 3: a single path three-stage pseudodifferential Nagaraj integrator using a fully passive SC CMFB circuit [28].

**Figure 15.**Scheme of the proposed standard-cell-based digital-ΔM with NS employing a split-capacitive DAC, an inverter-based OTA topology, to perform NS and an OAI-based comparator.

**Figure 17.**Simulated output spectrum of the schematic of the proposed standard-cell-based digital-ΔM employing NS. This result was achieved using 2

^{14}points, M = 8, a BW of 1 MHz (OSR of 32), and a Fin of 113 kHz.

ADC Architecture | Complexity | Resolution | Energy Efficiency |
---|---|---|---|

ΔM | Low | Moderate | Low |

SAR-ADC with NS | Moderate | Moderate/high | Very good |

First-order $\Delta \Sigma $M | Low | Moderate/high | Good |

$\Delta \Delta \Sigma $M | Moderate | Moderate/high | Good |

Digital-ΔM with NS | Moderate | Moderate/high | Very good |

OTA 1 | OTA 2 | OTA 3 | |
---|---|---|---|

DC gain | Low | High | High |

GBW | High | High | Moderate |

Linearity ^{1} | Low | Moderate | Moderate |

Current consumption | Low | High | Moderate |

Circuit complexity | Two inverters | Ten inverters | Six inverters |

^{1}Considering 2/3 of the full-scale output.

**Table 3.**Summary of simulated results of the proposed standard-cell-based digital-ΔM employing NS using a 28 nm CMOS technology.

Parameter | Unit | Digital-DM with NS |
---|---|---|

${F}_{S}$ | MHz | 64 |

BW | MHz | 1 |

OSR | 32 | |

SNDR | dB | 72.50 |

ENOB | −bit | 11.8 |

${V}_{DD}$ | V | 0.9 |

Power dissipation | μW | 112 |

${\mathrm{FoM}}_{\mathrm{Walden}}$ | fJ/conv.-step | 16.2 |

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**MDPI and ACS Style**

Correia, A.; Tavares, V.G.; Barquinha, P.; Goes, J.
All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications. *J. Low Power Electron. Appl.* **2022**, *12*, 64.
https://doi.org/10.3390/jlpea12040064

**AMA Style**

Correia A, Tavares VG, Barquinha P, Goes J.
All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications. *Journal of Low Power Electronics and Applications*. 2022; 12(4):64.
https://doi.org/10.3390/jlpea12040064

**Chicago/Turabian Style**

Correia, Ana, Vítor Grade Tavares, Pedro Barquinha, and João Goes.
2022. "All-Standard-Cell-Based Analog-to-Digital Architectures Well-Suited for Internet of Things Applications" *Journal of Low Power Electronics and Applications* 12, no. 4: 64.
https://doi.org/10.3390/jlpea12040064