A Noise-Shaping SAR-Based Capacitance-to-Digital Converter for Sensing Applications

Abstract

In this work, an energy-efficient noise-shaping (NS) successive-approximation (SAR) capacitance-to-digital converter (CDC) is proposed. The interface is based on a direct-comparison technique, in which the sensor capacitance is compared directly to an on-chip binary weighted capacitive digital-to-analog converter (DAC). To implement NS, a 2nd order feed-forward loop filter processes the extracted residue at the end of each conversion cycle. Employing NS to achieve the target resolution leads to a small capacitive DAC and hence a small Si-area compared to the conventional SAR approach that would require a capacitive DAC with the same resolution as the overall CDC resolution. The proposed capacitive NS SAR sensor interface is designed and implemented in 130 nm CMOS technology for a 4 pF dynamic range and achieves an effective number of bits (ENOB) of 12.0 bits with a measurement time of 2.5 ms. The CDC dissipates 1.0 $\mathsf{\mu }$A from a 0.8 V supply resulting in a figure of merit (FoM) of 488 fJ/conversion-step.

1. Introduction

The demand for high-resolution, low-power capacitive sensor interfaces is consistently increasing to meet the growing market needs and to satisfy the emerging new applications in the consumer, industrial, automotive, and aerospace domains. These applications employ capacitive sensors for proximity sensing [1,2,3,4], pressure sensing [5,6,7,8,9,10,11], humidity sensing [12,13,14,15,16], inertial sensing [17,18,19,20,21], and biomedical applications [22,23]. These applications add emphasis on various aspects of the design, particularly cost, accuracy, and energy efficiency. Different CDC architectures have been reported in the literature to address this wide spectrum of applications. Most common architectures involve converting the input sensor capacitance to a voltage signal, which is then digitized by an analog-to-digital converter (ADC) stage to produce the output code. $\mathrm{\Delta }$$\Sigma$ architectures were reported in [4,24,25]. These architectures are mostly power hungry, require complex front-end signal conditioning circuits and are characterized by their large die area. SAR-based architectures were reported in [10,26,27,28]. The SAR architectures are shown to be energy efficient, with FoMs reaching sub 50 fJ/conversion-step. However, the energy efficiency of SAR architectures comes at the expense of their medium resolution. In addition, capacitive DACs require large die areas to meet the mismatch requirements of the overall target resolution. Dual-slope architectures have been reported in [29,30,31]. Dual-slope architectures are simple in design and require less of a die area since no DACs are used. However, such architectures are characterized by their large measurement time, which degrades the energy efficiency. Other architectures are based on time-domain solutions such that the variation in the sensor capacitance modulates the period, rise, or fall times, or the pulse width of a stable clock reference. Then, this variation of the time property of the stable clock reference is digitized using a time-to-digital converter (TDC) circuit to produce the output code. Reported in [32] is an interface based on period modulation (PM) such that the sensor capacitance modulates the oscillation frequency of a relaxation oscillator. Furthermore, a time-based CDC architecture is reported in [33]. This time-based solution varies the rise or fall time of an input clock reference in proportion to the sensor capacitance using current-starved inverters as delay cells, then the delays are digitized using a TDC circuit to produce the output code. An iterative-delay discharge time-domain solution is proposed in [34]. Time-domain solutions are simple in design, insensitive to process or supply scaling since the conversion process is performed in the time domain, and can be implemented in a much smaller die area compared to voltage-domain solutions. However, time-domain solutions require a stable clock reference for operation. Moreover, a TDC circuit is required to produce the output code, which can be power hungry when operating at high switching speeds. Also, the TDC resolution can limit the accuracy of the interface, thus degrading the energy efficiency.

Recently, NS SAR CDCs were reported [35,36]. The NS SAR CDC architecture combines the low-power advantage of SAR architectures with the noise-shaping advantage of $\mathrm{\Delta }$$\Sigma$ architectures such that the resolution of the conventional SAR is boosted due to noise-shaping without increasing the area of the capacitive DAC, resulting in better area utilization compared to a conventional SAR. Also in SAR architectures, the residue is available at the end of each conversion process on the top plate of the capacitive DAC. Thus, the residue can be exploited easily for NS [37]. In NS SAR architectures, the integrator processes only a small signal residue, unlike in $\mathrm{\Delta }$$\Sigma$ architectures, in which the integrator is driven by the input signal, and thus the linearity requirements are much more relaxed. Consequently, the power consumption is greatly reduced [37]. Therefore, NS SAR architectures can be optimal in terms of energy efficiency with much less complexity compared to $\mathrm{\Delta }$$\Sigma$ architectures, while achieving greater resolution relative to conventional SAR architectures. In [35], an error-feedback (EF) NS SAR CDC architecture is demonstrated with an FoM of 187 fF/conversion-step, while in [36], a fully dynamic cascaded-integrator feed-forward (CIFF) NS SAR architecture is presented with an FoM of 139 fF/conversion step.

In this paper, a CDC architecture is proposed, based on the direct-comparison SAR technique reported in [10], but further improves the performance by introducing NS. The direct comparison technique of [10] allows digital conversion without the need to a stable reference voltage. Furthermore, it can be easily adapted to interface to a wide range of sensor capacitance by only changing a current–mirror ratio. The application of NS to this technique can lead to additional advantages, as the target resolution would be achieved with a lower-resolution capacitive DAC, and consequently a lower area. More specifically, in this work, the CDC is designed to have a resolution of >12 bits for a 200 Hz Bandwidth, with the objective of achieving a low cost and a small area design. The system is designed for 13-bits, and 1-bit of degradation is budgeted for the circuit and thermal noise. An 8-bit DAC is used to limit the area of the design, and NS is adopted to achieve the remaining resolution bits. Knowing the remaining bits needed, the required oversampling ratio (OSR) is determined.

This paper is organized as follows. Section 2 explains the operation of the proposed NS SAR CDC architecture. In Section 3, the effect of nonidealities is analyzed. Section 4 demonstrates the implementation of the proposed system. The simulation results of the proposed system are presented in Section 5. The paper is concluded in Section 6.

2. The Proposed CDC Architecture

The block diagram of the proposed CDC architecture is shown in Figure 1. It is composed of a capacitive DAC (CAPDAC), an offset DAC (OFFDAC), two matched and equal charging current sources, and a multi-input comparator. These blocks form the core SAR converter. In addition, a two-stage loop filter is added to the system for residue processing. The multi-input comparator sums the core SAR converter and the loop-filter outputs and controls the SAR logic. Note that in the actual implementation, the comparator output is differential as detailed in Section 4.3.

Considering the SAR converter (ignoring the operation of the loop filter), the operation of the converter is as follows. During bit-cycling, each comparison cycle starts with a reset operation to discharge both the sensor capacitance and the CAPDAC. The equal and matched current sources, namely $I_{SENSE}$ and $I_{DAC}$, charge the sensor capacitance and the CAPDAC, respectively, for a specific charging interval ($T_{charge}$). At the end of the charging phase, the voltages $V_{sense}$ and $V_{DAC}$ are compared, indicating whether the sensor capacitance is smaller or greater than the CAPDAC value, setting the CAPDAC value for the next comparison cycle in a successive approximation fashion.

The sensor capacitance is composed of an offset fixed capacitance $C_{xo}$ and varying capacitance $\mathrm{\Delta }{C}_x$. To best utilize the dynamic range, the digital output of the converter $D_{OUT}$ only expresses the value of $\mathrm{\Delta }{C}_x$. The offset capacitance of the sensor is eliminated by using the same bit-cycling process explained above but using the OFFDAC such that at the end of the offset cancellation, the capacitance of the OFFDAC $\left(C_{OFFDAC}\right)$ is equal to $C_{x0}$. For $I_{SENSE}$ equal to $I_{DAC}$ (=I), and for offset capacitance cancellation performed before sensor capacitance conversion, the differential input voltage to the comparator, $\mathrm{\Delta }V=V_{sense}-V_{DAC}$, in cycle i is given by

$$\mathrm{\Delta }V\left[i\right]={\displaystyle \frac{I\times T_{charge}(C_{DAC}\left[i\right]-\mathrm{\Delta }{C}_x)}{(C_{DAC}\left[i\right]+C_{x0})(\mathrm{\Delta }{C}_x+C_{xo})}}$$

(1)

where $T_{charge}$ is the charging interval. For a CAPDAC of $N_{DAC}$ bits, the value of $T_{charge}$ is set such that $N_{DAC}$+1 cycles are completed within the conversion time. The extra cycle is used for the residue sampling proposed in this work, while the maximum conversion time is defined by the maximum target input signal frequency as detailed in [11].

In Equation (Section 2), the charging current is multiplied by the capacitances. Thus, it is obvious that a scaling factor can be applied to the sensor capacitance relative to the CAPDAC by using different values for $I_{SENSE}$ than for $I_{DAC}$, allowing the same CAPDAC to interface to sensors with different capacitance range. For unequal $I_{SENSE}$ and $I_{DAC}$, the sensor capacitance experiences a scaling factor equal to ${\displaystyle \frac{I_{DAC}}{I_{SENSE}}}$.

In this work, at the end of the SAR bit-cycling process, the residue voltage $\mathrm{\Delta }V$ is sampled for further processing by the loop filter, and the loop-filter output is fed to the comparator. This arrangement represents a cascaded-integrator feed-forward (CIFF) structure. This structure is more tolerant to the loop-filter gain error compared to the error-feedback (EF) architecture [37]. Therefore, CIFF is adopted for this work.

The loop filter is a cascade of a two-tap charge-based FIR filter, followed by a switched-capacitor integrator acting as an IIR filter to achieve high gain at low frequencies, thus improving the noise transfer function (NTF). This loop-filter structure was shown to be effective for NS in [38,39]. Denoting the coefficients of the FIR filter by ${\alpha }_1$ and ${\alpha }_2$ and denoting the quality factor of the switched-capacitor integrator by $k_A$, the filter transfer function $H_{CIFF}$ and the NTF of the system are given by the following equations, and the NTF is plotted in Figure 2, for ${\alpha }_1$ = 3, ${\alpha }_2$ = 1 and $k_A$ = 0.7:

$$H_{CIFF}\left(z\right)=({\alpha }_1{z}^{-1}+{\alpha }_2{z}^{-2})\left({\displaystyle \frac{k_A}{1-k_A{z}^{-1}}}\right)$$

(2)

$$NTF\left(z\right)={\displaystyle \frac{1-k_A{z}^{-1}}{1+k_A({\alpha }_1-1)z^{-1}+k_A{\alpha }_2{z}^{-2}}}$$

(3)

The timing diagram of the control signals of Figure 1 is shown in Figure 3. In the SAR phase, the SAR bits are resolved, while in the loop-filter phase, the loop filter processes the residue. The control signal ${\varphi }_{en}$ enables the conversion circuitry only when it is needed to save power and extends for a time $T_{conv}$. The control signal ${\mathsf{\Phi }}_c$ and ${\mathsf{\Phi }}_r$ are responsible for charging and discharging the sensor capacitance and the CAPDAC, respectively, in every bit cycle. The comparator sampling and latch operations are controlled by the signal ${\mathsf{\Phi }}_{latch}$. The control signal ${\mathsf{\Phi }}_s$ samples the residue, while ${\mathsf{\Phi }}_{A1}$, ${\mathsf{\Phi }}_{B1}$, ${\mathsf{\Phi }}_{A2}$, and ${\mathsf{\Phi }}_{B2}$ control the operation of the two-tap FIR stage. The control signal ${\mathsf{\Phi }}_{int}$ defines the integration phase of the loop-filter IIR integrator.

3. The Impact of Nonidealities

The effect of circuit nonidealities on the performance of SAR-based converters has been thoroughly studied in the literature [40]. Also, the differential operation of this design circuitry, combined with the relatively very-low-frequency clocks employed (with relatively relaxed rise and fall time) result in no significant charge injection related to the switched-capacitor operation of the loop filter. Therefore, the discussion in this section is limited to nonidealities that are more relevant to the proposed architecture operation; that is, the current mismatch between $I_{SENSE}$ and $I_{DAC}$. The expression in Equation (Section 2) assumes a perfect match between $I_{SENSE}$ and $I_{DAC}$. The impact of mismatch can be readily studied, assuming a $\mathrm{\Delta }I$ mismatch current such that $I_{SENSE}$ = I and $I_{DAC}$ = I + $\mathrm{\Delta }I$. In this case, the input voltage to the comparator becomes

$$\mathrm{\Delta }V\left[i\right]={\displaystyle \frac{I\times T_{charge}(C_{DAC}\left[i\right]-\mathrm{\Delta }{C}_x(1+\frac{\mathrm{\Delta }I}{I}))}{(C_{DAC}\left[i\right]+C_{x0})(\mathrm{\Delta }{C}_x+C_{xo})}}$$

(4)

Therefore, in this case, the $C_{DAC}$ is compared to $\mathrm{\Delta }{C}_x(1+{\displaystyle \frac{\mathrm{\Delta }I}{I}})$, which results in a gain error of $\mathrm{\Delta }I/I$. It is worth noting that the gain error can be fully eliminated if the same current source is used to charge the sensor capacitance and the CAPDAC capacitance, sequentially, and then enabling the comparator. However, this solution comes at the expense of an additional charging phase for each bit, doubling the conversion time. Nevertheless, in general, gain and offset errors of data-converters are straightforward to compensate for in the digital domain. Therefore, this solution is dropped.

4. Circuit-Level Implementation

In this section, the circuit-level implementation of the proposed CDC is discussed, highlighting some of the circuit details and the trade-offs involved.

4.1. The Charging Current Sources

The circuit diagram of the charging current sources $I_{SENSE}$ and $I_{DAC}$ is shown in Figure 4. Two current sources are used to generate the charging currents $I_{SENSE}$ and $I_{DAC}$. The switch $M_0$ enables the circuit during the SAR conversion phase, only. Transmission gates are used to implement the switches controlled by ${\varphi }_c$. $I_{bias1}$ is equal to 250 nA and is mirrored from $M_5$ to $M_6$ and $M_7$ with a mirroring ratio of value 1:8 to generate the 8.14 $\mathsf{\mu }$A charging currents $I_{SENSE}$ and $I_{DAC}$. In a practical implementation, $I_{Ibias1}$ is implemented as a programmable current such that the target charging currents values are maintained across process variation. The value of the charging currents is selected such that the maximum value of $V_{sense}$ or $V_{DAC}$ during $T_{Charge}$, at the minimum input capacitance, remains below $V_{DD}-V_{Headroom}$, where $V_{Headroom}$ is the DC voltage headroom of the current sources. It is worth noting that a small charging current results in a small input voltage to the comparator and therefore sets a more strict noise performance on the comparator and hence higher power dissipation. Since the charging current sources directly produce the input voltage to the comparator, the noise contribution of these current sources needs to be considered. The worst-case integrated noise power of each of the charging current sources is given by [11]

$$V_N^2={\displaystyle \frac{2}{3}}{\displaystyle \frac{KT}{C_{xo}}}{\displaystyle \frac{2}{\lambda v_{od}}}$$

(5)

where $v_{od}$ is the over-drive voltage of the current source transistor and $\lambda$ is the channel-length modulation constant. Therefore, a relatively large value for $V_{Headroom}$ is adopted, in the design, to allow a large $v_{od}$. A large $v_{od}$ reduces the noise contribution of the current sources (Equation (5)), and improves the current matching, and hence reduces the gain error (Equation (3)).

4.2. The Capacitive DAC

A regular binary-weighted 8-bit MIM capacitor array is used to implement the CAPDAC (Figure 5). The capacitance matching requirements are set by the differential non-linearity (DNL), and the limit for the minimum $C_u$ is determined by

$${\sigma }_{DNL}=2^{{\displaystyle \frac{N_{DAC}}{2}}}\times {\sigma }_{{\displaystyle \frac{\delta C}{C_u}}}$$

(6)

where ${\sigma }_{DNL}$ is the standard deviation of the DNL, and ${\sigma }_{{\displaystyle \frac{\delta C}{C_u}}}$ is the standard deviation of the unit capacitor, which in turn determines the minimum area of $C_u$. The unit capacitance $C_u$ is equal to 16.98 fF. The DAC is designed for a maximum DNL less than 0.1 LSB, to avoid quantization noise degradation due to mismatch. The capacitor units in the capacitive DAC are switched on or off using bottom plate switches to avoid the non-linear charge injection error.

4.3. The Multi-Input Comparator and Digital Processing

The multi-input comparator is a dual-differential pair latched comparator [38,41]. The schematic of the comparator is shown in Figure 6. One of the differential pairs is driven by $V_{SENSE}$ and $V_{DAC}$, while the other is driven by the differential output of the loop filter. When ${\varphi }_{latch}$ is high, both the CAPDAC residue voltage and the loop-filter output are sampled, and a differential voltage is created at $V_{o1}$ and $V_{o2}$. This differential voltage is applied to the two back-to-back inverters formed by M10, M11, M14, and M15. The back-to-back inverters form a latch producing rail-to-rail digital outputs. When ${\varphi }_{latch}$ is low, the input to the second stage latch is reset. The comparator is followed by an S-R latch to hold the output. The voltages $V_{DAC}$ and $V_{sense}$ vary by a relatively wide range. Therefore, the effective input common-mode signal to the differential pair varies considerably. Hence, the differential pairs are designed with a large input common-mode range. The smallest voltage that the comparator needs to resolve in this design is 649 $\mathsf{\mu }V$, corresponding to the LSB, and the comparator input-referred noise is 430 $\mathsf{\mu }{V}_{rms}$. This comparator noise is further reduced by the noise-shaping transfer function.

The comparator output is fed to regular SAR logic, followed by a decimation stage. The decimation filter is a third-order cascaded-integrator-comb (CIC) filter. The filter consists of three successive integrator stages formed of adders and unit delays in positive feedback that add the input sample and its unit-delayed version to form the cascaded integrator stage. The next stage is a down-sampler that down-samples the output samples of the cascaded integrator stage by the OSR ratio. Moreover, a comb stage exists after the down-sampler that subtracts the samples from its delayed version in three successive subtraction operations.

4.4. The Loop Filter

The loop filter is formed of two stages. The first stage is a two-tap FIR filter that has two capacitor banks, that is, the $C_{A1,2}$ capacitor bank and $C_{B1,2}$ capacitor bank (Figure 1). The FIR filter uses two capacitor banks because each sample of residue voltage contributes to two successive outputs (Equation (2)). The second stage is an inverting switched-capacitor integrator with a feedback capacitor $C_F$, such that ${\alpha }_1$ = $C_{A1,2}$/$C_F$ and ${\alpha }_2$ = $C_{B1,2}$/$C_F$. Since the residue-sampling switches handle a large input range of $V_{SENSE}$ and $V_{DAC}$, they are implemented as CMOS transmission gates. A low-gain two-stage amplifier is used for the second-stage integrator amplifier as shown in Figure 7. The bias current $I_{bias2}$ is 50 nA. For a well-defined output common mode, the second-stage load is resistive with a diode-connected device to generate a common-mode of value 400 mV, which is half the supply voltage $V_{DD}$.

5. Simulation Results

The proposed system is designed towards a 13-bits of resolution for a capacitance range of 4 pF. The circuits are implemented for $T_{conv}$ equal to 6 $\mathsf{\mu }$s, and $T_{charge}$ of 305 ns, and at a sampling frequency $f_s$ of 6.4 KHz (sampling period ($T_s$) of 156.25 $\mathsf{\mu }$s). Therefore, this leaves 150.25 $\mathsf{\mu }$s for the loop-filter phases. This long time interval relaxes the settling time of the loop filter, and thus its power consumption is also relaxed improving the energy efficiency of the interface. The input signal bandwidth is 200 Hz. That is, the OSR is 16. A higher OSR is avoided, since, in general, a low OSR is recommended for NS SAR for better efficiency [42]. The CDC circuitry is implemented in 130 nm CMOS technology. The layout of the proposed system is shown in Figure 8. The design occupies an area of 0.062 mm².

Detailed simulations are conducted for different blocks of the proposed architecture and for the overall system. The CAPDAC mismatch is simulated using Monte Carlo simulations, and the worst-case INL and DNL plots are shown in Figure 9 and Figure 10, respectively, indicating max INL and max DNL less than 0.1 LSB. For the charging current sources, the worst-case mismatch is simulated with 200 Monte Carlo runs. The mismatch plot of $I_{SENSE}$/$I_{DAC}$ is shown in Figure 11. The standard deviation 1 − $\sigma$ of the current sources mismatch is found to be equal to 207.5 nA, which is 2.5% for a mean value of 8.14 $\mathsf{\mu }$A.

The dynamic performance of the CDC is evaluated with transient noise simulations. The spectrum of the output is shown in Figure 12 for 1024 FFT points at an input signal frequency of 53.125 Hz. The resulting spectrum takes into account the quantization noise, flicker and thermal noise, and the non-linearity errors due to the CAPDAC settling and the absence of the sample-and-hold circuit. The system achieves a signal-to-noise-plus-distortion ratio (SNDR) of 74.0 dB. It is worth noting that the transient simulation without circuit noise achieves an SNDR of 78.8 dB. This means that circuit noise results in a 4.8 dB (0.8 bit) drop in the resolution.

The proposed CDC consumes 1.0 $\mathsf{\mu }$A from a supply voltage of 0.8 V. The breakdown of current consumption is tabulated in

Table 1. Current consumption breakdown of the proposed CDC.

Block	Current Consumption (nA)	Percentage %
Charging current sources	334	33.1
Multi-input comparator	50	5
Noise-shaping Filter	225	22.3
Digital and $C_{DAC}$ switching	400	39.6

. Note that the charging current sources are switched on for a time that is less than $2\%$ of the sampling period; therefore, a low average current is maintained. The same is true for the rest of circuits that are enabled only when needed.

Different performance metrics of the proposed system are compared to the state-of-the-art published works in

Table 2. Performance summary and comparison.

Specification	TIM’ 2019	JSSC’ 2022	ISSCC’ 2012	JSNA’ 2016	TCAS-I’ 2017	This
	[35]	[36]	[4]	[27]	[26]	Work *
Technology (nm)	180	180	350	180	180	130
Architecture	NS SAR	NS SAR	$\mathrm{\Delta }$$\Sigma$	SAR	SAR	NS SAR
Noise-Shaping Order	1st	2nd	3rd	-	-	2nd
Dynamic Range	Fixed	Fixed	Fixed	Fixed	Fixed	Scalable
Offset Cap. Cancel.	N/A	N/A	Yes	N/A	N/A	Yes
Supply Voltage (V)	0.8/1	1.8	3.3	0.9/1	0.8/1.2	0.8
Input Range (pF)	3.6	13.6	3.2	16.14	12.66	4
Meas. Time ($\mathsf{\mu }$S)	810	50	20	42.5	16	2500
Cap. Resolution ($a{F}_{rms}$)	150	172	65	1300	1200	282
Power Consump. ($\mathsf{\mu }$W)	1.59	63.28	15,000	3.84	6.44	0.8
Resolution (bits)	11	12	6	12	12	8
ENOB (bits)	12.74	14.5	13.8	11.8	11.6	12.0
SNDR (dB)	78.5	88.9	84.8	72.8	71.6	74.0
Area (mm2)	0.3	0.25	2.6	0.1	0.2	0.062
FoM (fJ/conv.-step)	187	139	20,823	45.8	33	488

* Simulation results.

. The FoM used in the table is Walden’s FoM, given by [35,36]

$$FoM={\displaystyle \frac{Power\times T_{measurement}}{2^{ENOB}}}$$

(7)

where $T_{measurement}$ is the measurement time, defined as $(T_s$× OSR). $T_{measurement}$ is equal to 2500 $\mathsf{\mu }s$ in this work. The table lists CDCs representing three different architectures: the SAR-based, the $\mathrm{\Delta }\Sigma$, and the NS SAR. The $\mathrm{\Delta }\Sigma$ has the highest FoM, indicating the architecture with the lowest energy efficiency. On the other hand, the SAR-based architectures are the most efficient. The proposed CDC of this work has a higher FoM than the other NS SAR implementations of [35,36], but it has a much lower area compared to the other NS SAR and all other architectures. This is attributed to the simplicity of the direct-comparison architecture, but more importantly to the utilization of NS that allows the use of a lower resolution and hence a much smaller 8-bit DAC, rather than a 13-bit CAPDAC to meet the target resolution. Therefore, overall, the proposed architecture has several advantages compared to the other architecture in the table. First, the proposed architecture can interface to a wide range of sensor capacitance, by simply implementing programmability in the charging currents. Other architectures can only interface to a fixed pre-set and designed for sensor capacitance. Second, the proposed architecture does not need an accurate reference voltage, which further adds to the architecture simplicity. Third, the architecture is inherently simple and does not need many blocks. Furthermore, employing NS allows a significant reduction in the Si-area, and hence, providing a low-cost solution, which can be crucial to some applications.

Finally, it should be noted that the reported results of this work are based on detailed transient noise simulations, rather than measurements, as is the case for the other work in the table. However, the main objective of the comparison is to show how the performance of the proposed architecture can fit with respect to the other reported architectures.

6. Conclusions

In this work, a CDC architecture is proposed, where NS is introduced to the SAR-based direct-comparison technique. The direct-comparison technique provides a simple capacitance conversion technique that can interface to a wide range of sensor capacitances by scaling the charging current sources relative to each other. Furthermore, it does not need an accurate voltage reference. The application of NS to this technique allows using a small low-resolution DAC to meet the higher target capacitance-to-digital-conversion resolution. This results in a significant reduction in area. In this implementation, an 8-bit DAC is used to target a 13-bit resolution, using a second-order FIR-IIR filter network in a feed-forward structure with an OSR of 16. The CDC is realized in 130 nm CMOS technology with an area of 0.062 mm² and achieves an SNDR of 74 dB with a measurement time of 2.5 ms. The CDC consumes 0.8 $\mathsf{\mu }$W. resulting in an FoM of 488 fJ/conversion-step.