Search Results (88)

Laboratory data from in-cell tests at and near open circuit potentials (OCV) and ex-situ H₂O₂ vapor exposure tests are used to develop a fluoride emission rate (FER) model for a state-of-the-art 12-µm thin, low equivalent weight, long-chain perfluorosulfonic acid (PFSA) ionomer membrane that is mechanically reinforced with expanded PTFE and chemically stabilized with 2 mol% cerium as an anti-oxidant. The anode FER at OCV linearly correlates with O₂ crossover from the cathode and the high yield of H₂O₂ at anode potentials, as observed in rotating ring disk electrode (RRDE) studies. The cathode FER may be linked to the energetic formation of reactive hydroxyl radicals (·OH) from the decomposition of H₂O₂ produced as an intermediate in the two-electron ORR pathway at high cathode potentials. Both anode and cathode FERs are significantly enhanced at low relative humidity and high temperatures. The modeled FER is strongly influenced by the gradients in water activity and cerium concentration that develops in operating fuel cells. Membrane stability maps are constructed to illustrate the relationship between the cell voltage, temperature, and relative humidity for FER thresholds that define H₂ crossover failure by chemical degradation over a specified lifetime. Full article

We present a chemiresistor sensor for NO₂ leaks. The sensor uses the organometallic semiconductor copper(II)phthalocyanine (CuPc), and is more easily manufactured and characterised than previously described organic transistor gas sensors. Resistance R is high but within the range of modern voltage buffers. The chemiresistor weakly responds to several gases, with either a small increase (NH₃ and H₂S) or decrease (SO₂) in R. However, the response is low at environmental pollution levels. The response to NO₂ also is near-zero for permitted long-term exposure. Our sensor is, therefore, not suited for environmental monitoring, but acceptable environmental pollutant levels do not interfere with the sensor. Above a threshold of ~87 ppb, the response to NO₂ becomes very strong. This response is presumably due to the doping of CuPc by the strongly oxidising NO₂, and is far stronger than for previously reported CuPc chemiresistors. We relate this to differences in the film morphology. Under 1 ppm NO₂, R drops by a factor of 870 vs. non-polluted air. An amount of 1 ppm NO₂ is far above the ‘background’ environmental pollution, thereby avoiding false alarms, but far below immediately life-threatening levels, thus giving time to evacuate. Our sensor is destined for leak detection in the nitrogen fertiliser industry, where NO₂ is an important intermediate. Full article

This study investigates the application of carbon nanotube (CNT)-enhanced epoxy adhesives for localised Joule heating-based curing in composite bonding. The electrical, thermal, and mechanical properties of epoxy with 0.25–1 wt% CNT loadings were evaluated. A simple CNT alignment method using DC voltage showed improved electrical conductivity, greatly reducing the percolation threshold. Transient thermal analysis using finite element modelling of representative volume elements revealed that aligned CNTs led to increased localised temperatures near the CNT clusters. The model was validated with infrared thermal imaging analysis, which also showed similar non-linear heat distribution and more uniform heating under higher CNT loading. Additionally, power distribution mapping was evaluated through inverse modelling techniques, suggesting different conductivity zones and cluster distribution within the single-lap joint. The numerical and experimental results demonstrated that CNT alignment significantly enhanced localised conductivity, thereby improving curing efficiency at lower voltages. The lap shear test results showed a peak shear strength of 10.16 MPa at 0.5 wt% CNT loading, 9% higher than pure epoxy. Scanning electron microscopy analysis confirmed the formation of aligned CNT clusters, and how CNT loading affected the failure modes, transitioning from cohesive to void-rich fracture patterns at a higher wt%. These findings establish CNT-enhanced Joule heating as a viable and scalable alternative for efficient composite bonding in aerospace and structural applications. Full article

3D-integrated GaN power modules can effectively reduce parasitic parameters and enhance the power system’s performance. However, the heat from each power chip during operation can lead to a mutual thermal coupling effect, potentially causing performance drift of the GaN power chips. This work investigates the impact of the thermal coupling effect in a 3D-integrated GaN power module on the characteristics of its GaN power chips. The GaN power chips’ characteristics are measured before and after the other power chips in the 3D-integrated GaN power module and after applying V_GS/V_DS = 3 V/1 V for 60 s. The results indicate that the thermal coupling effect in 3D-integrated GaN power modules can cause a rightward shift in the threshold voltage, reduce the response speed and on-state current, and also increase the leakage current of GaN power chips. In severe cases, the threshold voltage drift can reach up to 0.26 V, the device’s response time can increase by as much as 217 μs, the on-state current can decrease by 1.7 A, and the off-state leakage current can increase by more than 80 times. The impact of the thermal coupling effect is related to the direction of heat flow and the distance between chips. The closer the chips are to each other, the stronger the thermal coupling. It has a greater impact on the performance of chips near the bottom substrate and a lesser impact on the performance of chips at the top of the module. Typically, the influence of the thermal field generated by two chips working simultaneously is more significant than that of the thermal field generated by a single chip working alone. Full article

In this work, a cylindrical gate-all-around junctionless field effect transistor (JLFET) was investigated. Junctions and doping concentration gradients are unavailable in JLFET. According to the results, the suggested device has a novel architecture that significantly enhances transistor performance while exhibiting a decreased vulnerability to short-channel effects (SCEs). The Atlas 3D device simulator has been used to analyze the proposed JLFET’s performance, especially for low-power applications for different channel lengths ranging from 10 nm to 60 nm with Al_0.30Ga_0.60As as III-V materials. The comparative simulated study has been based on various performance parameters, including subthreshold slope (SS), drain-induced barrier lowering (DIBL), transconductance, threshold voltage, and I_ON to I_OFF ratio. The results of the simulations demonstrated that the III-V JLFET exhibited a favorable SS and decreased DIBL compared to other circuit topologies. In the suggested study, gallium arsenide (GaAs) and its compound materials have demonstrated a strong correlation between the SS and DIBL values. The SS is approximately 63 mV/dec, extremely near the ideal 60 mV/dec value. Gallium arsenide (GaAs) and aluminum gallium arsenide (AlGaAs) exhibit DIBL of approximately 30 mV/V and an SS value of around 64 mV/dec. Full article

The thermal through-silicon-via (TTSV) has a serious thermal stress problem due to the mismatch of the coefficient of thermal expansion between the Si substrate and filler metal. At present, the thermal stress characteristics and strain mechanism of TTSV are mainly concerned with increases in temperature, and its temperature range is concentrated between 173 and 573 K. By employing finite element analysis and a device simulation method based on temperature-dependent material properties, the impact of TTSV thermal stress on metal-oxide-semiconductor field-effect transistor (MOSFET) properties is investigated under cooling down from room temperature to the ultra-low temperature (20 mK), where the magnitude of thermal stress in TTSV is closely associated with the TTSV diameter and results in significant tension near the Cu-Si interface and consequently increasing the likelihood of delamination and cracking. Considering the piezoresistive effect of the Si substrate, both the TTSV diameter and the distance between TTSV and MOSFET are found to have more pronounced effects on electron mobility along [100] crystal orientation and hole mobility along [110] crystal orientation. Applying a gate voltage of 3 V, the saturation current for the 45 nm-NMOS transistor oriented along channel [100] experiences a variation as high as 34.3%. Moreover, the TTSV with a diameter of 25 μm generates a change in MOSFET threshold voltage up to −56.65 mV at a distance as short as 20 μm. The influences exerted by the diameter and distance are consistent across carrier mobility, saturation current, and threshold voltage parameters. Full article

With the growing demand for more efficient power conversion and silicon reaching its theoretical limit, wide bandgap semiconductor devices are emerging as a potential solution. For instance, Gallium Nitride (GaN)-based high-electron-mobility transistors (HEMTs) are getting more attention, and several structures for the normally off operation have been proposed. Adding an AlN interlayer in conventional AlGaN/GaN normally on HEMT structures is known to enhance the current density. In this work, the effect of an AlN interlayer in the normally off AlGaN/GaN MISHEMT with a buried p-region was investigated using a TCAD simulation from Silvaco. The added AlN interlayer increases the two-dimensional electron gas density, requiring a higher p-doping concentration to achieve the same threshold voltage. The simulation results show that the overall effect is a reduction in the device’s current density and peak transconductance by 21.83% and 44.4%, respectively. Further analysis of the current profile shows that because of the buried p-region and at high gate voltages, the current flows near the AlGaN/GaN interface and along the insulator/AlGaN interface. Adding an AlN interface blocks the migration of channel electrons to the insulator/AlGaN interface, resulting in a lower current density. Full article

In robotic arm controllers, the ability to shift signal levels is crucial for interfacing between different voltage domains in a processor. The level shifter (LS) has been used to convert signals operating near threshold voltage to signals operating well above the threshold voltage. Researchers have developed current mirror-based LSs to employ current mirrors, which duplicate the current from one transistor and accurately replicate it in another, ensuring precise current matching. In this research, a dynamic inverter-based level shifter (DIBLS) with an error correction circuit is implemented. One of the main issues addressed by DIBLS is the problem of current disagreement. Current disagreement arises when multiple circuit components attempt to draw current from a common source, which leads to operational problems. Furthermore, DIBLS includes a feedback inverter controlled by the output node; this feedback inverter likely plays a pivotal role in controlling and stabilizing the output voltage of operation of the LS. The results demonstrate that DIBLS offers notable advantages on increased operational speed. This speed improvement has been achieved by circumventing the threshold voltage drop associated with the feedback of the inverter and by ensuring complete output swing, addressing stability issues. Voltage shifting between 0.3 V and 1.2 V at 1 MHz having power consumption is 16.57 nW, delay 0.22 ns, and energy per transition 32.25 fJ. The entire process is executed in 45 nm in CMOS technology. Full article

This work investigates the gate oxide reliability of commercial 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) with planar and trench gate structures. The performance of threshold voltage $\left({\mathrm{V}}_{\mathrm{t}\mathrm{h}}\right)$ and gate leakage current $\left({\mathrm{I}}_{\mathrm{g}\mathrm{s}\mathrm{s}}\right)$ in SiC MOSFETs is evaluated under positive and negative gate voltage stress. The oxide lifetimes of SiC planar and trench MOSFETs at 150 °C are measured using constant voltage Time-Dependent Dielectric Breakdown (TDDB) testing. From the test results, it is found that electron trapping and hole trapping in ${\mathrm{S}\mathrm{i}\mathrm{O}}_2$ caused by oxide electric field $\left({\mathrm{E}}_{\mathrm{o}\mathrm{x}}\right)$ stress affect the ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ of SiC MOSFETs. The saturation and turnaround behavior of the ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ shift during positive and negative gate voltage stresses indicates that the influence of charge trapping in the gate oxide varies with stress time. The ${\mathrm{I}}_{\mathrm{g}\mathrm{s}\mathrm{s}}$ under positive and negative gate voltages depends on the tunneling barrier height for electrons and holes, respectively, which can be calculated using the Fowler–Nordheim (FN) tunneling mechanism. Moreover, the presence of near-interface traps (NITs) affects the barrier height for holes under negative gate voltages. The behavior of ${\mathrm{V}}_{\mathrm{t}\mathrm{h}}$ shift and ${\mathrm{I}}_{\mathrm{g}\mathrm{s}\mathrm{s}}$ under high-temperature gate bias reflects the charge trapping occurring in different regions of the gate oxide. In addition, compared to SiC planar MOSFETs, SiC trench MOSFETs with thicker gate oxide tend to exhibit higher lifetimes in TDDB tests. Full article

In this study, we propose a simple measurement technique to quantitatively measure the time taken by threshold voltage of normally-off p-GaN AlGaN/GaN HEMTs to recover from a nominal operational gate stress-induced instability. The proposed technique eliminates the requirement to perform a full transfer characteristic sweep post-stress, thereby eliminating the measurement-induced instability effect, often colluding precise recovery time measurement. The rate of recovery and extracted recovery times hold significance in empirically correlating the location of traps in the p-GaN or AlGaN barrier region causing V_TH instability. The gate of the HEMT is stressed at nominal operational drive voltages 1.5 V, 2 V, and 4 V for various time intervals from 500 μs to 100 s, and the time taken for the drain current to recover to prestress levels measured at near-threshold voltage (~1.1 V_TH) is measured as the threshold voltage recovery time. With increasing gate stress voltages, 2DEG gets trapped at relatively deeper trap energy levels at the AlGaN/GaN interface requiring more emission time during the process of recovery, mandating larger recovery times. At higher stress voltage of 4 V, the Schottky gate leakage current is high enough enabling injected holes to cross the AlGaN barrier and counter-compensate for the deeply trapped 2DEG, requiring relatively the same recovery times as lower stress voltages where the gate leakage is negligibly small. With increasing stress time, the amount of 2DEG trapped increases, requiring more recovery time to de-trap and beyond a certain time, saturation of the trap density occurs causing the recovery time to plateau. Full article

The utilization of electroporation for delivering CRISPR/Cas9 system components has enabled efficient gene editing in mammalian zygotes, facilitating the development of genome-edited animals. In this study, our research focused on targeting the ACTG1 and MSTN genes in sheep, revealing a threshold phenomenon in electroporation with a voltage tolerance in sheep in vitro fertilization (IVF) zygotes. Various poring voltages near 40 V and pulse durations were examined for electroporating sheep zygotes. The study concluded that stronger electric fields required shorter pulse durations to achieve the optimal conditions for high gene mutation rates and reasonable blastocyst development. This investigation also assessed the quality of Cas9/sgRNA ribonucleoprotein complexes (Cas9 RNPs) and their influence on genome editing efficiency in sheep early embryos. It was highlighted that pre-complexation of Cas9 proteins with single-guide RNA (sgRNA) before electroporation was essential for achieving a high mutation rate. The use of suitable electroporation parameters for sheep IVF zygotes led to significantly high mutation rates and heterozygote ratios. By delivering Cas9 RNPs and single-stranded oligodeoxynucleotides (ssODNs) to zygotes through electroporation, targeting the MSTN (Myostatin) gene, a knock-in efficiency of 26% was achieved. The successful generation of MSTN-modified lambs was demonstrated by delivering Cas9 RNPs into IVF zygotes via electroporation. Full article

The impact of radiation on MoS₂-based devices is an important factor in the utilization of two-dimensional semiconductor-based technology in radiation-sensitive environments. In this study, the effects of gamma irradiation on the electrical variations in MoS₂ field-effect transistors with buried local back-gate structures were investigated, and their related effects on Al₂O₃ gate dielectrics and MoS₂/Al₂O₃ interfaces were also analyzed. The transfer and output characteristics were analyzed before and after irradiation. The current levels decreased by 15.7% under an exposure of 3 kGy. Additionally, positive shifts in the threshold voltages of 0.50, 0.99, and 1.15 V were observed under irradiations of 1, 2, and 3 kGy, respectively, compared to the non-irradiated devices. This behavior is attributable to the comprehensive effects of hole accumulation in the Al₂O₃ dielectric interface near the MoS₂ side and the formation of electron trapping sites at the interface, which increased the electron tunneling at the MoS₂ channel/dielectric interface. Full article

Due to their remarkable intrinsic physical properties, carbon nanotubes (CNTs) can enhance mechanical properties and confer electrical and thermal conductivity to polymers currently being investigated for use in advanced applications based on thermal management. An epoxy resin filled with varying concentrations of CNTs (up to 3 wt%) was produced and experimentally characterized. The electrical percolation curve identified the following two critical filler concentrations: 0.5 wt%, which is near the electrical percolation threshold (EPT) and suitable for exploring mechanical and piezoresistive properties, and 3 wt% for investigating thermo-electric properties due to the Joule effect with applied voltages ranging from 70 V to 200 V. Near the electrical percolation threshold (EPT), the CNT concentration in epoxy composites forms a sparse, sensitive network ideal for deformation sensing due to significant changes in electrical resistance under strain. Above the EPT, a denser CNT network enhances electrical and thermal conductivity, making it suitable for Joule heating applications. Numerical models were developed using multiphysics simulation software. Once the models have been validated with experimental data, as a perfect agreement is found between numerical and experimental results, a simulation study is performed to investigate additional physical properties of the composites. Furthermore, a statistical approach based on the design of experiments (DoE) was employed to examine the influence of certain thermal parameters on the final performance of the materials. The purpose of this research is to promote the use of contemporary statistical and computational techniques alongside experimental methods to enhance understanding of materials science. New materials can be identified through these integrated approaches, or existing ones can be more thoroughly examined. Full article

In this paper, simulation modeling was carried out using Sentaurus Technology Computer-Aided Design. Two types of high electron mobility transistors (HEMT), an AlGaN/GaN/AlGaN double heterojunction and AlGaN/GaN single heterojunction, were designed and compared. The breakdown characteristics and damage mechanisms of the two devices under the injection of high-power microwaves (HPM) were studied. The variation in current density and peak temperature inside the device was analyzed. The effect of Al components at different layers of the device on the breakdown of HEMTs is discussed. The effect and law of the power damage threshold versus pulse width when the device was subjected to HPM signals was verified. It was shown that the GaN HEMT was prone to thermal breakdown below the gate, near the carrier channels. A moderate increase in the Al component can effectively increased the breakdown voltage of the device. Compared with the single heterojunction, the double heterojunction HEMT devices were more sensitive to Al components. The high domain-limiting characteristics effectively inhibited the overflow of channel electrons into the buffer layer, which in turn regulated the current density inside the device and improved the temperature distribution. The leakage current was reduced and the device switching characteristics and breakdown voltage were improved. Moreover, the double heterojunction device had little effect on HPM power damage and high damage resistance. Therefore, a theoretical foundation is proposed in this paper, indicating that double heterojunction devices are more stable compared to single heterojunction devices and are more suitable for applications in aviation equipment operating in high-frequency and high-voltage environments. In addition, double heterojunction GaN devices have higher radiation resistance than SiC devices of the same generation. Full article

The exponential emergence of Field-Programmable Gate Arrays (FPGAs) has accelerated research on hardware implementation of Deep Neural Networks (DNNs). Among all DNN processors, domain-specific architectures such as Google’s Tensor Processor Unit (TPU) have outperformed conventional GPUs (Graphics Processing Units) and CPUs (Central Processing Units). However, implementing low-power TPUs in reconfigurable hardware remains a challenge in this field. Voltage scaling, a popular approach for energy savings, can be challenging in FPGAs, as it may lead to timing failures if not implemented appropriately. This work presents an ultra-low-power FPGA implementation of a TPU for edge applications. We divide the systolic array of a TPU into different FPGA partitions based on the minimum slack value of different design paths of Multiplier Accumulators (MACs). Each partition uses different near-threshold (NTC) biasing voltages to run its FPGA cores. The biasing voltage for each partition is roughly calculated by the proposed static schemes. However, further calibration of biasing voltage is performed by the proposed runtime scheme. To overcome the timing failure caused by NTC, the MACs with higher minimum slack are placed in lower-voltage partitions, while the MACs with lower minimum slack paths are placed in higher-voltage partitions. The proposed architecture is implemented in a commercial platform, namely $Vivado$ with Xilinx $Artix\text{-}7$ FPGA and academic platform $VTR$ with 22 nm, 45 nm and 130 nm FPGAs. Any timing error caused by NTC can be caught by the Razor flipflop used in each MAC. The proposed voltage-scaled, partitioned systolic array can save 3.1% to 11.6% of dynamic power in $Vivado$ and $VTR$ tools, respectively, depending on the FPGA technology, partition size, number of partitions and biasing voltages. The normalized performance and accuracy of benchmark models running on our low-power TPU are very competitive compared to existing literature. Full article