Search Results (82)

This study focuses on the evaluation of electrical stress limit capability for 3D-packaged memory (256 M × 72-bit DDR3 SDRAM) (Shanghai Fudan Microelectronics Group Co., Ltd., Shanghai, China). Guided by Reliability Enhancement Theory, this study presents a meticulously designed comprehensive test profile that incorporates critical stress parameters, including supply voltage, input clock frequency, electrostatic discharge (ESD) sensitivity, and electrical endurance. Explicit criteria for stress selection, upper/lower bounds, step increments, and duration are established. A dedicated test platform is constructed, integrating automated test equipment (ATE) and ESD sensitivity analyzers with detailed specifications on device selection criteria and operational principles. The functional performance testing methodology is systematically investigated, covering test platform configuration, initialization protocols, parametric testing procedures, functional verification, and acceptance criteria. Extreme-condition experiments—including supply voltage margining, input clock frequency tolerance, ESD sensitivity characterization, and accelerated electrical endurance testing—are conducted to quantify operational and destructive limits. The findings provide critical theoretical insights and practical guidelines for the design optimization, quality control, and reliability enhancement of 3D-packaged memory devices. Full article

Stealthy chip-level tamper attacks, such as hardware Trojan insertions or security-critical circuit modifications, can threaten modern microelectronic systems’ security. While traditional inspection and side-channel methods offer potential for tamper detection, they may not reliably detect all forms of attacks and often face practical limitations in terms of scalability, accuracy, or applicability. This work introduces a non-invasive, contactless tamper detection method employing a complementary split-ring resonator (CSRR). CSRRs, which are typically deployed for non-destructive material characterization, can be placed on the surface of the chip’s package to detect subtle variations in the impedance of the chip’s power delivery network (PDN) caused by tampering. The changes in the PDN’s impedance profile perturb the local electric near field and consequently affect the sensor’s impedance. These changes manifest as measurable variations in the sensor’s scattering parameters. By monitoring these variations, our approach enables robust and cost-effective physical integrity verification requiring neither physical contact with the chips or printed circuit board (PCB) nor activation of the underlying malicious circuits. To validate our claims, we demonstrate the detection of various chip-level tamper events on an FPGA manufactured with 28 nm technology. Full article

Advancements in semiconductor packaging toward higher integration and interconnect density have increased the risk of structural defects—such as missing solder balls, pad delamination, and bridging—that can disrupt thermal conduction paths, leading to localized overheating and potential chip failure. To address the limitations of traditional non-destructive testing methods in detecting micron-scale defects, this study introduces a multimodal detection approach combining finite-element thermal simulation, infrared thermography, and the YOLO11 deep learning network. A comprehensive 3D finite-element model of a ball grid array (BGA) package was developed to analyze the impact of typical defects on both steady-state and transient thermal distributions, providing a solid physical foundation for modeling defect-induced thermal characteristics. An infrared thermal imaging platform was established to capture real thermal images, which were then compared with simulation results to verify physical consistency. An integrated dataset of simulated and infrared images was constructed to enhance the robustness of the detection model. Leveraging the YOLO11 network’s capabilities in end-to-end training, dataset small-object detection, and rapid inference, the system achieved accurate and rapid localization of defect regions. Experimental results show a mean average precision (mAP) of 99.5% at an intersection over union (IoU) threshold of 0.5 and an inference speed of 556 frames per second on the simulation dataset. Training with the hybrid dataset improved detection accuracy on real images from 41.7% to 91.7%, significantly outperforming models trained on a single data source. Furthermore, the maximum temperature discrepancy between simulation and experimental measurements was less than 5%, validating the reliability of the proposed method. This research offers a high-precision, real-time solution for semiconductor packaging defect detection, with substantial potential for industrial application. Full article

This study systematically explores the structural stability, mechanical properties, elastic anisotropy, fracture toughness, and thermophysical characteristics of Au₃In and Au₃In₂ intermetallic compounds (IMCs) through density functional theory (DFT) simulations. Employing the generalized gradient approximation (GGA) and the Voigt–Reuss–Hill approximation enables precise predictions of polycrystalline elastic behavior, providing critical insights into the intrinsic stability and mechanical anisotropy of these IMCs. Structural optimization identifies the equilibrium lattice parameters and cohesive energies, indicating stronger atomic bonding and superior structural stability in Au₃In relative to Au₃In₂. Elastic constant calculations confirm mechanical stability and reveal pronounced anisotropic elastic behavior; Au₃In exhibits significant stiffness along the [010] crystallographic direction, while Au₃In₂ demonstrates notable stiffness predominantly along the [001] direction. Both Au₃In and Au₃In₂ exhibit ductile characteristics, confirmed by positive Cauchy pressures and elevated bulk-to-shear modulus (K/G) ratios. Fracture toughness analysis further establishes that Au₃In offers greater resistance to crack propagation compared to Au₃In₂, suggesting its suitability in mechanically demanding applications. Thermophysical property evaluations demonstrate that Au₃In possesses higher thermal conductivity, elevated Debye temperature, and superior volumetric heat capacity relative to Au₃In₂, reflecting its enhanced capability for effective thermal management in electronic packaging. Anisotropy assessments, utilizing both universal and Zener anisotropy indices, reveal significantly higher mechanical anisotropy in Au₃In₂, influencing its practical applicability. Full article

This study employed density functional theory (DFT) to investigate the structural, mechanical, thermodynamic, and electronic properties of monoclinic CuP₂ and hexagonal Cu₃P. The analysis confirmed the mechanical stability of both compounds, with distinct anisotropic behaviors arising from crystallographic symmetries. Cu₃P exhibits a higher bulk modulus (130.1 GPa), indicating superior resistance to volumetric compression, while CuP₂ demonstrates greater shear (52.9 GPa) and Young’s moduli (133.3 GPa), reflecting enhanced stiffness and tensile resistance. The K/G ratio (1.749 for CuP₂ vs. 3.120 for Cu₃P) and Cauchy pressure analyses revealed the brittle nature of CuP_2, with covalent bonding, and the ductility of Cu₃P, with metallic bonding. The thermodynamic evaluations highlighted the higher Debye temperature of CuP₂ (453.1 K) and its lattice thermal conductivity (8.37 W/mK), suggesting superior heat dissipation, whereas Cu₃P shows greater thermal expansion (38.4 × 10⁻⁶/K) and a higher volumetric heat capacity (3.29 × 10⁶ J/m³K). The electronic structure calculations identified CuP₂ as a semiconductor with a 0.824 eV bandgap and Cu₃P as a conductor with metallic states at the Fermi level. These insights are critical for optimizing Cu-P compounds in microelectronic packaging, where thermal management and mechanical reliability are paramount. Full article

The continuous miniaturization of electronics, high processing capacity, compact microelectronic devices, and high circuit density contribute to an increasing demand for the efficient cooling of electronics. For aerospace and space applications, where packaging and the optimal use of space, weight, and power are important, adequate and efficient cooling is a limiting factor due to the increased heat flux rates from compact-design electronic units. As a technology enabler, thermal management applications become important with the increasing demand for longer component operation times. This study aims to review the literature and the analysis results of thermal engineering applications on cooling of electronics and thermal management approaches in space and aerospace applications. Many advanced cooling applications with interdisciplinary advancements and their benefits are discussed. Full article

As semiconductor packaging technologies face limitations, through-silicon via (TSV) technology has emerged as a key solution to extending Moore’s law by achieving high-density, high-performance microelectronics. TSV technology enables enhanced wiring density, signal speed, and power efficiency, and offers significant advantages over traditional wire-bonding techniques. However, achieving fine-pitch and high-density interconnects remains a challenge. Solder flip-chip microbumps have demonstrated their potential to improve interconnect reliability and performance. However, the environmental impact of lead-based solders necessitates a shift to lead-free alternatives. This review highlights the transition from Sn-Pb solders to lead-free options, such as Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Zn, and Bi- or In-based alloys, driven by regulatory and environmental considerations. Although lead-free solders address environmental concerns, their higher melting points pose challenges such as thermal stress and chip warping, which affect device reliability. To overcome these challenges, the development of low-melting-point solder alloys has gained momentum. This study examines advancements in low-temperature solder technologies and evaluates their potential for enhancing device reliability by mitigating thermal stress and ensuring long-term stability. Full article

As the trend towards the densification of integrated circuit (IC) devices continues, the complexity of interfaces involving dissimilar materials and thermo-mechanical interactions has increased. Highly integrated systems in packages now comprise numerous thin layers made from various materials. The interfaces between these different materials represent a vulnerable point in ICs due to imperfect adhesion and stress concentrations caused by mismatches in thermo-mechanical properties such as Young’s modulus, coefficients of thermal expansion (CTE), and hygro-swelling-induced expansion. This study investigates the impact of thermal variations on the fracture behavior of three bi-material interfaces used in semiconductor packaging: epoxy molding compound–silicon (EMC–Si), silicon oxide–polyimide (SiO₂–PI), and PI–EMC. Using double cantilever beam (DCB) tests, we analyzed these interfaces under mode I loading at three temperatures: −20 °C, 23 °C, and 100 °C, under both quasi-static and cyclic loading conditions. This provided a comprehensive analysis of the thermal effects across all temperature ranges in microelectronics. The results show that temperature significantly alters the failure mechanism. For SiO₂–PI, the weakest point shifts from silicon at low temperatures to the interface at higher temperatures due to thermal stress redistribution. Additionally, the fracture energy of the EMC–Si interface was found to be highly temperature-dependent, with values ranging from 0.136 N/mm at low temperatures to 0.38 N/mm at high temperatures. SiO₂–PI’s fracture energy at high temperature was 42% less than that of EMC–Si. The PI–EMC interface exhibited nearly double the crack growth rate compared to EMC–Si. The findings of this study provide valuable insights into the fracture behavior of bi-material interfaces, offering practical applications for improving the reliability and design of semiconductor devices, especially in chip packaging. Full article

In advanced microelectronic packaging, high thermo-mechanical loads arise on the solder interconnects. Accurate and efficient modeling of the mechanical behavior is crucial in the design of the package, and the simulation results can provide a basis for estimations of the reliability of the assembly. However, the accuracy of the simulation results depends on the accuracy of the modeled geometry and the modeling simplifications and assumptions employed to achieve computational cost-efficient calculations. In this work, finite element analysis (FEA) of a Fan Out—Wafer Level Packaging (FO-WLP) layout was carried out considering the following variations: modeling domain (2-D and pseudo-3-D) was defined for creating the efficient calculation framework, where soldering material (SAC 305 and SACQ), incorporation of intermetallic compound (IMC), bond pad edge geometry (sharp and blunt) were modeled for cycles of thermal load. Stress and strain analysis was carried out to evaluate the solder behavior for the parameter variations. Furthermore, fatigue indicators were evaluated. An efficient planar simulation framework with 2-D and pseudo-3-D meshed geometries provides a quick estimate for the lower and upper bound for the strain, stress and strain energy-related parameters, respectively. This calculation framework can be employed for extensive parameter studies solved rapidly at low computational costs. Full article

Ultrafast laser welding technology for transparent materials has developed rapidly in recent years; however, high-strength non-optical contact transparent material welding has been a challenge. This work presents a welding method for silica glass using a double-pulse femtosecond (fs) laser and optimizes the laser processing parameters to enhance the welding performance. The welding characteristics of silica glass are analyzed under different time delays by controlling the pulse delay of double pulses. In addition to comprehensively study the influence of various experimental conditions on double-pulse fs laser welding, multi-level tests are designed for five factors, including average laser power, pulse delay, scanning interval, scanning speed, and repetition rate. Finally, by optimizing the parameters, a welding strength of 57.15 MPa is achieved at an average power of 3500 mW, repetition rate of 615 kHz, pulse delay of 66.7 ps, scanning interval of 10 µm, and scanning speed of 1000 µm/s. This work introduces a new approach to glass welding and presents optimal parameters for achieving higher welding strength, which can be widely used in aerospace, microelectronic packaging, microfluidics, and other fields. Full article

Metal micro-droplet ejection technology has attracted attention for its potential applications in the rapid prototyping of micro-metal parts and microelectronic packaging. The current micro-droplet ejection device developed based on this technology faces challenges such as the requirement of a micro-oxygen ejection environment, a complex feeding structure, and high costs. Therefore, a drop-on-demand droplet generator for metallic pellets with impact feed ejection is designed in this paper. This device has a simple and compact structure, does not require a high-cost heat source, and can perform drop-on-demand ejection of metallic pellets in an atmospheric environment. A micro-channel feeding method based on piezoelectric ceramic actuator drives is proposed. A rigid dynamics metallic pellet flight trajectory model is established to analyze the relationships between the driving voltage and the flight trajectory of the pellets. With the help of Fluent to simulate and analyze the melting and ejection processes of the pellets inside the nozzle, the changes in the variable parameters of the flow field in the process of the melting and flight of a single molten drop are studied. The droplet generator produces stable droplets with a 500 µs pulse width and 1100 mm/s initial velocity of the projectile. The simulation results show that a single projectile has to go through three stages including feeding, melting, and ejecting, which take 39.5 ms, 7.85 ms, and 17.65 ms. The total simulation time is 65.0 ms. It is expected that the injection frequency of the metal projectile droplet-generating device will reach 15 Hz. Full article

Aluminium nitride (AlN) materials are widely used in heat-dissipation substrates and electronic device packages. However, the application of aluminium nitride ceramics is hindered by the obvious anisotropy and high brittleness of its crystals, leading to poor material surface integrity and high grinding force. With the rapid development of microelectronics, the requirements for the material’s dimensional accuracy, machining efficiency, and surface accuracy are increasing. Therefore, a new machining process is proposed, combining laser and ultrasonic vibration with grinding. The laser–ultrasonic-assisted grinding (LUAG) of aluminium nitride is simulated by molecular dynamics (MD). Meanwhile, the effects of different processing techniques on grinding force, stress distribution, matrix damage mechanism, and subsurface damage depth are systematically investigated and verified by experiments. The results show that laser–ultrasonic-assisted grinding produces 50% lower grinding forces compared to traditional grinding (TG). The microhardness of AlN can reach more than 1200 HV, and the coefficient of friction and wear is reduced by 42.6%. The dislocation lines of the AlN substrate under this process are short but interlaced, making the material prone to phase transformation. Moreover, the subsurface damage depth is low, realising the substrate’s material hardening and wear resistance. These studies not only enhance the comprehension of material build-up and stress damage under the synergistic impact of laser, ultrasonic, and abrasive processing but also indicate that the proposed method can facilitate and realise high-performance machining of aluminium nitride substrate surfaces. Full article

Bi-doped Sn–Ag–Cu (SAC) microelectronic solder is gaining attention for its utility as a material for solder joints that connect substrates to printed circuit boards (PCB) in future advanced packages, as Bi-doped SAC is reported to have a lower melting temperature, higher strength, higher wettability on conducting pads, and lower intermetallic compound (IMC) formation at the solder-pad interface. As solder joints are subjected to aging during their service life, an investigation of aging-induced changes in the microstructure and mechanical properties of the solder alloy is needed before its wider acceptance in advanced packages. This study focuses on the effects of 1 to 3 wt.% Bi doping in an Sn–3.0Ag–0.5Cu (SAC305) solder alloy on aging-induced changes in hardness and creep resistance for samples prepared by high cooling rates (>5 °C/s). The specimens were aged at ambient and elevated temperatures for up to 90 days and subjected to quasistatic nanoindentation to determine hardness and nanoscale dynamic nanoindentation to determine creep behavior. The microstructural evolution was investigated with a scanning electron microscope in tandem with energy-dispersive spectroscopy to correlate with aging-induced property changes. The hardness and creep strength of the samples were found to increase as the Bi content increased. Moreover, the hardness and creep strength of the 0–1 wt.% Bi-doped SAC305 was significantly reduced with aging, while that of the 2–3 wt.% Bi-doped SAC305 increased with aging. The changes in these properties with aging were correlated to the interplay of multiple hardening and softening mechanisms. In particular, for 2–3 wt.% Bi, the enhanced performance was attributed to the potential formation of additional Ag₃Sn IMCs with aging due to non-equilibrium solidification and the more uniform distribution of Bi precipitates. The observations that 2–3 wt.% Bi enhances the hardness and creep strength of the SAC305 alloy with isothermal aging to mitigate reliability risks is relevant for solder samples prepared using high cooling rates. Full article

Sn-Ag-Cu-Bi (SAC-Bi) alloys are gaining popularity as a potential replacement for current lead-free solder alloys in microelectronic packages. In this study, the tensile and viscoplastic behaviors of eight SAC-Bi alloys with 0, 1 wt.%, 2 wt.%, and 3 wt.% Bi content were investigated. The samples of these eight alloys were cast, aged at room temperature, 75 °C and 125 °C, and tensile-tested at rates of 0.1/s, 0.01/s, and 0.001/s in ambient and elevated temperature environments to facilitate the quantification of viscoplasticity using the Anand viscoplastic model. The Anand parameters of all eight alloys in the as-cast and aged conditions were determined. Tensile strength was found to increase with the addition of Bi. Additionally, alloys containing 2 and 3 wt.% Bi showed a 5 to 10% increase in tensile strength after isothermal aging of 90 days at 125 °C. On the contrary, the tensile strength of alloys with up to 1 wt.% Bi decreased by 22 to 48% after such aging. Using a Scanning Electron Microscope (SEM) and energy dispersive spectroscopy (EDS), the microstructure of the alloys was characterized. The aging-induced property changes in the samples were correlated to strengthening by Bi solute atoms for alloys with 1 wt.% Bi and the formation of Bi precipitation for alloys with 2 wt.% and 3 wt.% Bi. Full article

Electrostatic discharge (ESD) failure is a major reliability problem for all forms of microelectronics products. ESD protection is required for all integrated circuits (ICs). As dimension scaling-down approaches its physical limit, heterogeneous integration (HI) emerges as a main pathway towards the age beyond Moore’s Law to facilitate advanced microsystem chips with extreme performance and rich functionalities. Advanced packaging is a key requirement for HI-enabled integrated systems-on-chiplets (SoIC) that require robust ESD protection solutions. This article outlines key emerging technical challenges associated with smart future SoIC microsystem superchips in the context of advanced packaging technologies. Full article