Search Results (62)

Biological systems learn from past experiences by establishing relationships between two simultaneously occurring events, a phenomenon known as associative learning. This concept has promising applications in modern AI (Artificial Intelligence) and ML (Machine Learning). To leverage it effectively, a precise electrical model that can simulate associative learning observed in biological systems is essential. The paper focuses on modeling Pavlov’s famous experiment related to the drooling of dogs at the sound of bell after associating the food with the bell during training. The study addresses limitations in existing circuit designs that fail to accurately replicate associative learning in dogs, particularly when the sequence of food and bell signals deviates from a specific pattern. We propose a novel design using a few CMOS (Complementary Metal Oxide Semiconductor) transistors and memristor models that produces an output corresponding to the dogs drooling only when food and bell signals are associated, mirroring real-life training conditions. The results section first discusses simulations using the standard TiO₂ (Titanium Oxide) memristor model, followed by experimental results obtained from a classical memristor emulator. Both simulation and experimental findings confirm the effectiveness of the circuit designs. Full article

Memristors are promising candidates for next-generation non-volatile memory devices, offering low power consumption and high-speed switching capabilities. However, conventional metal oxide-based memristors are constrained by fabrication complexity and high costs, limiting their commercial viability. Organic–inorganic hybrid perovskites (OIHPs), known for their facile solution processability and unique ionic–electronic conductivity, provide an attractive alternative. This study presents a conjugated polyelectrolyte (CPE), PhNa-1T, as an interlayer for OIHP memristors to enhance the high-resistance state (HRS) performance. A post-treatment process using n-octylammonium bromide (OABr) was further applied to optimize the interlayer properties. Devices treated with PhNa-1T/OABr achieved a significantly improved ON/OFF ratio of 2150, compared to 197 for untreated devices. Systematic characterization revealed that OABr treatment improved film morphology, reduced crystallite strain, and optimized energy level alignment, thereby reinforcing the Schottky barrier and minimizing current leakage. These findings highlight the potential of tailored interlayer engineering to improve OIHP-based memristor performance, offering promising prospects for applications in non-volatile memory technologies. Full article

Among the transition metal oxides, hematite (α-Fe₂O₃) has been widely used in the preparation of memristors because of its excellent physical and chemical properties. In this paper, α-Fe₂O₃ nanowire arrays with a preferred orientation along the [110] direction were prepared by a facile hydrothermal method and annealing treatment on the FTO substrate, and then α-Fe₂O₃ nanowire array-based Au/α-Fe₂O₃/FTO memristors were obtained by plating the Au electrodes on the as-prepared α-Fe₂O₃ nanowire arrays. The as-prepared α-Fe₂O₃ nanowire array-based Au/α-Fe₂O₃/FTO memristors have demonstrated stable nonvolatile bipolar resistive switching behaviors with a high resistive switching ratio of about two orders of magnitude, good resistance retention (up to 10³ s), and ultralow set voltage (V_set = +2.63 V) and reset voltage (V_reset = −2 V). In addition, the space charge-limited conduction (SCLC) mechanism has been proposed to be in the high resistance state, and the formation and destruction of the conductive channels modulated by oxygen vacancies have been suggested to be responsible for the nonvolatile resistive switching behaviors of the Au/α-Fe₂O₃/FTO memristors. Our results show the potential of the Au/α-Fe₂O₃/FTO memristors in nonvolatile memory applications. Full article

Oxygen vacancy engineering in metal oxides is a propitious route to modulate their resistive switching properties for memory and neuromorphic applications. This review provides an account of the research works on tailoring RS behavior in oxide thin-film-based memristor devices by oxygen vacancy engineering. We discuss the recent research progress on controlling oxygen vacancy concentration in metal oxide thin films and its impact on their resistive switching properties for application in electronic memory and neuromorphic computing devices. Full article

Tungsten disulfide (WS₂) is a promising material with excellent electrical, magnetic, optical, and mechanical properties. It is regarded as a key candidate for the development of optoelectronic devices due to its high carrier mobility, high absorption coefficient, large exciton binding energy, polarized light emission, high surface-to-volume ratio, and tunable band gap. These properties contribute to its excellent photoluminescence and high anisotropy. These characteristics render WS2 an advantageous material for applications in light-emitting devices, memristors, and numerous other devices. This article primarily reviews the most recent advancements in the field of optoelectronic devices based on two-dimensional (2D) nano-WS₂. A variety of advanced devices have been considered, including light-emitting diodes (LEDs), sensors, field-effect transistors (FETs), photodetectors, field emission devices, and non-volatile memory. This review provides a guide for improving the application of 2D WS₂ through improved methods, such as introducing defects and doping processes. Moreover, it is of great significance for the development of transition-metal oxides in optoelectronic applications. Full article

Directional ionic migration in ultra-thin metal-oxide semiconductors under applied electric fields is a key mechanism for developing various electronic nanodevices. However, understanding charge transfer dynamics is challenging due to rapid ionic migration and uncontrolled charge transfer, which can reduce the functionality of microelectronic devices. This research investigates the supercapacitive-coupled memristive characteristics of ultra-thin heterostructured metal-oxide semiconductor films at TiO₂-In₂O₃/Au Schottky junctions. Using atomic layer deposition (ALD), we nano-engineered In₂O₃/Au-based metal/semiconductor heterointerfaces. TEM studies followed by XPS elemental analysis revealed the chemical and structural characteristics of the heterointerfaces. Subsequent AFM studies of the hybrid heterointerfaces demonstrated supercapacitor-like behavior in nanometer-thick TiO₂-In₂O₃/Au junctions, resembling ultra-thin supercapacitors, pseudocapacitors, and nanobatteries. The highest specific capacitance of 2.6 × 10⁴ F.g⁻¹ was measured in the TiO₂-In₂O₃/Au junctions with an amorphous In₂O₃ electron gate. Additionally, we examined the impact of crystallization, finding that thermal annealing led to the formation of crystalline In₂O₃ films with higher oxygen vacancy content at TiO₂-In₂O₃ heterointerfaces. This crystallization process resulted in the evolution of non-zero I-V hysteresis loops into zero I-V hysteresis loops with supercapacitive-coupled memristive characteristics. This research provides a platform for understanding and designing adjustable ultra-thin Schottky junctions with versatile electronic properties. Full article

We explore security aspects of a new computing paradigm that combines novel memristors and traditional Complimentary Metal Oxide Semiconductor (CMOS) to construct a highly efficient analog and/or digital fabric that is especially well-suited to Machine Learning (ML) inference processors for Radio Frequency (RF) signals. Analog and/or hybrid hardware designed for such application areas follows different constraints from that of traditional CMOS. This paradigm shift allows for enhanced capabilities but also introduces novel attack surfaces. Memristors have different properties than traditional CMOS which can potentially be exploited by attackers. In addition, the mixed signal approximate computing model has different vulnerabilities than traditional digital implementations. However both the memristor and the ML computation can be leveraged to create security mechanisms and countermeasures ranging from lightweight cryptography, identifiers (e.g., Physically Unclonable Functions (PUFs), fingerprints, and watermarks), entropy sources, hardware obfuscation and leakage/attack detection methods. Three different threat models are proposed: (1) Supply Chain, (2) Physical Attacks, and (3) Remote Attacks. For each threat model, potential vulnerabilities and defenses are identified. This survey reviews a variety of recent work from the hardware and ML security literature and proposes open problems for both attack and defense. The survey emphasizes the growing area of RF signal analysis and identification in terms of commercial space, as well as military applications and threat models. We differ from other recent surveys that target ML, in general, neglecting RF applications. Full article

For processing streaming events from a Dynamic Vision Sensor camera, two types of neural networks can be considered. One are spiking neural networks, where simple spike-based computation is suitable for low-power consumption, but the discontinuity in spikes can make the training complicated in terms of hardware. The other one are digital Complementary Metal Oxide Semiconductor (CMOS)-based neural networks that can be trained directly using the normal backpropagation algorithm. However, the hardware and energy overhead can be significantly large, because all streaming events must be accumulated and converted into histogram data, which requires a large amount of memory such as SRAM. In this paper, to combine the spike-based operation with the normal backpropagation algorithm, memristor–CMOS hybrid circuits are proposed for implementing event-driven neural networks in hardware. The proposed hybrid circuits are composed of input neurons, synaptic crossbars, hidden/output neurons, and a neural network’s controller. Firstly, the input neurons perform preprocessing for the DVS camera’s events. The events are converted to histogram data using very simple memristor-based latches in the input neurons. After preprocessing the events, the converted histogram data are delivered to an ANN implemented using synaptic memristor crossbars. The memristor crossbars can perform low-power Multiply–Accumulate (MAC) calculations according to the memristor’s current–voltage relationship. The hidden and output neurons can convert the crossbar’s column currents to the output voltages according to the Rectified Linear Unit (ReLU) activation function. The neural network’s controller adjusts the MAC calculation frequency according to the workload of the event computation. Moreover, the controller can disable the MAC calculation clock automatically to minimize unnecessary power consumption. The proposed hybrid circuits have been verified by circuit simulation for several event-based datasets such as POKER-DVS and MNIST-DVS. The circuit simulation results indicate that the neural network’s performance proposed in this paper is degraded by as low as 0.5% while saving as much as 79% in power consumption for POKER-DVS. The recognition rate of the proposed scheme is lower by 0.75% compared to the conventional one, for the MNIST-DVS dataset. In spite of this little loss, the power consumption can be reduced by as much as 75% for the proposed scheme. Full article

Memristors are state-of-the-art, nano-sized, two-terminal, passive electronic elements with very good switching and memory characteristics. Owing to their very low power usage and a good compatibility to the existing CMOS ultra-high-density integrated circuits and chips, they are potentially applicable in artificial and spiking neural networks, memory arrays, and many other devices and circuits for artificial intelligence. In this paper, a complete electronic realization of an analog circuit model of the modified neural net with memristor-based synapses and transfer function with memristors and MOS transistors in LTSPICE is offered. Each synaptic weight is realized by only one memristor, providing enormously reduced circuit complexity. The summing and scaling implementation is founded on op-amps and memristors. The logarithmic-sigmoidal activation function is based on a simple scheme with MOS transistors and memristors. The functioning of the suggested memristor-based neural network for pulse input signals is evaluated both analytically in MATLAB-SIMULINK and in the LTSPICE environment. The obtained results are compared one to another and are successfully verified. The realized memristor-based neural network is an important step towards the forthcoming design of complex memristor-based neural networks for artificial intelligence, for implementation in very high-density integrated circuits and chips. Full article

A broad compositional range of Nb-Ti anodic memristors with volatile and self-rectifying behaviour was studied using a combinatorial screening approach. A Nb-Ti thin-film combinatorial library was co-deposited by sputtering, serving as the bottom electrode for the memristive devices. The library, with a compositional spread ranging between 22 and 64 at.% Ti was anodically oxidised, the mixed oxide being the active layer in MIM-type structures completed by Pt discreet top electrode patterning. By studying I–U sweeps, memristors with self-rectifying and volatile behaviour were identified. Moreover, all the analysed memristors demonstrated multilevel properties. The best-performing memristors showed HRS/LRS (high resistive state/low resistive state) ratios between 4 and 6 × 10⁵ and very good retention up to 10⁶ successive readings. The anodic memristors grown along the compositional spread showed very good endurance up to 10⁶ switching cycles, excluding those grown from alloys containing between 31 and 39 at.% Ti, which withstood only 10 switching cycles. Taking into consideration all the parameters studied, the Nb-46 at.% Ti composition was screened as the parent metal alloy composition, leading to the best-performing anodic memristor in this alloy system. The results obtained suggest that memristive behaviour is based on an interfacial non-filamentary type of resistive switching, which is consistent with the performed cross-sectional TEM structural and chemical characterisation. Full article

Low-power-consumption gas sensors are crucial for diverse applications, including environmental monitoring and portable Internet of Things (IoT) systems. However, the desorption and adsorption characteristics of conventional metal oxide-based gas sensors require supplementary equipment, such as heaters, which is not optimal for low-power IoT monitoring systems. Memristor-based sensors (gasistors) have been investigated as innovative gas sensors owing to their advantages, including high response, low power consumption, and room-temperature (RT) operation. Based on IGZO, the proposed isopropanol alcohol (IPA) gas sensor demonstrates a detection speed of 105 s and a high response of 55.15 for 50 ppm of IPA gas at RT. Moreover, rapid recovery to the initial state was achievable in 50 μs using pulsed voltage and without gas purging. Finally, a low-power circuit module was integrated for wireless signal transmission and processing to ensure IoT compatibility. The stability of sensing results from gasistors based on IGZO has been demonstrated, even when integrated into IoT systems. This enables energy-efficient gas analysis and real-time monitoring at ~0.34 mW, supporting recovery via pulse bias. This research offers practical insights into IoT gas detection, presenting a wireless sensing system for sensitive, low-powered sensors. Full article

As technologies like the Internet, artificial intelligence, and big data evolve at a rapid pace, computer architecture is transitioning from compute-intensive to memory-intensive. However, traditional von Neumann architectures encounter bottlenecks in addressing modern computational challenges. The emulation of the behaviors of a synapse at the device level by ionic/electronic devices has shown promising potential in future neural-inspired and compact artificial intelligence systems. To address these issues, this review thoroughly investigates the recent progress in metal-oxide heterostructures for neuromorphic applications. These heterostructures not only offer low power consumption and high stability but also possess optimized electrical characteristics via interface engineering. The paper first outlines various synthesis methods for metal oxides and then summarizes the neuromorphic devices using these materials and their heterostructures. More importantly, we review the emerging multifunctional applications, including neuromorphic vision, touch, and pain systems. Finally, we summarize the future prospects of neuromorphic devices with metal-oxide heterostructures and list the current challenges while offering potential solutions. This review provides insights into the design and construction of metal-oxide devices and their applications for neuromorphic systems. Full article

There is always a need for low-power, area-efficient VLSI (Very Large-Scale Integration) design and this need is increasing day by day. However, conventional design methods based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) technology cannot meet the performance requirements. The memristor, as a promising computing and memory integration device, offers a new research idea for conventional logic circuit structure and architecture innovation, given its non-volatility, scalability, low power consumption, fast switching speed, etc. This paper proposes a brief overview of the characteristics and current status of memristor-based logic circuits and analyzes their applications in numerical expression and memory. The benefits and drawbacks of various analog logic circuit structures are summarized and compared. In addition, some solution strategies for these issues are presented. Finally, this paper offers prospects for the applications of memristors in the logic implementation of large-scale memristor arrays, the novel structure of in-memory computing, and neural network computing. Full article

Spiking neural networks (SNNs) are considered a crucial research direction to address the “storage wall” and “power wall” challenges faced by traditional artificial intelligence computing. However, developing SNN chips based on CMOS (complementary metal oxide semiconductor) circuits remains a challenge. Although memristor process technology is the best alternative to synapses, it is still undergoing refinement. In this study, a novel approach is proposed that employs tools to automatically generate HDL (hardware description language) code for constructing neuron and memristor circuits after using Python to describe the neuron and memristor models. Based on this approach, HR (Hindmash–Rose), LIF (leaky integrate-and-fire), and IZ (Izhikevich) neuron circuits, as well as HP, EG (enhanced generalized), and TB (the behavioral threshold bipolar) memristor circuits are designed to construct the most basic connection of a SNN: the neuron–memristor–neuron circuit that satisfies the STDP (spike-timing-dependent-plasticity) learning rule. Through simulation experiments and FPGA (field programmable gate array) prototype verification, it is confirmed that the IZ and LIF circuits are suitable as neurons in SNNs, while the $X$ variables of the EG memristor model serve as characteristic synaptic weights. The EG memristor circuits best satisfy the STDP learning rule and are suitable as synapses in SNNs. In comparison to previous works on hardware spiking neurons, the proposed method needed fewer area resources for creating spiking neurons models on FPGA. The proposed SNN basic components design method, and the resulting circuits, are beneficial for architectural exploration and hardware–software co-design of SNN chips. Full article

In this work, we report the digital and analog resistive-switching (RS) characteristics in a memristor based on silicon nanocrystals (Si-NCs) integrated into a complementary metal-oxide-semiconductor (MOS) structure. Si-NCs with a diameter of 5.48 ± 1.24 nm embedded in a SiO₂/Si-NCs/SiO₂ multilayer structure acts as an RS layer. These devices exhibit bipolar RS with an intermediate resistance step during SET and RESET processes, which is believed to lie in the Si-NCs layer acting as charge-trapping nodes. The endurance studies of about 70 DC cycles indicate an ON/OFF ratio of ~10⁶ and a retention time larger than 10⁴ s. Long-term potentiation (LTP, −2 V) and long-term depression (LTD, +4 V) are obtained by applying consecutive identical pulse voltages of 150 ms duration. The current value gradually increases/decreases (LTP/LTD) as the pulse number increases. Three consecutive identical pulses of −2 V/150 ms (LTP) separated by 5 and 15 min show that the last current value obtained at the end of each pulse train is kept, confirming an analog RS behavior. These characteristics provide a possible way to mimic biological synapse functions for applications in neuromorphic computing in Si-NCs-based CMOS structures. Full article