Search Results (7)

Autonomous navigation is essential for small-body exploration, particularly for sophisticated missions such as sample-return operations. This study proposes a radio marker-based self-positioning system for small-body exploration using the asynchronous one-way ranging (AOWR) technique. In the proposed system, the spacecraft distributes a master time reference to radio markers deployed on the surface, enabling simultaneous ranging and clock synchronization among multiple entities. The system is designed to support both surface landing and cooperative rendezvous operations within a multi-spacecraft mission architecture. To demonstrate the feasibility of the proposed system for small-body exploration, a ground-based analogue experiment was conducted using a drone and four radio markers. The experimental results show that the system achieves positioning accuracy comparable to GPS-based measurements on the ground, indicating its applicability to small-body missions. Full article

Data acquisition based on network-on-chip (NoC) technology is a high-sampling-rate data acquisition scheme using low-sampling-rate analog–digital conversion (ADC) chips. It has the characteristics of multi-task parallel communication, being global asynchronous, local synchronous clock distribution, high throughput, low transmission latency, and strong scalability. High-speed data acquisition is realized through the combination of an on-chip network and time-interleaved data acquisition technology. In the time-interleaved sampling technique, the precision of clock synchronization directly affects the precision of sampling. Based on the proposed NOC data acquisition scheme, an improved White Rabbit clock synchronization protocol is applied to high-speed data acquisition to achieve high-precision synchronization of multi-channel time-interleaved sampling clocks. Firstly, the offset of the master clock and slave clock is determined by the PTP protocol, and the offset is corrected to achieve rough synchronization between the master clock and slave clock. Secondly, a digital dual-mixer time difference (DDMTD) is used to measure the phases of the master and slave clocks. After that, the phase of the slave clock is corrected through the dynamic phase-shift function of the clock’s phase-locked loop (PLL). Finally, according to the simulation results in Modelsim, the average absolute error of a TI-ADC sampling clock can be less than 20 ps. Full article

In the energy sector, distributed synchronism and a high degree of stability are necessary for all real-time monitoring and control systems. Instantaneous response to critical situations is essential for the integration of renewable energies. The most widely used standards for clock synchronisation, such as Network Time Protocol (NTP) and Precision Time Protocol (PTP), do not allow for achieving synchronised simultaneous sampling in distributed systems. In this work, a novel distributed synchronism system based on the Time-Sensitive Networking (TSN) standard has been validated for its integration in an architecture oriented towards the high-resolution digitisation of photovoltaic (PV) generation systems. This method guarantees a time stamping with an optimal resolution that allows for the analysis of the influence of fast-evolving atmospheric fluctuations in several plants located in the same geographical area. This paper proposes an enhanced micro-phasor measurement unit (µPMU) that acts as a phasor meter and TSN master controlling the monitoring system synchronism. With this technique, the synchronism would be extended to the remaining measurement systems that would be involved in the installation at distances greater than 100 m. Several analyses were carried out with an on-line topology of four acquisition systems capturing simultaneously. The influence of the Ethernet network and the transducers involved in the acquisition process were studied. Tests were performed with Ethernet cable lengths of 2, 10, 50, and 75 m. The results were validated with 24-bit Sigma-Delta converters and high-precision resistor networks specialised in high-voltage monitoring. It was observed that with an appropriate choice of sensors and TSN synchronism, phase errors of less than ±1 µs can be guaranteed by performing distributed captures up to 50 kS/s. Statistical analysis showed that uncertainties of less than ±100 ns were achieved with 16-bit Successive Approximation Register (SAR) converters at a moderate cost. Finally, the requirements of the IEEE C37.118.1-2011 standard for phasor measurement units (PMU) were also satisfied. This standard establishes an uncertainty of ±3.1 μs for 50 Hz systems. These results demonstrate the feasibility of implementing a simultaneous sampling system for distributed acquisition systems coordinated by a µPMU. Full article

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step. Full article

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step. Full article

Circadian and sleep disorders, short sleep duration, and evening chronotype are often present in attention-deficit/hyperactivity disorder (ADHD). CLOCK, considered the master gene in the circadian rhythm, has been explored by few studies. Understanding the relationship between ADHD and CLOCK may provide additional information to understand the correlation between ADHD and sleep problems. In this study, we aimed to explore the association between ADHD and CLOCK, using several genetic markers to comprehensively cover the gene extension. A total of 259 ADHD children and their parents from a Brazilian clinical sample were genotyped for eight single nucleotide polymorphisms (SNPs) in the CLOCK locus. We tested the individual markers and the haplotype effects using binary logistic regression. Binary logistic and linear regressions considering ADHD symptoms among ADHD cases were conducted as secondary analysis. As main result, the analysis showed a risk effect of the G-A-T-G-G-C-G-A (rs534654, rs1801260, rs6855837, rs34897046, rs11931061, rs3817444, rs4864548, rs726967) haplotype on ADHD. A suggestive association between ADHD and rs534654 was observed. The results suggest that the genetic susceptibility to circadian rhythm attributed to the CLOCK gene may play an important role on ADHD. Full article

Accurate and precise clock synchronization is one of the fundamental requirements for various applications, such as telecommunication systems, measurement and control systems, and smart grid systems. Precision time protocol (PTP) was designed and specified in IEEE 1588 to meet that requirement. PTP provides a mechanism for synchronizing the clocks in a PTP system to a high degree of accuracy and precision based on exchange synchronization messages through a master–slave hierarchy. The best master clock (BMC) algorithm is currently used to establish the master–slave hierarchy for PTP. However, the BMC algorithm does not provide a fast recovery mechanism in case of master failures. The accuracy and precision of the PTP clocks could be deteriorated by the occurrence of failure in the network (link or node failure). These fault occurrences will affect network performance and reliability, and cause clock time drifting of the PTP nodes. In this paper, we present a novel approach, called timing fault recovery (TFR), to significantly reduce clock time drifting in PTP systems. TFR detects the fault occurrence in the network and recovers it by using a handshake mechanism with a short duration. Therefore, the TFR approach provides clock stability and constancy and increases the reliability and the availability of PTP systems. The performance of TFR has been analyzed and compared to that of the standard PTP. Various simulations were conducted to validate the performance analysis. The results show that, for our sample network, the TFR approach reduces clock drifting by 90% in comparison to the standard PTP, thus providing better clock firmness and synchronization accuracy for PTP clocks. Full article