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25 pages, 3946 KB

Open AccessReview

Advancements in Active-Pixel-Type CMOS Image Sensor Design Techniques and Architectures for Wide Dynamic Range

by Sangwoong Sim and Jaehoon Jun

Sensors 2026, 26(2), 489; https://doi.org/10.3390/s26020489 - 12 Jan 2026

Viewed by 1189

Advances in CMOS image sensors (CISs) have led to utilization in various industrial fields, including machine vision, medical, surveillance, the automotive industry, and the Internet of Things (IoT). One critical metric for CISs is the dynamic range (DR), which indicates the range of [...] Read more.

Advances in CMOS image sensors (CISs) have led to utilization in various industrial fields, including machine vision, medical, surveillance, the automotive industry, and the Internet of Things (IoT). One critical metric for CISs is the dynamic range (DR), which indicates the range of light intensity that can clearly capture images. As the technology evolves, wide dynamic range (WDR) becomes increasingly required for more diverse applications. To further advance these industries, this paper presents the active-pixel-type CIS design techniques and architectures developed to achieve WDR. These include the following: the basic concepts of the active pixel sensor, readout mechanism, and DR of the CIS; multiple exposure and dual conversion gain (DCG) schemes that are conventionally used to address a trade-off in the CIS; lateral overflow integration capacitor (LOFIC) and dual photodiode (PD) architectures that can improve the DR by utilizing trade-offs in the DR and exposure mechanism; CISs with logarithmic and linear–logarithmic (Lin-Log) responses to enable non-linear characteristics; and techniques that can be employed for higher sensitivity in dark conditions. This comprehensive study of various techniques and architectures can also be utilized for cutting-edge tech advances and future research, including neuromorphic array architecture. Full article

(This article belongs to the Special Issue Sensor Techniques for Signal, Image and Video Processing)

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16 pages, 3699 KB

Open AccessArticle

Development of Circuits for Antilogarithmic Converters with Efficient Error–Area–Delay Product Using the Fractional-Bit Compensation Scheme for Digital Signal Processing Applications

by Chao-Tsung Kuo

Appl. Sci. 2024, 14(4), 1487; https://doi.org/10.3390/app14041487 - 12 Feb 2024

Cited by 1 | Viewed by 1650

Abstract

Digital signal processing (DSP) has been widely adopted in sensor systems, communication systems, digital image processing, artificial intelligence, and Internet of Things applications. However, these applications require circuits for complex arithmetic computation. The logarithmic number system is a method to reduce the implementation [...] Read more.

Digital signal processing (DSP) has been widely adopted in sensor systems, communication systems, digital image processing, artificial intelligence, and Internet of Things applications. However, these applications require circuits for complex arithmetic computation. The logarithmic number system is a method to reduce the implementation area and transmission delay for arithmetic computation in DSP. In this study, we propose antilogarithmic converters with efficient error–area–delay products (eADPs) based on the fractional-bit compensation scheme. We propose three mathematical approximations—case 1, case 2, and case 3—to approximate the accurate antilogarithmic curve with different DSP requirements. The maximum percentage errors of conversion for case 1, case 2, and case 3 are 1.9089%, 1.7330%, and 1.2063%, respectively. Case 1, case 2, and case 3 can achieve eADP savings of 15.66%, 80.80%, and 84.61% compared with other methods reported in the literature. The proposed eADP-efficient antilogarithmic converters can achieve lower eADP and digitalized circuit implementation. The hardware implementation utilizes Verilog Hardware Description Language and the digital circuits are created via very-large-scale integration by the Taiwan Semiconductor Manufacturing Company with 0.18 µm CMOS technology. This proposed antilogarithmic converter can be efficiently applied in DSP. Full article

(This article belongs to the Topic Innovation of Applied System)

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10 pages, 15786 KB

Open AccessFeature PaperArticle

A Low Dark Current 160 dB Logarithmic Pixel with Low Voltage Photodiode Biasing

by Alessandro Michel Brunetti and Bhaskar Choubey

Electronics 2021, 10(9), 1096; https://doi.org/10.3390/electronics10091096 - 7 May 2021

Cited by 6 | Viewed by 5039

Abstract

Extending CMOS Image Sensors’ dynamic range is of fundamental importance in applications, such as automotive, scientific, or X-ray, where a broad variation of incoming light should be measured. The typical logarithmic pixels suffer from poor performance under low light conditions due to a [...] Read more.

Extending CMOS Image Sensors’ dynamic range is of fundamental importance in applications, such as automotive, scientific, or X-ray, where a broad variation of incoming light should be measured. The typical logarithmic pixels suffer from poor performance under low light conditions due to a leakage current, usually referred to as the dark current. In this paper, we propose a logarithmic pixel design capable of reducing the dark current through low-voltage photodiode biasing, without introducing any process modifications. The proposed pixel combines a high dynamic range with a significant improvement in the dark response compared to a standard logarithmic pixel. The reported experimental results show this architecture to achieve an almost 35 dB improvement at the expense of three additional transistors, thereby achieving an unprecedented dynamic range higher than 160 dB. Full article

(This article belongs to the Special Issue Design of Ultra-Low Voltage/Power Circuits and Systems)

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16 pages, 4781 KB

Open AccessArticle

A Graphene/Polycrystalline Silicon Photodiode and Its Integration in a Photodiode–Oxide–Semiconductor Field Effect Transistor

by Yu-Yang Tsai, Chun-Yu Kuo, Bo-Chang Li, Po-Wen Chiu and Klaus Y. J. Hsu

Micromachines 2020, 11(6), 596; https://doi.org/10.3390/mi11060596 - 17 Jun 2020

Cited by 4 | Viewed by 5111

Abstract

In recent years, the characteristics of the graphene/crystalline silicon junction have been frequently discussed in the literature, but study of the graphene/polycrystalline silicon junction and its potential applications is hardly found. The present work reports the observation of the electrical and optoelectronic characteristics [...] Read more.

In recent years, the characteristics of the graphene/crystalline silicon junction have been frequently discussed in the literature, but study of the graphene/polycrystalline silicon junction and its potential applications is hardly found. The present work reports the observation of the electrical and optoelectronic characteristics of a graphene/polycrystalline silicon junction and explores one possible usage of the junction. The current–voltage curve of the junction was measured to show the typical exponential behavior that can be seen in a forward biased diode, and the photovoltage of the junction showed a logarithmic dependence on light intensity. A new phototransistor named the “photodiode–oxide–semiconductor field effect transistor (PDOSFET)” was further proposed and verified in this work. In the PDOSFET, a graphene/polycrystalline silicon photodiode was directly merged on top of the gate oxide of a conventional metal–oxide–semiconductor field effect transistor (MOSFET). The magnitude of the channel current of this phototransistor showed a logarithmic dependence on the illumination level. It is shown in this work that the PDOSFET facilitates a better pixel design in a complementary metal–oxide–semiconductor (CMOS) image sensor, especially beneficial for high dynamic range (HDR) image detection. Full article

(This article belongs to the Special Issue Miniaturized Silicon Photodetectors: New Perspectives and Applications)

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10 pages, 5972 KB

Open AccessArticle

The Design of a Single-Bit CMOS Image Sensor for Iris Recognition Applications

by Keunyeol Park, Minkyu Song and Soo Youn Kim

Sensors 2018, 18(2), 669; https://doi.org/10.3390/s18020669 - 24 Feb 2018

Cited by 13 | Viewed by 6681

Abstract

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts [...] Read more.

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts the iris data, and then compares it with a reference image through a recognition algorithm. However, in this case, the frame rate decreases by the time required for digital signal conversion of multi-bit digital data through the analog-to-digital converter (ADC) in the CIS. In order to reduce the overall processing time as well as the power consumption, we propose a data processing technique with an exclusive OR (XOR) logic gate to obtain single-bit and edge detection image data instead of multi-bit image data through the ADC. In addition, we propose a logarithmic counter to efficiently measure single-bit image data that can be applied to the iris recognition algorithm. The effective area of the proposed single-bit image sensor (174 × 144 pixel) is 2.84 mm² with a 0.18 μm 1-poly 4-metal CMOS image sensor process. The power consumption of the proposed single-bit CIS is 2.8 mW with a 3.3 V of supply voltage and 520 frame/s of the maximum frame rates. The error rate of the ADC is 0.24 least significant bit (LSB) on an 8-bit ADC basis at a 50 MHz sampling frequency. Full article

(This article belongs to the Special Issue Image Sensors)

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12 pages, 2664 KB

Open AccessArticle

QLog Solar-Cell Mode Photodiode Logarithmic CMOS Pixel Using Charge Compression and Readout

by Yang Ni

Sensors 2018, 18(2), 584; https://doi.org/10.3390/s18020584 - 14 Feb 2018

Cited by 6 | Viewed by 6798

Abstract

In this paper, we present a new logarithmic pixel design currently under development at New Imaging Technologies SA (NIT). This new logarithmic pixel design uses charge domain logarithmic signal compression and charge-transfer-based signal readout. This structure gives a linear response in low light [...] Read more.

In this paper, we present a new logarithmic pixel design currently under development at New Imaging Technologies SA (NIT). This new logarithmic pixel design uses charge domain logarithmic signal compression and charge-transfer-based signal readout. This structure gives a linear response in low light conditions and logarithmic response in high light conditions. The charge transfer readout efficiently suppresses the reset (KTC) noise by using true correlated double sampling (CDS) in low light conditions. In high light conditions, thanks to charge domain logarithmic compression, it has been demonstrated that 3000 electrons should be enough to cover a 120 dB dynamic range with a mobile phone camera-like signal-to-noise ratio (SNR) over the whole dynamic range. This low electron count permits the use of ultra-small floating diffusion capacitance (sub-fF) without charge overflow. The resulting large conversion gain permits a single photon detection capability with a wide dynamic range without a complex sensor/system design. A first prototype sensor with 320 × 240 pixels has been implemented to validate this charge domain logarithmic pixel concept and modeling. The first experimental results validate the logarithmic charge compression theory and the low readout noise due to the charge-transfer-based readout. Full article

(This article belongs to the Special Issue Special Issue on the 2017 International Image Sensor Workshop (IISW))

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4 pages, 661 KB

Open AccessProceeding Paper

Linear-Logarithmic CMOS Image Sensor with Reduced FPN Using Photogate and Cascode MOSFET

by Myunghan Bae, Byung-Soo Choi, Sang-Hwan Kim, Jimin Lee, Chang-Woo Oh, Pyung Choi and Jang-Kyoo Shin

Proceedings 2017, 1(4), 338; https://doi.org/10.3390/proceedings1040338 - 18 Aug 2017

Viewed by 3000

Abstract

We propose a linear-logarithmic CMOS image sensor with reduced fixed pattern noise (FPN). The proposed linear-logarithmic pixel based on a conventional 3-transistor active pixel sensor (APS) structure has additional circuits in which a photogate and a cascade MOSFET are integrated with the pixel [...] Read more.

We propose a linear-logarithmic CMOS image sensor with reduced fixed pattern noise (FPN). The proposed linear-logarithmic pixel based on a conventional 3-transistor active pixel sensor (APS) structure has additional circuits in which a photogate and a cascade MOSFET are integrated with the pixel structure in conjunction with the photodiode. To improve FPN, we applied the PMOSFET hard reset method as a reset transistor instead of NMOSFET reset normally used in APS. The proposed pixel has been designed and fabricated using 0.18-μm 1-poly 6-metal standard CMOS process. A 120 × 240 pixel array of test chip was divided into 2 different subsections with 60 × 240 sub-arrays, so that the proposed linear-logarithmic pixel with reduced FPN could be compared with the conventional linear-logarithmic pixel. We confirmed a reduction of pixel response variation which affected image quality. Full article

(This article belongs to the Proceedings of Proceedings of Eurosensors 2017, Paris, France, 3–6 September 2017)

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22 pages, 495 KB

Open AccessArticle

Using Polynomials to Simplify Fixed Pattern Noise and Photometric Correction of Logarithmic CMOS Image Sensors

by Jing Li, Alireza Mahmoodi and Dileepan Joseph

Sensors 2015, 15(10), 26331-26352; https://doi.org/10.3390/s151026331 - 16 Oct 2015

Cited by 11 | Viewed by 7455

Abstract

An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable [...] Read more.

An important class of complementary metal-oxide-semiconductor (CMOS) image sensors are those where pixel responses are monotonic nonlinear functions of light stimuli. This class includes various logarithmic architectures, which are easily capable of wide dynamic range imaging, at video rates, but which are vulnerable to image quality issues. To minimize fixed pattern noise (FPN) and maximize photometric accuracy, pixel responses must be calibrated and corrected due to mismatch and process variation during fabrication. Unlike literature approaches, which employ circuit-based models of varying complexity, this paper introduces a novel approach based on low-degree polynomials. Although each pixel may have a highly nonlinear response, an approximately-linear FPN calibration is possible by exploiting the monotonic nature of imaging. Moreover, FPN correction requires only arithmetic, and an optimal fixed-point implementation is readily derived, subject to a user-specified number of bits per pixel. Using a monotonic spline, involving cubic polynomials, photometric calibration is also possible without a circuit-based model, and fixed-point photometric correction requires only a look-up table. The approach is experimentally validated with a logarithmic CMOS image sensor and is compared to a leading approach from the literature. The novel approach proves effective and efficient. Full article

(This article belongs to the Section Physical Sensors)

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Graphical abstract

14 pages, 1794 KB

Open AccessArticle

An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors

by Yuan Cao, Xiaofang Pan, Xiaojin Zhao and Huisi Wu

Sensors 2014, 14(12), 24132-24145; https://doi.org/10.3390/s141224132 - 15 Dec 2014

Cited by 10 | Viewed by 7431

Abstract

In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma [...] Read more.

In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS) process. Full article

(This article belongs to the Section Physical Sensors)

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18 pages, 3508 KB

Open AccessArticle

Digital Pixel Sensor Array with Logarithmic Delta-Sigma Architecture

by Alireza Mahmoodi, Jing Li and Dileepan Joseph

Sensors 2013, 13(8), 10765-10782; https://doi.org/10.3390/s130810765 - 16 Aug 2013

Cited by 16 | Viewed by 11600

Abstract

Like the human eye, logarithmic image sensors achieve wide dynamic range easily at video rates, but, unlike the human eye, they suffer from low peak signal-to-noise-and-distortion ratios (PSNDRs). To improve the PSNDR, we propose integrating a delta-sigma analog-to-digital converter (ADC) in each pixel. [...] Read more.

Like the human eye, logarithmic image sensors achieve wide dynamic range easily at video rates, but, unlike the human eye, they suffer from low peak signal-to-noise-and-distortion ratios (PSNDRs). To improve the PSNDR, we propose integrating a delta-sigma analog-to-digital converter (ADC) in each pixel. An image sensor employing this architecture is designed, built and tested in 0.18 micron complementary metal-oxide-semiconductor (CMOS) technology. It achieves a PSNDR better than state-of-the-art logarithmic sensors and comparable to the human eye. As the approach concerns an array of many ADCs, we use a small-area low-power delta-sigma design. For scalability, each pixel has its own decimator. The prototype is compared to a variety of other image sensors, linear and nonlinear, from industry and academia. Full article

(This article belongs to the Section Physical Sensors)

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18 pages, 1726 KB

Open AccessArticle

A Novel Method to Increase LinLog CMOS Sensors’ Performance in High Dynamic Range Scenarios

by Antonio Martínez-Sánchez, Carlos Fernández, Pedro J. Navarro and Andrés Iborra

Sensors 2011, 11(9), 8412-8429; https://doi.org/10.3390/s110908412 - 29 Aug 2011

Cited by 7 | Viewed by 10041

Abstract

Images from high dynamic range (HDR) scenes must be obtained with minimum loss of information. For this purpose it is necessary to take full advantage of the quantification levels provided by the CCD/CMOS image sensor. LinLog CMOS sensors satisfy the above demand by [...] Read more.

Images from high dynamic range (HDR) scenes must be obtained with minimum loss of information. For this purpose it is necessary to take full advantage of the quantification levels provided by the CCD/CMOS image sensor. LinLog CMOS sensors satisfy the above demand by offering an adjustable response curve that combines linear and logarithmic responses. This paper presents a novel method to quickly adjust the parameters that control the response curve of a LinLog CMOS image sensor. We propose to use an Adaptive Proportional-Integral-Derivative controller to adjust the exposure time of the sensor, together with control algorithms based on the saturation level and the entropy of the images. With this method the sensor’s maximum dynamic range (120 dB) can be used to acquire good quality images from HDR scenes with fast, automatic adaptation to scene conditions. Adaptation to a new scene is rapid, with a sensor response adjustment of less than eight frames when working in real time video mode. At least 67% of the scene entropy can be retained with this method. Full article

(This article belongs to the Section Physical Sensors)

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27 pages, 3509 KB

Open AccessArticle

Design and Fabrication of Vertically-Integrated CMOS Image Sensors

by Orit Skorka and Dileepan Joseph

Sensors 2011, 11(5), 4512-4538; https://doi.org/10.3390/s110504512 - 27 Apr 2011

Cited by 19 | Viewed by 19090

Abstract

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data [...] Read more.

Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. Full article

(This article belongs to the Special Issue State-of-the-Art Sensors in Canada)

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