Search Results (46)

This paper presents a novel cochlear implant (CI) sound coding strategy called Spectral Feature Extraction (SFE). The SFE is a novel Fast Fourier Transform (FFT)-based Continuous Interleaved Sampling (CIS) strategy that provides less-smeared spectral cues to CI patients compared to Crystalis, a predecessor strategy used in Oticon Medical devices. The study also explores how the SFE can be enhanced into a Temporal Fine Structure (TFS)-based strategy named Spectral Event Extraction (SEE), combining spectral sharpness with temporal cues. Background/Objectives: Many CI recipients understand speech in quiet settings but struggle with music and complex environments, increasing cognitive effort. De-smearing the power spectrum and extracting spectral peak features can reduce this load. The SFE targets feature extraction from spectral peaks, while the SEE enhances TFS-based coding by tracking these features across frames. Methods: The SFE strategy extracts spectral peaks and models them with synthetic pure tone spectra characterized by instantaneous frequency, phase, energy, and peak resemblance. This deblurs input peaks by estimating their center frequency. In SEE, synthetic peaks are tracked across frames to yield reliable temporal cues (e.g., zero-crossings) aligned with stimulation pulses. Strategy characteristics are analyzed using electrodograms. Results: A flexible Frequency Allocation Map (FAM) can be applied to both SFE and SEE strategies without being limited by FFT bandwidth constraints. Electrodograms of Crystalis and SFE strategies showed that SFE reduces spectral blurring and provides detailed temporal information of harmonics in speech and music. Conclusions: SFE and SEE are expected to enhance speech understanding, lower listening effort, and improve temporal feature coding. These strategies could benefit CI users, especially in challenging acoustic environments. Full article

Turbo Codes (TCs) are a family of convolutional codes that provide powerful Forward Error Correction (FEC) and operate near the Shannon limit for channel capacity. In the context of modern communication systems, such as those conforming to the DVB-RCS2 standard, Turbo Encoders (TEs) play a crucial role in ensuring robust data transmission over noisy satellite links. A key computational bottleneck in the Turbo Encoder is the non-uniform interleaving stage, where input bits are rearranged according to a dynamically generated permutation pattern. This stage often requires the intermediate storage of data, resulting in increased latency and reduced throughput, especially in embedded or real-time systems. This paper introduces a vector processing algorithm designed to accelerate the interleaving stage of the Turbo Encoder. The proposed algorithm is tailored for vector DSP architectures (e.g., CEVA-XC4500), and leverages the hardware’s SIMD capabilities to perform the permutation operation in a structured, phase-wise manner. Our method adopts a modular Load–Execute–Store design, facilitating efficient memory alignment, deterministic latency, and hardware portability. We present a detailed breakdown of the algorithm’s implementation, compare it with a conventional scalar (serial) model, and analyze its compatibility with the DVB-RCS2 specification. Experimental results demonstrate significant performance improvements, achieving a speed-up factor of up to 3.4× in total cycles, 4.8× in write operations, and 7.3× in read operations, relative to the baseline scalar implementation. The findings highlight the effectiveness of vectorized permutation in FEC pipelines and its relevance for high-throughput, low-power communication systems. Full article

The error correction capability of the RS(255,223) code has been significantly enhanced compared to that of the RS(256,252) code, making it the preferred choice for the next generation of onboard solid-state recorders (O-SSRs). With the application of non-volatile double data rate (NV-DDR) interface technology in O-SSRs, instantaneous transmission rates of up to 1 Gbps per data I/O interface can be achieved. This development imposes higher requirements on the encoding throughput of RS encoders. For RS(255,223) encoders, throughput improvement is limited by the structures of serial architectures. The algorithm’s inherent characteristics restrict the depth of pipelining. In contrast, parallel solutions face bottlenecks in resource efficiency. To address these challenges, an interleaved pipelined architecture is proposed. By integrating interleaving technology within the pipeline, the structure overcomes the limitations of serial architectures. Using this architecture, a 36-stage pipelined RS(255,223) encoder is implemented. The throughput is greatly enhanced, and the radiation tolerance is also improved due to the application of interleaving techniques. The RS(255,223) encoder performance was evaluated on the Xilinx XC7K325T platform. The results confirm that the proposed architecture can support high data rates and provide effective error correction. With an 8-bit symbol size, a single encoder achieved throughput of 3.043 Gbps, making it highly suitable for deployment in future space exploration missions. Full article

Multi-level coded modulation (MLCM) enhances data transmission by allocating error correction more effectively to bits with higher error probabilities, thus optimizing redundancy and improving performance. Despite MLCM’s advantages over traditional bit-interleaved coded modulation (BICM) systems in certain scenarios, its integration with hybrid automatic repeat request (HARQ) systems remains underexplored. HARQ, which combines the benefits of forward error correction (FEC) and automatic repeat request (ARQ), significantly increases resilience to interference and fading, enhancing overall system reliability. This paper bridges the gap by integrating HARQ techniques into the MLCM framework, which was specifically adapted to the layered nature of MLCM. We present tailored hybrid retransmission strategies for each layer of MLCM, demonstrating substantial gains in retransmission efficiency and overall transmission performance. Full article

In the context of Internet of Things and 5G communication, ensuring the accuracy and reliability of data transmission is critical, especially as the future 6G communication system places a greater emphasis on highly reliable transmission. However, the existing error correction schemes for 5G are found to be insufficient in their error correction capability for the 6G environment. To address this issue, this paper proposes an enhanced error correction scheme, which is an improvement over existing methods. This scheme is based on a combination of cyclic redundancy check (CRC) codes and Polar Codes, optimized through the use of a Successive Cancellation Decoding algorithm. The objective is to enhance the error detection and correction capabilities during data transmission. By leveraging the synergistic application of CRC and Polar Codes, the proposed scheme introduces enhanced sequence interleaving techniques and error pattern analysis, which significantly improve the decoding algorithm’s performance and accuracy. Experimental results demonstrate that the proposed scheme, in comparison to the traditional Successive Cancellation Decoding algorithm, effectively reduces the block error rate (BLER), thereby enhancing the high reliability of data transmission. Full article

The data acquisition rate of electromagnetic spectrum sensors is exceedingly high. However, the throughput of current high-speed spaceborne solid-state recorders (S-SSR) remains relatively low, making it difficult for the data to be fully stored. To address this issue, a novel architecture for a high-speed S-SSR is introduced in this study. The throughput of the S-SSR is primarily limited by three factors: the performance of the error-checking algorithm, the inability of a single FPGA to support the parallel expansion of too many Flash chips due to its limited effective I/O pins, and the efficiency of FLASH control. In the proposed architecture, a 10-stage pipelined RS(252,256) code is implemented. Data are distributed and stored in different memory regions controlled by separate FPGAs. Interleaved storage, multi-plane, and cache operation FLASH control module are also employed to resolve these bottlenecks. To further increase the throughput of the S-SSR, the system clock distribution has been optimized. In addition, interleaved encoding technology has been applied to improve radiation resistance and ensure data integrity. The performance of the system was evaluated on the Xilinx XC7K325T platform. The results confirm that the architecture is capable of handling high data rates and effectively correcting errors. The system can achieve a throughput of 46.8948 Gbps, making it suitable for future deployment in space exploration missions. Full article

Parallel Concatenated Block (PCB) codes are conventionally represented as high-rate codes with low error correcting capability. To form a reliable and outstanding code, this paper presents a modification on the structure of PCB codes, which is accomplished by encoding some parity bits of one of their component codes. For the newly proposed code, named as the braided code, non-stuff bit-based convolutional interleavers are applied, aiming to minimize the design complexity while ensuring the proper permutations of the original message and selected parity bits. To precisely determine the error correcting capability, a tight bound for the minimum weight of braided code is presented. Additionally, further analyses are provided, which verify iterative decoding performance and the complexity of the constructed code. It is concluded that an outstanding braided code is formed by utilizing a reasonable number of iterations applied at its decoding processes, while maintaining its design complexity at a level similar to other well-known codes. The significant performance of short and long-length-based braided codes is evident in both waterfall and error floor regions. Full article

Secure distributed matrix multiplication (SDMM) schemes are crucial for distributed learning algorithms where extensive data computation is distributed across multiple servers. Inspired by the application of repairing Reed–Solomon (RS) codes in distributed storage and secret sharing, we propose SDMM schemes with reduced communication overhead through the use of trace polynomials. Specifically, these schemes are designed to address three critical concerns: (i) ensuring information-theoretic privacy against collusion among servers; (ii) providing security against Byzantine servers; and (iii) offering resiliency against stragglers to mitigate computing delays. To the best of our knowledge, security and resiliency are being considered for the first time within trace polynomial-based approaches. Furthermore, our schemes offer the advantage of reduced sub-packetization and a lower server-count requirement, which diminish the computational complexity and download cost for the user. Full article

Polymerase Chain Reaction (PCR) amplification is widely used for retrieving information from DNA storage. During the PCR amplification process, nonspecific pairing between the 3’ end of the primer and the DNA sequence can cause cross-talk in the amplification reaction, leading to the generation of interfering sequences and reduced amplification accuracy. To address this issue, we propose an efficient coding algorithm for PCR amplification information retrieval (ECA-PCRAIR). This algorithm employs variable-length scanning and pruning optimization to construct a codebook that maximizes storage density while satisfying traditional biological constraints. Subsequently, a codeword search tree is constructed based on the primer library to optimize the codebook, and a variable-length interleaver is used for constraint detection and correction, thereby minimizing the likelihood of nonspecific pairing. Experimental results demonstrate that ECA-PCRAIR can reduce the probability of nonspecific pairing between the 3’ end of the primer and the DNA sequence to 2–25%, enhancing the robustness of the DNA sequences. Additionally, ECA-PCRAIR achieves a storage density of 2.14–3.67 bits per nucleotide (bits/nt), significantly improving storage capacity. Full article

With the development of the Internet and information technology, optical fiber communication systems need to meet people’s information demand for large capacity and high speed. High-order phase modulation and channel multiplexing can improve the capacity and data rate of optical fiber communication systems, but they also bring the problem of bit error. To improve the transmission quality and reliability of optical fiber communication systems, forward error correction (FEC) coding techniques are commonly used, which serve as the fundamental approach to enhance the quality and reliability of fiber optic communication systems, ensuring that the received data remain accurate and reliable. The FEC in optical fiber communication systems is divided into three generations. The first generation FEC is mainly hard decision codewords, represented as RS code. The second generation FEC is mainly cascaded code, which stands for interleaved cascaded code. The third generation of FEC mainly refers to soft decision codes, which are represented as low-density parity-check (LDPC) codes. As a kind of FEC, LDPC codes stand out as pivotal contributors in the field of optical communication and have gained remarkable attention due to exceptional error correction performance and low decoding complexity. Based on IEEE802.16e standard, LDPC code with specific code length and rate is compiled and simulated in MATLAB and VPItransmissionMaker 10.1 and successfully incorporated into polarization multiplexed differential quadrature phase shift keying (PM-DQPSK) coherent optical transmission system. The simulation results indicate that the bit error rate (BER) can be reduced to 10⁻³ when the optical signal-to-noise ratio (OSNR) reaches 14.2 dB, and the BER experiences a reduction by nearly three orders of magnitude when the OSNR is 17.2 dB. These findings underscore the efficacy of LDPC codes in significantly improving the performance of optical communication systems, particularly in scenarios demanding robust error correction capabilities. This study provides valuable, significant results regarding the potential of LDPC codes for enhancing the reliability of optical transmission in real-world applications. Full article

Severe conditions such as high-energy particle strikes may induce soft errors in on-chip memory, like cache and translation lookaside buffers (TLBs). As the key component of virtual-to-physical address translation, TLB directly affects processor performance. To protect the virtual page information stored in TLB, several studies have introduced error detection or correction codes. However, most schemes proposed for data TLB cannot support the detection of multi-bit upsets, which is reported as a serious issue in modern fault-tolerant processors due to the downscaling of CMOS process technology. In this paper, we propose a new two-dimensional protection technique, called the matrix protection tag (MaP-Tag), to provide stronger error detection and correction capability to TLB virtual page information. Our proposal reorganizes virtual page information into a matrix and employs adjacent check bits and interleaved check bits for error detection. The two-dimensional design offers one-bit error detection, burst multi-bit error detection, and even multi-bit error correction in some cases. The simulation results show that our proposal can detect almost all error patterns when injected with up to eight bit-flips. Furthermore, the technique provides a better error correction rate than conventional single error correction (SEC) codes. The reliability calculation shows that our proposal is powerful in both error detection and correction with affordable storage overhead. Full article

A multi-constellation, multi-frequency Global Navigation Satellite System (GNSS) receiver is capable of simultaneously receiving signals from multiple satellite constellations across various frequency bands. This allows for increased observations, thereby enhancing navigation accuracy, continuity, effectiveness, and reliability. The spread spectrum code structures used in satellite navigation signals differ among systems. Compatible code generators are employed in multi-constellation, multi-frequency GNSS receivers to support tasks such as signal acquisition and tracking. There are three main types of spread spectrum code structures: Linear Feedback Shift Register (LFSR), Legendre sequences, and Memory codes. The Indian Regional Navigation Satellite System (IRNSS) released the L1-SPS (Standard Positioning Service) signal format in August 2023, which utilizes the Interleaved Z4-linear ranging code (IZ4 code) as its spread spectrum code. Currently, there is no universal code generator design compatible with the IZ4 code. In this paper, a proposed universal code generator is based on the hardware structure of the IRNSS IZ4 code generator. It achieves compatibility with all LFSR-based spread spectrum codes and enables parallel generation of multiple sets of GNSS signal spread spectrum codes, thereby improving hardware utilization efficiency. The proposed structure is implemented and validated using FPGA design, and resource consumption is provided as part of the validation results. Full article

The tremendous increase in the use of video-based eye tracking has made it possible to collect eye tracking data from thousands of participants. The traditional procedures for the manual detection and classification of saccades and for trial categorization (e.g., correct vs. incorrect) are not viable for the large datasets being collected. Additionally, video-based eye trackers allow for the analysis of pupil responses and blink behaviors. Here, we present a detailed description of our pipeline for collecting, storing, and cleaning data, as well as for organizing participant codes, which are fairly lab-specific but nonetheless, are important precursory steps in establishing standardized pipelines. More importantly, we also include descriptions of the automated detection and classification of saccades, blinks, “blincades” (blinks occurring during saccades), and boomerang saccades (two nearly simultaneous saccades in opposite directions where speed-based algorithms fail to split them), This is almost entirely task-agnostic and can be used on a wide variety of data. We additionally describe novel findings regarding post-saccadic oscillations and provide a method to achieve more accurate estimates for saccade end points. Lastly, we describe the automated behavior classification for the interleaved pro/anti-saccade task (IPAST), a task that probes voluntary and inhibitory control. This pipeline was evaluated using data collected from 592 human participants between 5 and 93 years of age, making it robust enough to handle large clinical patient datasets. In summary, this pipeline has been optimized to consistently handle large datasets obtained from diverse study cohorts (i.e., developmental, aging, clinical) and collected across multiple laboratory sites. Full article

Labeling-Based Recipient Identification (LABRID) brings the possibility of representing the destination station address in a Bit-Interleaved Coded Modulation with Iterative Decoding (BICM-ID) system by a signal labeling rule. Low-order modulations, such as BPSK or QPSK, pose a general problem for BICM-ID due to a limited convergence of iterative decoding. In the context of LABRID, they have one more drawback—a small number of different labeling rules in general; the number of the optimal ones, which exhibit the maximal asymptotic coding gain, is reduced even further. Meanwhile, LABRID needs a sizable collection of different optimal labeling rules to serve many users in large wireless networks. In this paper, the author suggests the use of hypercube BPSK or QPSK labeling to overcome all these challenges. By means of the Reactive Tabu Search (RTS) algorithm, more than 1500 equivalent optimal hypercube labeling rules are found. Analytical error bounds of the system are developed and supported by simulation experiments. Then, the focus is moved to the criterion to determine the frame destination at the LABRID receiver; a simple threshold-based method is proposed to keep the incorrect decision probability below ${10}^{-5}$. Finally, it is shown that LABRID outperforms a reference BICM-ID system in terms of computational complexity. Full article

This paper proposes an adaptive bit-interleaved polar coded modulation (A-BIPCM) method based on minimum logarithmic upper bound weight (MLUW). It is designed to reduce the fading effects and long string of bit error interference caused by atmospheric turbulence in free-space optical communications (FSOC). To assess the effectiveness of this method across turbulent channels of varying intensities, we conducted an evaluation of the bit error rate (BER) performance of polar codes in turbulent channels. The results demonstrate significant performance improvements provided by the A-BIPCM method compared to conventional polar code encoding and decoding. Specifically, under weak, moderate, and strong turbulence conditions, the A-BIPCM method achieves performance gains of 0.96 dB, 1.66 dB, and 1.35 dB, respectively. Additionally, an experimental verification platform for FSOC employing intensity modulation direct detection (IM/DD) with an atmospheric turbulence simulation channel, is established in this work. When the optical power of the detector is −16 dBm, the traditional polar code encoding and decoding performance at BER = 2.36 × 10⁻⁵, whereas the A-BIPCM scheme exhibits a significantly higher performance at BER = 2.11 × 10⁻⁶. The BER has been improved by representing an order of magnitude. Full article