Search Results (11)

A 4H-silicon carbide (SiC) trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) with dual integrated Schottky barrier diodes (SBDs) was characterized using numerical simulations. The advantage of three-dimensional stacked integration is that it allows the proposed structure to obtain an electric field of below 0.6 MV/cm in the gate oxide and SBD contacts and achieve ~10% lower forward voltage of SBDs than the planar gate SBD-integrated MOSFET (PSI-MOS) and the trench gate structure with three p-type-protecting layers (TPL-MOS). The dual-SBD-integrated MOSFET (DSI-MOS) also highlights the better influences of the more than 70% reduction in the miller charge, as well as the over 50% reduction in switching loss compared to the others. Furthermore, the short-circuit (SC) robustness of the three devices was identified. The DSI-MOS attains the critical energy and the aluminum melting point in a longer SC time interval than the TPL-MOS. The p-shield layers in the DSI-MOS are demonstrated to yield the huge benefit of improving the reliability of the contacts when SC reliability is considered. Full article

As a promising candidate for More Moore technology, InGaAs-based n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) have attracted growing research interest, especially with InGaAs-on-insulator (InGaAs-OI) configurations aimed at alleviating the short channel effects. Correspondingly, the fabrication of an ultrathin InGaAs body becomes necessary for the full depletion of the channel, while the deteriorated semiconductor–insulator interface-related scattering could severely limit carrier mobility. This work focuses on the exploration of carrier mobility enhancement strategies for 8 nm body-based InGaAs-OI nMOSFETs. With the introduction of a bottom gate bias on the substrate side, the conduction band structure in the channel was modified, relocating the carrier wave function from the InGaAs/Al₂O₃ interface into the body. Resultantly, the channel mobility with an inversion layer carrier concentration of 1 × 10¹³ cm⁻² was increased by 62%, which benefits InGaAs-OI device application in monolithic 3D integration. The influence of the dual-gate bias from front gate and bottom gate on gate stability was also investigated, where it has been unveiled that the introduction of the positive bottom gate bias is also beneficial for gate stability with an alleviated orthogonal electric field. Full article

Background: The electrodes of implantable cardiac devices (ICDs) may cause significant problems in cardiac computed tomography (CT) because they are a source of artifacts that obscure surrounding structures and possible pathology. There are a few million patients currently with ICDs, and some of these patients will require cardiac imaging due to coronary artery disease or problems with ICDs. Modern CT scanners can reduce some of the metal artifacts because of MAR software, but in some vendors, it does not work with ECG gating. Introduced in 2008, dual-energy CT scanners can generate virtual monoenergetic images (VMIs), which are much less susceptible to metal artifacts than standard CT images. Objective: This study aimed to evaluate if dual-energy CT can reduce metal artifacts caused by ICD leads by using VMIs. The second objective was to determine how the angle between the electrode and the plane of imaging affects the severity of the artifacts in three planes of imaging. Methods: A 3D-printed model was constructed to obtain a 0–90-degree field at 5-degree intervals between the electrode and each of the planes: axial, coronal, and sagittal. This electrode was scanned in dual-energy and single-energy protocols. VMIs with an energy of 40–140 keV with 10 keV intervals were reconstructed. The length of the two most extended artifacts originating from the tip of the electrode and 2 cm above it—at the point where the thick metallic defibrillating portion of the electrode begins—was measured. Results: For the sagittal plane, these observations were similar for both points of the ICDs that were used as the reference location. VMIs with an energy over 80 keV produce images with fewer artifacts than similar images obtained in the single-energy scanning mode. Conclusions: Virtual monoenergetic imaging techniques may reduce streak artifacts arising from ICD electrodes and improve the quality of the image. Increasing the angle of the electrode as well as the imaging plane can reduce artifacts. The angle between the electrode and the beam of X-rays can be increased by tilting the gantry of the scanner or lifting the upper body of the patient. Full article

In this work, a novel enhancement-mode GaN p-MISFET with a buried back gate (BBG) is proposed to improve the gate-to-channel modulation capability of a high drain current. By using the p-GaN/AlN/AlGaN/AlN double heterostructure, the buried 2DEG channel is tailored and connected to the top metal gate, which acts as a local back gate. Benefiting from the dual-gate structure (i.e., top metal gate and 2DEG BBG), the drain current of the p-MISFET is significantly improved from −2.1 (in the conv. device) to −9.1 mA/mm (in the BBG device). Moreover, the dual-gate design also bodes well for the gate to p-channel control; the subthreshold slope (SS) is substantially reduced from 148 to ~60 mV/dec, and such a low SS can be sustained for more than 3 decades. The back gate effect and the inherent hole compensation mechanism of the dual-gate structure are thoroughly studied by TCAD simulation, revealing their profound impact on enhancing the subthreshold and on-state characteristics in the BBG p-MISFET. Furthermore, the decent device performance of the proposed BBG p-MISFET is projected to the complementary logic inverters by mixed-mode simulation, showcasing excellent voltage transfer characteristics (VTCs) and dynamic switching behavior. The proposed BBG p-MISFET is promising for developing GaN-on-Si monolithically integrated complementary logic and power devices for high efficiency and compact GaN power IC. Full article

This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual-material gate (DMG) and gate stack (GS) as gate engineering techniques and its analog/RF performance parameters are compared to those of the Gate-All-Around Single-Material Gate Charge Plasma Nanowire Field Effect Transistor (GAA-SMG-CP NW-FET) device. Both Gate-All-Around (GAA) devices are designed using the Silvaco TCAD tool. GAA structures have demonstrated good gate control because the gate holds the channel, which is an inherent advantage for both devices discussed herein. The charge plasma dopingless technique is used, in which the source and drain regions are formed using metal contacts and necessary work functions rather than doping. This dopingless technique eliminates the need for doping, reducing fluctuations caused by random dopants and lowering the device’s thermal budget. Gate engineering techniques such as DMG and GS significantly improved the current characteristics which played a crucial role in obtaining maximum gain for circuit designs. The lookup table (LUT) approach is used in the implementation of the CS amplifier circuit with the proposed device. The transient response of the circuit is analyzed with both the device structures where the gain achieved for the CS amplifier circuit using the proposed GAA-DMG-GS-CP NW-FET is 15.06 dB. The superior performance showcased by the proposed GAA-DMG-GS-CP NW-FET device with analog, RF and circuit analysis proves its strong candidature for future nanoscale and low-power applications. Full article

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM) cell based on a polycrystalline silicon dual-gate metal-oxide-semiconductor field-effect transistor with a fin-shaped structure was optimized and analyzed using technology computer-aided design simulation. The proposed 1T-DRAM demonstrated improved memory characteristics owing to the adoption of the fin-shaped structure on the side of gate 2. This was because the holes generated during the program operation were collected on the side of gate 2, allowing an expansion of the area where the holes were stored using the fin-shaped structure. Therefore, compared with other previously reported 1T-DRAM structures, the fin-shaped structure has a relatively high retention time due to the increased hole storage area. The proposed 1T-DRAM cell exhibited a sensing margin of 2.51 μA/μm and retention time of 598 ms at T = 358 K. The proposed 1T-DRAM has high retention time and chip density, so there is a possibility that it will replace DRAM installed in various applications such as PCs, mobile phones, and servers in the future. Full article

This study investigates the effect of gate insulators on thin-film transistors (TFTs) using an amorphous InGaZnO₄ (a-IGZO) channel layer. TFTs with single-layer Ta₂O₅ and dual-layer Ta₂O₅/SiO₂ gate insulators were fabricated on a glass substrate. An evaluation of the insulating film using the MIM (Metal-Insulator-Metal) structure confirmed its electrical characteristics. Microscopic imaging showed that the dual-layer Ta₂O₅/SiO₂ dielectric significantly improved surface characteristics. A reduction in the leakage current, better on/off ratios, and a decreased subthreshold swing (SS) compared to a single-layer Ta₂O₅ dielectric were reported. The dual-layer insulator composed of SiO₂/Ta₂O₅ was highly effective in improving device characteristics. Full article

Ultraviolet-visible absorption spectroscopy is widely used to monitor water quality, and rapid optical signal detection is a key technology in the process of spectrum measurement. In this paper, an ultrafast spectrophotometer system that can achieve spectrum data acquisition in a single flash of the xenon lamp (within 200 ns) is introduced, and a real-time denoising method for the spectrum is implemented on a field programmable gate array (FPGA) to work cooperatively with the nanosecond spectrum acquisition system, in order to guarantee the quality of the spectrum signals without losing running speed. The hardware of the data acquisition and processing system are constructed on a Xilinx Spartan 6 FPGA chip and its peripheral circuit, including an analog to digital converter and a complementary metal-oxide-semiconductor transistor (CMOS) sensor’s diver circuit. An oversampling method that is suitable for the CMOS sensor’s output is proposed, which works on the CMOS sensor’s dark current noise and readout noise. Another moving-average filter method is designed adaptively, which works on the low-frequency component to filter out the residual spectrum noise of the spectrum signal. The implementation of the filter on the FPGA has been optimized by using a pipelined structure and dual high-speed random-access memory (RAM). As a result, the CMOS linear image sensor successfully captured the spectrum of xenon flash light at the readout clock frequency of 500 kHz and the processing manipulation to the full UV-Vis spectrum data was accomplished at a sub-microsecond speed performance. After the digital filter and oversampling technology were implemented, the coefficient of variation of the measurements reduced from 9.57% to 1.74%, while the signal noise ratio (SNR) of the absorption spectrum increased nine times, compared to the raw data of the CMOS sensor’s output. The tests towards different analyte samples were conducted, and the system shows good performance on distinguishing different concentrations of different analyte solutions on both ultra-violet and visible spectrum bands. The present work showcases the potential of the CMOS sensor’s technique for the fast detection of contaminated water containing nitrate and organic compounds. Full article

The electrical and thermal characteristics of AlGaN/GaN high-electron mobility transistor (HEMT) devices with a dual-metal gate (DMG) structure are investigated by electrothermal simulation and compared with those of conventional single-metal gate (SMG) structure devices. The simulations reveal that the DMG structure devices have a 10-percent higher transconductance than the SMG structure devices when the self-heating effect is considered. In the meantime, employing the DMG structure, a decrease of more than 11% in the maximum temperature rise of the devices can be achieved at the power density of 6 W/mm. Furthermore, the peak in heat generation distribution at the gate edge of the devices is reduced using this structure. These results could be attributed to the change in the electric field distribution at the gate region and the suppression of the self-heating effect. Therefore, the electrical and thermal performances of AlGaN/GaN HEMT devices are improved by adopting the DMG structure. Full article

A gallium nitride (GaN)-based normally off metal–oxide–semiconductor field-effect transistor (MOSFET) using a dual-metal-gate (DMG) structure was proposed and fabricated to improve current drivability. Normally off operation with a high V_th of 2.3 V was obtained using a Cl₂/BCl₃-based recess etching process. The DMG structure was employed to improve current characteristics, which can be degraded by recess etching. The I_D and g_m of a DMG-based device with nickel (Ni)-aluminum (Al) were improved by 42.1% and 30.9%, respectively, in comparison to the performances of a single-metal-gate-based device with Ni because the DMG structure increased electron velocity in the channel region. This demonstrates that the DMG structure with a large work-function difference significantly improves the carrier transport efficiency. GaN-based recessed-gate MOSFETs based on the DMG structure hold promising potentials for high-efficiency power devices. Full article

In this paper, the impact of La₂O₃ passivation layers on the interfacial properties of Ge-based metal-insulator-semiconductor (MIS) structures was investigated. It was proven that the formation of a thermodynamically stable LaGeO_x component by incorporating a La₂O₃ interlayer could effectively suppress desorption of the interfacial layer from GeO₂ to volatile GeO. The suppression of GeO desorption contributed to the decrease in oxide trapped charges and interfacial traps in the bulk of the gate insulator, or the nearby interfacial regions in the Al₂O₃/La₂O₃/Ge structure. Consequently, the hysteretic behavior of the dual-swept capacitance-voltage (C-V) curves and the frequency dispersion of multi-frequency C-V curves were remarkably weakened. Besides, more than one order of magnitude decrease in the gate leakage current density, and higher insulator breakdown electric field were obtained after inserting a La₂O₃ passivation layer. Full article