Improvements on the Interfacial Properties of High-k/Ge MIS Structures by Inserting a La₂O₃ Passivation Layer

Abstract

In this paper, the impact of La₂O₃ passivation layers on the interfacial properties of Ge-based metal-insulator-semiconductor (MIS) structures was investigated. It was proven that the formation of a thermodynamically stable LaGeO_x component by incorporating a La₂O₃ interlayer could effectively suppress desorption of the interfacial layer from GeO₂ to volatile GeO. The suppression of GeO desorption contributed to the decrease in oxide trapped charges and interfacial traps in the bulk of the gate insulator, or the nearby interfacial regions in the Al₂O₃/La₂O₃/Ge structure. Consequently, the hysteretic behavior of the dual-swept capacitance-voltage (C-V) curves and the frequency dispersion of multi-frequency C-V curves were remarkably weakened. Besides, more than one order of magnitude decrease in the gate leakage current density, and higher insulator breakdown electric field were obtained after inserting a La₂O₃ passivation layer.

1. Introduction

For a very long time, the excellent properties of a SiO₂/Si interface, with high band offsets and few interfacial defects, have been the key reasons for supporting Si use as the main semiconductor material in integrated circuits (IC) [1]. However, with the continued scaling of the device’s size feature on a Si-based complementary metal oxide semiconductor (CMOS) process, high dielectric constant (high-k) materials have been introduced as alternative gate oxide dielectrics to replace ultrathin SiO₂. The purpose was to reduce gate leakage current and power consumption beyond 45-nm technology nodes [2,3]. The introduction of high-k dielectrics into the Si-based CMOS process results in poorer insulator/Si interfaces compared to that of SiO₂/Si, bringing in some unfavorable impacts such as instability problems and mobility degradation [4]. Considering this, alternative technological progress to dimension scaling, such as changing channel material, is also necessary for achieving high performance devices [5]. Owing to its high intrinsic hole mobility, Ge has drawn remarkable attention for realizing high performance applications in the past decade [6,7]. Ge-based metal-insulator-semiconductor (MIS) devices have shown great potential for integration into the Si CMOS technology, since promising electrical characteristics beyond those of Si devices could be realized by high-k/Ge structures [8]. However, there are some obstacles to overcome before employing Ge into a CMOS-compatible processing scheme with high performance. One of the most critical issues to solve is the Ge surface passivation engineering prior to the deposition of gate oxides [9]. For most high-k dielectric films deposited on Ge substrates without any surface passivation treatments, the generation of unstable Ge oxides is unavoidable during the thermal annealing process. That is, at temperatures higher than 400 °C, GeO₂ reacts with Ge atoms at high-k dielectrics/Ge interface, which then form substoichiometric Ge oxides, including volatile GeO [10,11]. The desorption of GeO brings in a large number of structural defects, which would deteriorate the properties of the insulator/Ge interface [12].

Recently, it has been reported that rare earth oxides (REOs; i.e., Y₂O₃, CeO₂, Sm₂O₃, and La₂O₃) show high affinity for Ge atoms. That is, the strong reaction between REOs and Ge substrates leads to the catalytic oxidation of Ge, which results in the spontaneous formation of stable interfacial layers [13,14,15,16]. Amongst the REOs, due to their large dielectric constant and high band offset relative to Ge, La-based oxides are considered as one kind of promising alternative gate dielectrics in Ge-based MIS devices, which can achieve more aggressive equivalent oxide thickness (EOT) scaling [17,18]. Furthermore, as the interface between La-based oxides and Ge substrates shows much better thermodynamic stability than that of GeO₂/Ge, La-based oxides have promising interfacial passivation effects and could improve the electrical performance of Ge-based MIS devices [19,20]. Considering this, the effects of inserting a La₂O₃ passivation layer between an Al₂O₃ dielectric and Ge substrate, on the interfacial properties of Al/Al₂O₃/Ge and Al/Al₂O₃/La₂O₃/Ge MIS structures was investigated in this paper.

2. Experimental Section

La₂O₃ and Al₂O₃ gate stack films were deposited on n-type Ge (100) substrates, with electrical resistivity of about 0.1–1 Ω·cm, in an atomic layer deposition (ALD) reactor (R-150, Picosun, Espoo, Finland). Prior to the deposition, Ge substrates were treated with acetone and hydrous alcohol, and then cyclically dipped into a diluted HF solution (HF:H₂O = 1:50) 5 times to remove the native GeO_x layer. During the deposition process, La(ⁱ⁻PrCp)₃ and trimethylaluminum (TMA) were used as La and Al precursors, respectively, while H₂O was used as an oxidant. The precursors were alternately introduced to the reactor chamber, and were carried by high purity N₂ (>99.999%). A typical ALD growth cycle for La₂O₃ was 0.3 s La(ⁱ⁻PrCp)₃ pulse, followed by 4 s N₂ purge and 0.3 s H₂O pulse, followed by 9 s N₂ purge. The Al₂O₃ ALD cycle structure was set as 0.1 s TMA pulse/3 s N₂ purge/0.1 s H₂O pulse/4 s N₂ purge. By varying the number of ALD cycles, a 2 nm La₂O₃ oxide layer was deposited on the cleaned Ge substrate at 300 °C, followed by deposition of a 4 nm Al₂O₃ layer. For comparison, a control sample with only 6 nm Al₂O₃ as gate dielectrics was also prepared. After the deposition, rapid thermal annealing (RTA) was performed at 600 °C for 90 s in N₂ ambient for both Al₂O₃/La₂O₃/Ge and Al₂O₃/Ge structures.

The surface morphology of the deposited films was monitored using atomic force microscopy (AFM, Dimension 3100, Veeco Digital Instruments by Bruker, Billerica, MA, USA) in tapping mode. The physical thickness was optically measured using Woollam M2000D spectroscopic ellipsometry (SE, Woollam Co. Inc., Lincoln, NE, USA) fitted with a Cauchy model. The chemical bonding state of the samples related to Ge substrates was examined by X-ray photoelectron spectroscopy (XPS, Axis Ultra DLD, Kratos Analytical, Manchester, UK) measurements. MIS capacitor structures were used to evaluate the electrical properties of the deposited films. Al was evaporated using electron-beam evaporation as a metal gate through a shadow mask with a diameter of 300 μm followed by a post metallization annealing (PMA) carried out in 97% N₂/3% H₂ ambient at 400 °C for 20 min to form a good Ohmic contact with gate dielectrics. Then the electrical properties of the fabricated MIS capacitors were evaluated using an Agilent B1500A parameter analyzer (Santa Clara, CA, USA).

3. Results and Discussion

The Ge 3d spectra of the samples with and without the La₂O₃ passivation layer are shown in Figure 1. During the analysis of XPS data, the C 1s peak extracted from adventitious carbon at 284.6 eV was chosen as a bonding energy calibration reference. Compared with Figure 1a, a noteworthy change in Figure 1b was the appearance of a LaGeO_x peak, indicating that a LaGeO_x component was generated after inserting a thin La₂O₃ interlayer. Besides, the Ge oxide (GeO_x) spectra could be divided into four Gaussian–Lorentzian line shape peaks (Ge¹⁺, Ge²⁺, Ge³⁺, and Ge⁴⁺), which were located at a higher binding energy with respect to the Ge⁰ peak, with energy shifts of 0.8, 1.8, 2.6, and 3.4 eV, respectively [21]. The existence of these GeO_x species was caused by the formation of an interfacial layer between gate dielectric films and Ge substrates [22]. Among the Ge sub-oxides, GeO (Ge²⁺) is known to adversely affect interfacial properties in contrast to other Ge oxides (Ge¹⁺ and Ge³⁺), since GeO volatilization would cause a huge number of structural defects [13]. Compared with the control sample, a visible reduction in the intensity of the Ge²⁺ peak was observed in the Al₂O₃/La₂O₃/Ge case, indicating that to a certain extent, the formation of GeO was restrained by inserting a La₂O₃ passivation layer. Besides, it was observed that the intensity of the Ge⁴⁺ peak increased a bit after inserting a La₂O₃ passivation layer. Such variations in Ge²⁺ and Ge⁴⁺ peaks displayed a reasonable self-consistency, which was mainly ascribed to the reduction of desorption from GeO₂ (Ge⁴⁺) to GeO, benefiting from the generation of a thermodynamically stable LaGeO_x component near the La₂O₃/Ge interface [23].

The two- and three-dimensional AFM images of the Al₂O₃ films deposited on Ge substrates with and without a La₂O₃ interlayer are shown in Figure 2. The scan size of each AFM image was 1 × 1 µm². The root-mean-square (RMS) surface roughness of the films was extracted from the AFM images. The surface roughness of the sample without a La₂O₃ interlayer was about 0.62 nm in RMS, which was relatively a large RMS value for dielectric films deposited by ALD. We ascribed this large RMS value to the degradation of interfacial smoothness caused by the desorption of volatile GeO nearby the Al₂O₃/Ge interface during the high temperature post-deposition annealing (PDA) process [24]. While for the sample with a La₂O₃ interfacial passivation layer, an obviously smaller RMS value of 0.23 nm was observed. Such a reduction in the RMS value suggested that the desorption of GeO was suppressed since the existence of a thermodynamically stable LaGeO_x layer between gate oxides and Ge substrates restrained the generation of volatile GeO. The decrease in volatile GeO had a positive impact on the electrical performance in the Al₂O₃/La₂O₃/Ge case. This improvement will be discussed in detail in the following capacitance-voltage (C-V) and gate leakage current density-voltage (J-V) parts.

To further investigate the effects of a La₂O₃ interfacial passivation layer on the interfacial properties of Ge-based MIS structures, the electrical properties of the fabricated MIS capacitors were analyzed. Figure 3 shows the C-V and conductance-voltage (G-V) characteristics of the fabricated MIS capacitors using Al₂O₃ as an insulator, with and without a La₂O₃ passivation layer. For simplicity, the MIS capacitor using only Al₂O₃ as an insulator was marked as S1, and the MIS capacitor with La₂O₃ as an interfacial passivation layer was assigned as S2. The dual-swept C-V curves were obtained by biasing the gate-applied voltage from accumulation to inversion (backward sweep), and sweeping back (forward sweep) at 100 kHz. G-V measurements were performed simultaneously with the backward swept C-V curves. The capacitance values at the accumulation region of the C-V curves for capacitor S1 and S2 were 1.06 and 1.41 μF/cm², respectively. The dielectric constant values of the samples were estimated using the following equations [25,26]:

$$C_{\mathrm{ox}}=C_{\mathrm{ac}}\left[1+{\left(\frac{G_{\mathrm{ac}}}{\omega C_{\mathrm{ac}}}\right)}^2\right]$$

(1)

$$CET=\frac{{\epsilon }_0{\epsilon }_{\mathrm{Si}{\mathrm{O}}_2}A}{C_{\mathrm{ox}}}$$

(2)

$$k=\frac{{\epsilon }_{\mathrm{Si}{\mathrm{O}}_2}{t}_{\mathrm{ox}}}{CET}$$

(3)

where C_ac is the capacitance value at the accumulation region, G_ac is the conductance corresponding to the accumulation region of the C-V curves, ω is the angular frequency, C_ox is the oxide capacitance of dielectric films, A is the electrode area, t_ox is the measured thickness of gate dielectrics, ${\epsilon }_0$ and ${\epsilon }_{\mathrm{Si}{\mathrm{O}}_2}$ are the permittivity values of vacuum and SiO₂, respectively. The physical thickness of the gate dielectric films in S1 and S2 was measured to be 6.42 and 6.83 nm, separately. Therefore, the effective dielectric constant values of S1 and S2 were calculated to be 7.95 and 11.10, respectively. The increment in the dielectric constant value for the sample with a La₂O₃ interfacial passivation layer was attributed to the introduction of La elements into dielectric films, since the k values of La₂O₃ [27], and La_xAl_yO [28] formed by the interdiffusion of La₂O₃ and Al₂O₃ were much higher than that of Al₂O₃ [29].

The flat band voltages (V_FB) of the C-V curves in Figure 3 were extracted from the Hauser NCSU CVC simulation software (North Carolina State University, Raleigh, NC, USA), taking quantum mechanical effects into account [30]. It was observed that the Al/Al₂O₃/Ge MIS capacitor showed a much larger flat band voltage hysteresis width (ΔV_FB), ∼863 mV, than that of S2 (∼174 mV). The hysteretic behavior of the dual-swept C-V curves has been proven to be caused by the existence of oxide trapped charges (Q_ot) in the bulk of the gate insulator or nearby the interfacial region [31]. Using the midgap charge separation method, the oxide-trapped charge density (N_ot) for the fabricated capacitors was calculated using the following equation [32]:

$$N_{\mathrm{ot}}=\frac{\Delta V_{\mathrm{FB}}{C}_{\mathrm{ox}}}{qA}$$

(4)

where ΔV_FB is the hysteresis width of V_FB, C_ox is the oxide capacitance, q is the elementary charge (1.602 × 10⁻¹⁹ C), and A is the electrode area. The N_ot values were calculated to be 5.91 × 10¹² cm⁻² for the Al/Al₂O₃/Ge MIS capacitor, and 1.56 × 10¹² cm⁻² for the case with a La₂O₃ passivation layer. A visible decrease of N_ot was observed after inserting a La₂O₃ passivation layer.

The C-V curves of the MIS capacitors without the La₂O₃ interlayer showed a significant anomalous hump phenomena at the weak inversion regions as shown in Figure 3a, which were reported to be caused by slow interfacial traps existing between the gate insulator and substrate [33]. Besides, as shown in Figure 4, different amounts of interfacial traps caused different degrees of frequency dispersion phenomena at the weak inversion regions of the C-V curves measured at multi-frequencies. Considering this, we discussed the interface state density (D_it) values of S1 and S2, extracted from the combination of the backward swept C-V and G-V characteristics, using the following relation of single-frequency approximation method [29,34]:

$$D_{\mathrm{it}}=\frac{2}{qA}\frac{\frac{G_{\max }}{\omega }}{\left[{\left(\frac{G_{\max }}{\omega C_{\mathrm{ox}}}\right)}^2+{\left(1-\frac{C_{\max }}{C_{\mathrm{ox}}}\right)}^2\right]}$$

(5)

where A is the electrode area, C_ox is the gate oxide capacitance as defined in Equation (1), G_max is the peak value of G-V curve, and C_max is the capacitance corresponding to G_max at the same gate-applied voltage. The various parameter results discussed above are shown in

Table 1. The electrical parameters extracted from the fabricated MIS capacitors without and with a La₂O₃ interfacial passivation layer.

Sample	Cox (µF/cm2)	k	ΔVFB (mV)	Not (cm−2)	Dit (eV−1·cm−2)
S1	1.096	7.95	863	5.91 × 1012	1.13 × 1013
S2	1.438	11.10	174	1.56 × 1012	4.97 × 1012

. For the fabricated MIS capacitors without a La₂O₃ passivation layer, the value of D_it was about 1.13 × 10¹³ eV⁻¹·cm⁻². After the Ge surface passivation treatment using a La₂O₃ interlayer, the D_it value decreased evidently to ∼4.97 × 10¹² eV⁻¹·cm⁻², indicating that to some extent, the insertion of a La₂O₃ passivation layer inhibited the generation of interface traps, which gave an explanation to the pronounced weak anomalous hump tendency. It is worth noting that, the frequency dispersion phenomenon was also observed at the accumulation region of the C-V curves. It has been reported by Kouda et al. that the frequency-dependent variations in the dielectric constant of the gate stacks caused by oxygen vacancies should be responsible for the frequency dispersion phenomenon at the accumulation region [14,35]. As shown in Figure 4, the frequency dispersion phenomenon at the accumulation region became weaker after inserting a La₂O₃ interlayer, indicating that the introduction of this interlayer suppressed the generation of oxygen vacancies in the stack structures.

The contribution of the La₂O₃ interfacial passivation layer to the decrease in trapped oxide charges and interfacial traps could be explained as follows; when Al₂O₃ dielectrics were deposited on the Ge substrates without any passivation treatment, the outdiffusion of Ge atoms to the Al₂O₃ dielectric films generated unstable Ge oxides at the Al₂O₃/Ge interface. The quality of the interface between Ge and its oxides tends to deteriorate during the PDA process because the decomposition or desorption from GeO₂ to GeO following the reaction equation of GeO₂ + Ge → 2GeO leads to the formation of structural defects mainly consisting of dangling bonds and oxygen vacancies [36]. While after inserting the La₂O₃ interfacial passivation layer, La₂O₃ could react with the outdiffused Ge atoms to form the stable LaGeO_x compound, which would effectively suppress the generation of volatile GeO, contributing to the decrease of structural defects in the bulk of the insulator and/or in the interfacial region. As a result, the N_ot and D_it values were obviously decreased by inserting a La₂O₃ passivation layer of insulator/Ge interfaces, contributing to the suppression of hysteresis in dual-swept C-V curves and frequency dispersion in multi-frequency C-V curves.

Figure 5 shows the gate leakage current density of the fabricated MIS capacitors as a function of the gate-applied electrical field. The gate leakage current density for capacitors S1 and S2 were measured to be 1.92 × 10⁻⁴ and 1.29 × 10⁻⁵ A/cm² separately, when the gate-applied electrical field was 3 MV/cm. More than one order of magnitude decrease in the gate leakage current density was achieved after inserting a La₂O₃ passivation layer. Furthermore, it is worth noting that the gate insulator breakdown electric field of capacitor S2 (~7.07 MV/cm) was apparently higher than that of capacitor S1 (~5.86 MV/cm), which revealed that the inserted La₂O₃ passivation layer had a positive effect on the breakdown characteristics of the gate insulators. The improvements in gate leakage current density and gate insulator breakdown characteristics were suspected to benefit from the reduction of structural defects including dangling bonds and oxygen vacancies [37]. For the sample with a La₂O₃ passivation layer, less structural defects in the gate insulator meant a smaller possibility of creating a continuous chain connecting the gate electrode to the substrate semiconductor, contributing to the realization of lower gate leakage current density and higher insulator breakdown electric field [38].

4. Conclusions

The Ge surface engineering using La₂O₃ as a passivation layer was carried out and investigated systematically in this paper. The formation of a thermodynamically stable LaGeO_x interfacial layer effectively suppressed the desorption of volatile GeO, resulting in smaller N_ot and D_it values achieved after the insertion of a La₂O₃ passivation layer compared with the control sample. These improvements on the interfacial properties significantly weakened the hysteresis in dual-swept C-V curves and frequency dispersion in multi-frequency C-V curves. Besides, the gate leakage current and insulator breakdown characteristics for the MIS structure with La₂O₃ passivation were also improved.