Search Results (94)

Ultra-high sampling rates in coherent optical front-ends increasingly exceed the processing capabilities of real-time baseband processors, creating a bottleneck in coherent free-space optical communication systems. We propose a unified state-space framework to systematically parallelize digital signal processing (DSP) algorithms. This approach transforms an algorithm’s transfer function into a state-space representation from which a parallel architecture is derived through matrix operations, overcoming the complexity of traditional ad hoc methods. Crucially, our framework enables an analysis of parallelization-induced latency. We introduce the parallel equivalent delay (PED) metric and demonstrate that it introduces right-half-plane zeros into the loop’s transfer function, thereby fundamentally constraining stability. This analysis leads to the derivation of “Throughput–Bandwidth Product” (TBP), a constant that provides a design guideline linking maximum stable loop bandwidth to the parallelization factor. The framework’s efficacy is demonstrated by designing a parallel Costas carrier recovery loop. Simulations validate its performance, confirm the TBP limit, and show significant advantages over conventional feedforward estimators, especially in low-SNR conditions. Implementation results on a AMD XCVU13P FPGA demonstrate that the proposed 50-parallel architecture achieves a throughput of 15.625 Gsps at a clock frequency of 312.5 MHz with a logic utilization below 7%. The experimental results confirm the theoretical trade-off between throughput and loop bandwidth, verifying the proposed design methodology. Full article

You Only Look Once (YOLO) is a convolutional neural network-based object detection algorithm widely used in real-time vision applications. However, its high computational demand leads to significant power consumption and cost when deployed in graphics processing units. Field-programmable gate arrays offer a low-power alternative. However, their efficient implementation requires architecture-level optimization tailored to limited device resources. This study presents an optimized YOLOv2 accelerator for the Zynq-7000 system-on-chip (SoC). The design employs 16-bit integer quantization, a filter reuse structure, an input feature map reuse scheme using a line buffer, and tiling parameter optimization for the convolution and max pooling layers to maximize resource efficiency. In addition, a stall-based control mechanism is introduced to prevent structural hazards in the pipeline. The proposed accelerator was implemented on the Zynq-7000 SoC board, and a system-level evaluation confirmed a negligible accuracy drop of only 0.2% compared with the 32-bit floating-point baseline. Compared with previous YOLO accelerators on the same SoC, the design achieved up to 26% and 15% reductions in flip-flop and digital signal processor usage, respectively. This result demonstrates feasible deployment on XC7Z020 with DSP 57.27% and FF 16.55% utilization. Full article

In this work, a controller hardware-in-the-loop (CHIL) simulation of a grid-connected three-phase inverter equipped with an LCL filter is implemented using a real-time digital simulator (RTDS) as the plant and a digital signal processor (DSP) as the control hardware. This work identifies and discusses the critical aspects of the CHIL implementation process, emphasizing the relevance of the control delays that arise from sampling, computation, and pulse width modulation (PWM), which also adversely affect system stability, accuracy, and performance. Time and frequency domains are used to validate the modeling of the system, either to represent large-signal or small-signal models. This work shows multiple representations of the system under study: the fundamental frequency model, the switched model, and the switched model controlled by the DSP, are used to validate the nonlinear model, whereas the impedance-based modeling is followed to validate the linear representation. The results demonstrate a strong correlation among the models, confirming that the delay effects are accurately captured in the different simulation approaches. This comparison provides valuable insights into configuration practices that improve the fidelity of CHIL-based validation and supports impedance-based stability analysis in power electronic systems. The findings are particularly relevant for wideband modeling and real-time studies in electromagnetic transient analysis. Full article

This project presents the development of an open-source educational platform based on an automotive Electrically Excited Synchronous Machine (EESM) repurposed from a KIA Sportage mild-hybrid vehicle. The introduction provides an overview of hybrid drive systems and the primary configurations employed in automotive applications, including classifications based on power flow and the placement of electric motors. The focus is placed on the parallel hybrid configuration, where a belt-driven starter-generator assists the internal combustion engine (ICE). Due to the proprietary nature of the original control system, the unit was disassembled, and a custom control board was designed using a Texas Instruments C2000 Digital Signal Processor (DSP). The motor features a six-phase dual three-phase stator, offering improved torque smoothness, fault tolerance, and reduced current per phase. A compact Anisotropic Magneto Resistive (AMR) position sensor was implemented for position and speed measurements. Current sensing was achieved using both direct and magnetic field-based methods. The control algorithm was verified on a modified six-phase inverter under simulated vehicle conditions utilizing a dynamometer. Results confirmed reliable operation and validated the control approach. Future work will involve complete hardware testing with the new control board to finalize the platform as a flexible, open-source tool for research and education in hybrid drive technologies. Full article

The utilization of electric vehicles (EVs) has grown significantly and continuously in recent years, encouraging the creation of new implementation opportunities. The battery electric vehicle (BEV) charging system can be effectively used during peak load periods, for voltage regulation, and for the improvement of power system stability within the smart grid. It provides an efficient bidirectional interface for charging the battery from the grid and discharging the battery into the grid. These two operation modes are referred to as grid-to-vehicle (G2V) and vehicle-to-grid (V2G), respectively. The management of power flow in both directions is highly complex and sensitive, which requires employing a robust control scheme. In this paper, an Integral Fast Terminal Synergetic Control Scheme (IFTSC) is designed to control the BEV charger system through accurately tracking the required current and voltage in both G2V and V2G system modes. Moreover, the Black-Winged Kite Algorithm is introduced to select the optimal gains of the proposed IFTS control scheme. The system stability is checked using the Lyapunov stability method. Comprehensive simulations using MATLAB/Simulink are conducted to assess the safety and efficacy of the suggested optimal IFTSC in comparison with IFTSC, optimal integral synergetic, and conventional PID controllers. Furthermore, processor-in-the-loop (PIL) co-simulation is carried out for the studied system using the C2000 launchxl-f28379d digital signal processing (DSP) board to confirm the practicability and effectiveness of the proposed OIFTS. The analysis of the obtained quantitative comparison proves that the proposed optimal IFTSC provides higher control performance under several critical testing scenarios. Full article

Convolutional neural networks (CNNs) are widely used in geotechnical engineering. Real-time detection in complex geological environments, combined with the strict power constraints of embedded devices, makes Field-Programmable Gate Array (FPGA) platforms ideal for accelerating CNNs. Conventional parallelization strategies in FPGA-based accelerators often result in imbalanced resource utilization and computational inefficiency due to varying kernel sizes. To address this issue, we propose a customized heterogeneous hybrid parallel strategy and refine the bit-splitting approach for Digital Signal Processor (DSP) resources, improving timing performance and reducing Look-Up Table (LUT) consumption. Using this strategy, we deploy the lightweight YOLOv5n network on an FPGA platform, creating a high-speed, low-power subsurface geotechnical defect-detection system. A layer-wise quantization strategy reduces the model size with negligible mean average precision (mAP) loss. Operating at 300 MHz, the system reduces LUT usage by 33%, achieves a peak throughput of 328.25 GOPs in convolutional layers, and an overall throughput of 157.04 GOPs, with a power consumption of 9.4 W and energy efficiency of 16.7 GOPs/W. This implementation demonstrates more balanced performance improvements than existing solutions. Full article

This work devised an on-device learning approach to self-calibrate Micro-Electro-Mechanical Systems-based Inertial Measurement Units (MEMS-IMUs), integrating a digital signal processor (DSP), an accelerometer, and a gyroscope in the same package. The accelerometer and gyroscope stream their data in real time to the DSP, which runs artificial intelligence (AI) workloads. The real-time sensor data are subject to errors, such as time-varying bias and thermal stress. To compensate for these drifts, the traditional calibration method based on a linear model is applicable, and unfortunately, it does not work with nonlinear errors. The algorithm devised by this study to reduce such errors adopts Radial Basis Function Neural Networks (RBF-NNs). This method does not rely on the classical adoption of the backpropagation algorithm. Due to its low complexity, it is deployable using kibyte memory and in software runs on the DSP, thus performing interleaved in-sensor learning and inference by itself. This avoids using any off-package computing processor. The learning process is performed periodically to achieve consistent sensor recalibration over time. The devised solution was implemented in both 32-bit floating-point data representation and 16-bit quantized integer version. Both of these were deployed into the Intelligent Sensor Processing Unit (ISPU), integrated into the LSM6DSO16IS Inertial Measurement Unit (IMU), which is a programmable 5–10 MHz DSP on which the programmer can compile and execute AI models. It integrates 32 KiB of program RAM and 8 KiB of data RAM. No permanent memory is integrated into the package. The two (fp32 and int16) RBF-NN models occupied less than 21 KiB out of the 40 available, working in real-time and independently in the sensor package. The models, respectively, compensated between 46% and 95% of the accelerometer measurement error and between 32% and 88% of the gyroscope measurement error. Finally, it has also been used for attitude estimation of a micro aerial vehicle (MAV), achieving an error of only 2.84°. Full article

This paper proposes a novel maximum power point tracking (MPPT) strategy for renewable energy systems using Input Impedance Control (I²C) in power electronic converters, combined with an adaptive nonlinear controller. Unlike conventional voltage- or current-based methods, the I²C-MPPT approach leverages the maximum power transfer theorem by dynamically matching the converter’s equivalent input impedance to the source’s internal impedance. The adaptive nonlinear controller, designed using the Lyapunov stability theory, estimates system uncertainties and provides superior performance compared to traditional Proportional–Integral (PI) controllers. The proposed approach is validated through both simulations in MATLAB and experimental implementation using a Digital Signal Processor (DSP)-based controller. Practical results confirm the controller’s effectiveness in maintaining maximum power transfer under dynamic variations in source parameters, demonstrating improved settling time and robust operation. These findings underscore the potential of the I²C approach for enhancing the efficiency and reliability of renewable energy systems. Full article

Accurate and reliable estimation of the state of charge (SOC) of lithium-ion batteries is essential for the performance and safety of battery management systems (BMS) in applications such as electric vehicles and energy storage systems. However, there is a lack of comprehensive comparative studies evaluating different SOC estimation methods under standardized conditions. In this paper, we address this gap by providing a comprehensive, objective comparison of various Kalman and H-Infinity filter variants for battery SOC estimation, utilizing a detailed validation method based on well-defined criteria. The main contributions of this work are: (1) Implementation of multiple filter variants using a consistent equivalent circuit battery model; (2) Development of a standardized validation method for objective performance evaluation; (3) Detailed mathematical formulations enhancing reproducibility; (4) Evaluation of computational efficiency on a digital signal processor (DSP) to provide practical insights for real-time applications. Our findings reveal that while neither filter type is universally superior, the Extended Kalman Filter (EKF) and H-Infinity Filter (HIF) offer a solid balance between estimation accuracy and computational load, making them reliable choices for general applications. This work advances the understanding of SOC estimation methods and aids practitioners in balancing accuracy and computational efficiency for real-world applications. Full article

Fault diagnosis in power converters is essential for keeping electrical systems stable, efficient and long-lasting. Park’s Vector Transform, discrete wavelet transform, Artificial Neural Network, Fuzzy Logic and other methods are used to diagnose faults in the power converter in both single and multiple open switch situations. These methods are implemented on the digital signal processor or controller, which needs additional hardware and consumes more processing time. This paper presents a hardware-based open switch fault diagnostic method in a 3ϕ voltage source inverter to minimize fault diagnosis time and cost. An innovative hardware-based approach that utilizes a single neuron for open switch fault diagnosis in 3ϕ voltage source inverters was successfully implemented without using a digital signal processor or controller. A gradient descent algorithm calculates the weight and bias values of a single processing neuron. Furthermore, a high-speed multiplier and adder circuit seamlessly integrate with the single processing neuron, enabling rapid real-time fault diagnosis. This method is capable of diagnosing single and multiple switch open circuit faults in switching devices under variable load conditions at different frequencies. The proposed system ensures good effectiveness and resistivity, detecting faults in less than one cycle with low implementation effort and no tuning or threshold dependence. It achieves 98% accuracy, 96% precision and 95% recall, with a 2% false positive rate. Unlike traditional methods, it eliminates DSP/controller dependency by using a single neuron-based processing circuit, reducing cost and improving real-time fault diagnosis in three-phase voltage source inverters. Full article

The You Only Look Once (YOLO) object detection network has garnered widespread adoption in various industries, owing to its superior inference speed and robust detection capabilities. This model has proven invaluable in automating production processes such as material processing, machining, and quality inspection. However, as market competition intensifies, there is a constant demand for higher detection speed and accuracy. Current FPGA accelerators based on 8-bit quantization have struggled to meet these increasingly stringent performance requirements. In response, we present a novel 4-bit quantization-based neural network accelerator for the YOLOv5 model, designed to enhance real-time processing capabilities while maintaining high detection accuracy. To achieve effective model compression, we introduce an optimized quantization scheme that reduces the bit-width of the entire YOLO network—including the first layer—to 4 bits, with only a 1.5% degradation in mean Average Precision (mAP). For the hardware implementation, we propose a unified Digital Signal Processor (DSP) packing scheme, coupled with a novel parity adder tree architecture that accommodates the proposed quantization strategies. This approach efficiently reduces on-chip DSP utilization by 50%, offering a significant improvement in performance and resource efficiency. Experimental results show that the industrial object detection system based on the proposed FPGA accelerator achieves a throughput of 808.6 GOPS and an efficiency of 0.49 GOPS/DSP for YOLOv5s on the ZCU102 board, which is 29% higher than a commercial FPGA accelerator design (Xilinx’s Vitis AI). Full article

In the modern technological era of sophisticated applications and high-quality communications, a platform of clever strategy and quickly updated systems is needed. It should be capable of withstanding the fastest emerging problems like signal attenuation and hostile actions intended to harm the whole network. The main contributions of this work are the production of an OFDM system (with low cost) that can sustain high-speed communications and be easily adjusted with new integrated code while exhibiting the feasibility of implementing a transmitter–receiver system in the same DSP and demonstrating the holistic approach with the qualitative integration of such an architecture in a warfare scenario. Specifically, in this research, the point of view is toward three facts. The first is to show a method of quick self-checking the operational status of a digital signal processor (DSP) platform and then the pedagogical issues of how to fast check and implement an updated code inside DSPs through simple schematics. The second point is to present the prototype system that can easily be programmed using a graphical user interface (GUI) and can change its properties (such as the transmitted modulated sinusoids—orthogonal frequency division multiplexing subcarriers). Alongside the presentation, the measurements are presented and discussed. These were acquired with the use of an oscilloscope and spectrum analyzer. The third point is to qualitatively show the application of such a system inside a modern warfare environment and to recommend various potential system responses according to the development of such a platform of reconfigurable implemented OFDM systems. The implementation was performed for two types of systems: (1) transmitter and (2) transmitter–receiver system. Notably, the system acts quickly with a delay of about 1 msec in the case of transmitting and receiving in the same DSP, suggesting excellent future results under real conditions. Full article

In recent years, the penetration of wind power generation has been growing steadily to adapt to the modern trend of boosting renewable energy (RE)-based power generation. However, the dynamic power flow of wind turbine generators (WTGs) is unpredictable and can have a negative impact on existing power grids. To solve this problem efficiently, this paper presents a multifunctional WTG intelligent compensator (WTGIC) for the advanced power management and compensation of power systems embedded with WTGs. The proposed WTGIC consists of a power semiconductor device (PSD)-based bidirectional three-phase inverter module and an energy storage unit (ESU). In order to reduce system costs and improve reliability, efficiency, and flexibility, various control functions and algorithms are integrated via a modularized all-digital control scheme. In this paper, the configuration of the proposed WTGIC is first introduced, and then the operating modes and related compensation and control functions are addressed. An online efficiency optimization algorithm is proposed, and the required controllers are designed and implemented. The designed functions of the proposed WTGIC include high-efficiency charging/discharging of the ESU, real-time power quality (PQ) compensation, and high-efficiency power smoothing of the WTGs. The feasibility and effectiveness of the proposed WTGIC are verified using case studies with simulations in the Powersim (PSIM) environment and the implementation of a small-scale hardware experimental system with TI’s digital signal processor (DSP) TI28335 as the main controller. Full article

Auscultation of heart sounds is important to perform cardiovascular assessment. External noises may limit heart sound perception. In addition, heart sound bandwidth is concentrated at very low frequencies, where the human ear has poor sensitivity. Therefore, the acoustic perception of the operator can be significantly improved by shifting the heart sound spectrum toward higher frequencies. This study proposes a real-time frequency shifter based on the Hilbert transform. Key system components are the Hilbert transformer implemented as a Finite Impulse Response (FIR) filter, and a Direct Digital Frequency Synthesizer (DDFS), which allows agile modification of the frequency shift. The frequency shifter has been implemented on a VLIW Digital Signal Processor (DSP) by devising a novel piecewise quadratic approximation technique for efficient DDFS implementation. The performance has been compared with other DDFS implementations both considering piecewise linear technique and sine/cosine standard library functions of the DSP. Piecewise techniques allow a more than 50% reduction in execution time compared to the DSP library. Piecewise quadratic technique also allows a more than 50% reduction in total required memory size in comparison to the piecewise linear. The theoretical analysis of the dynamic power dissipation exhibits a more than 20% reduction using piecewise techniques with respect to the DSP library. The real-time operation has been also verified on the DSK6713 rapid prototyping board by Texas Instruments C6713 DSP. Audiologic tests have also been performed to assess the actual improvement of heart sound perception. To this aim, heart sound recordings were corrupted by additive white Gaussian noise, crowded street noise, and helicopter noise, with different signal-to-noise ratios. All recordings were collected from public databases. Statistical analyses of the audiological test results confirm that the proposed approach provides a clear improvement in heartbeat perception in noisy environments. Full article

Modern processors have improved performance but still face challenges such as power consumption, storage limitations, and the need for faster processing. The 16-bit Digital Signal Processors (DSPs) accelerate DSP applications by significantly enhancing speed and performance for tasks including audio processing, telecommunications, image and video processing, wireless communication, and consumer electronics. This paper presents a novel technique for accelerating DSP applications on a 16-bit processor by combining two methods: Block Random Access Memory (BRAM) and Distributed Arithmetic (DA). Integrating BRAM as a replacement for conventional RAM minimizes timing and critical route delays, improving processor efficiency and performance. Furthermore, the Distributed Arithmetic approach enhances performance and efficiency by utilizing precomputed lookup tables to expedite multiplication operations within the Arithmetic and Logic Unit (ALU). We use the Xilinx Vivado tool, a robust development environment for FPGA-based systems, for the design process and execute the hardware implementation using the Genesys2 Kintex board. The proposed work produces improved efficiency with a cycle per instruction of 2, where the delay is 2.009 ns, the critical path delay is 8.182 ns, and the power consumption is 4 mW. Full article